#define CHIPREV_ID_5750_A0 0x4000
#define CHIPREV_ID_5750_A1 0x4001
#define CHIPREV_ID_5750_A3 0x4003
-#define CHIPREV_ID_5750_C2 0x4202
#define CHIPREV_ID_5752_A0_HW 0x5000
#define CHIPREV_ID_5752_A0 0x6000
#define CHIPREV_ID_5752_A1 0x6001
#define ASIC_REV_5752 0x06
#define ASIC_REV_5780 0x08
#define ASIC_REV_5714 0x09
-#define ASIC_REV_5755 0x0a
-#define ASIC_REV_5787 0x0b
#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
#define CHIPREV_5700_AX 0x70
#define CHIPREV_5700_BX 0x71
#define RX_MODE_PROMISC 0x00000100
#define RX_MODE_NO_CRC_CHECK 0x00000200
#define RX_MODE_KEEP_VLAN_TAG 0x00000400
-#define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
#define MAC_RX_STATUS 0x0000046c
#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
#define RX_STATUS_XOFF_RCVD 0x00000002
#define RCVLPC_STATSCTRL_ENABLE 0x00000001
#define RCVLPC_STATSCTRL_FASTUPD 0x00000002
#define RCVLPC_STATS_ENABLE 0x00002018
-#define RCVLPC_STATSENAB_DACK_FIX 0x00040000
#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
#define RCVLPC_STATS_INCMASK 0x0000201c
/* 0x2020 --> 0x2100 unused */
#define GRC_LCLCTRL_CLEARINT 0x00000002
#define GRC_LCLCTRL_SETINT 0x00000004
#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
-#define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
#define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
#define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
#define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
#define GRC_MDI_CTRL 0x00006844
#define GRC_SEEPROM_DELAY 0x00006848
/* 0x684c --> 0x6c00 unused */
-#define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
/* 0x6c00 --> 0x7000 unused */
#define FLASH_5752VENDOR_ST_M45PE10 0x02400000
#define FLASH_5752VENDOR_ST_M45PE20 0x02400002
#define FLASH_5752VENDOR_ST_M45PE40 0x02400001
-#define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
-#define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
-#define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
-#define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
-#define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
-#define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
-#define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
-#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
-#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
-#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
#define FLASH_5752PAGE_SIZE_256 0x00000000
#define FLASH_5752PAGE_SIZE_512 0x10000000
/* SMP locking strategy:
*
- * lock: Held during reset, PHY access, timer, and when
- * updating tg3_flags and tg3_flags2.
+ * lock: Held during all operations except TX packet
+ * processing.
*
- * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
- * netif_tx_lock when it needs to call
- * netif_wake_queue.
+ * tx_lock: Held during tg3_start_xmit and tg3_tx
*
* Both of these locks are to be held with BH safety.
- *
- * Because the IRQ handler, tg3_poll, and tg3_start_xmit
- * are running lockless, it is necessary to completely
- * quiesce the chip with tg3_netif_stop and tg3_full_lock
- * before reconfiguring the device.
- *
- * indirect_lock: Held when accessing registers indirectly
- * with IRQ disabling.
*/
spinlock_t lock;
spinlock_t indirect_lock;
u32 tx_cons;
u32 tx_pending;
+ spinlock_t tx_lock;
+
struct tg3_tx_buffer_desc *tx_ring;
struct tx_ring_info *tx_buffers;
dma_addr_t tx_desc_mapping;
struct tg3_rx_buffer_desc *rx_std;
struct ring_info *rx_std_buffers;
dma_addr_t rx_std_mapping;
- u32 rx_std_max_post;
struct tg3_rx_buffer_desc *rx_jumbo;
struct ring_info *rx_jumbo_buffers;
#define TG3_FLAG_ENABLE_ASF 0x00000020
#define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040
#define TG3_FLAG_POLL_SERDES 0x00000080
+#if defined(CONFIG_X86)
#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
+#else
+#define TG3_FLAG_MBOX_WRITE_REORDER 0 /* disables code too */
+#endif
#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
#define TG3_FLAG_WOL_SPEED_100MB 0x00000400
#define TG3_FLAG_WOL_ENABLE 0x00000800
#define TG3_FLAG_PCIX_MODE 0x00020000
#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
#define TG3_FLAG_PCI_32BIT 0x00080000
-#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
-#define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
+#define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000
+#define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000
#define TG3_FLAG_SERDES_WOL_CAP 0x00400000
#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
#define TG3_FLAG_10_100_ONLY 0x01000000
#define TG3_FLAG_INIT_COMPLETE 0x80000000
u32 tg3_flags2;
#define TG3_FLG2_RESTART_TIMER 0x00000001
-#define TG3_FLG2_HW_TSO_1_BUG 0x00000002
+#define TG3_FLG2_SUN_570X 0x00000002
#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
#define TG3_FLG2_IS_5788 0x00000008
#define TG3_FLG2_MAX_RXPEND_64 0x00000010
#define TG3_FLG2_PHY_SERDES 0x00002000
#define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000
#define TG3_FLG2_FLASH 0x00008000
-#define TG3_FLG2_HW_TSO_1 0x00010000
+#define TG3_FLG2_HW_TSO 0x00010000
#define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
#define TG3_FLG2_5705_PLUS 0x00040000
#define TG3_FLG2_5750_PLUS 0x00080000
#define TG3_FLG2_PARALLEL_DETECT 0x01000000
#define TG3_FLG2_ICH_WORKAROUND 0x02000000
#define TG3_FLG2_5780_CLASS 0x04000000
-#define TG3_FLG2_HW_TSO_2 0x08000000
-#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
-#define TG3_FLG2_1SHOT_MSI 0x10000000
-#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
-#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
u32 split_mode_max_reqs;
#define SPLIT_MODE_5704_MAX_REQ 3
#define PHY_ID_BCM5752 0x60008100
#define PHY_ID_BCM5714 0x60008340
#define PHY_ID_BCM5780 0x60008350
-#define PHY_ID_BCM5755 0xbc050cc0
-#define PHY_ID_BCM5787 0xbc050ce0
#define PHY_ID_BCM8002 0x60010140
#define PHY_ID_INVALID 0xffffffff
#define PHY_ID_REV_MASK 0x0000000f
u32 led_ctrl;
char board_part_number[24];
- char fw_ver[16];
u32 nic_sram_data_cfg;
u32 pci_clock_ctrl;
struct pci_dev *pdev_peer;
(X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
(X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
(X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
- (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
- (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM8002)
+ (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM8002)
struct tg3_hw_stats *hw_stats;
dma_addr_t stats_mapping;
git://git.onelab.eu / linux-2.6.git / blobdiff