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vserver 2.0 rc7
[linux-2.6.git] / drivers / net / tg3.h
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 629f189..993f84c 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -125,6 +125,9 @@
 #define  CHIPREV_ID_5750_A0             0x4000
 #define  CHIPREV_ID_5750_A1             0x4001
 #define  CHIPREV_ID_5750_A3             0x4003
+#define  CHIPREV_ID_5752_A0_HW          0x5000
+#define  CHIPREV_ID_5752_A0             0x6000
+#define  CHIPREV_ID_5752_A1             0x6001
 #define  GET_ASIC_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                         0x07
 #define   ASIC_REV_5701                         0x00
@@ -132,6 +135,7 @@
 #define   ASIC_REV_5704                         0x02
 #define   ASIC_REV_5705                         0x03
 #define   ASIC_REV_5750                         0x04
+#define   ASIC_REV_5752                         0x06
 #define  GET_CHIP_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX               0x70
 #define   CHIPREV_5700_BX               0x71
@@ -140,6 +144,8 @@
 #define   CHIPREV_5703_AX               0x10
 #define   CHIPREV_5704_AX               0x20
 #define   CHIPREV_5704_BX               0x21
+#define   CHIPREV_5750_AX               0x40
+#define   CHIPREV_5750_BX               0x41
 #define  GET_METAL_REV(CHIP_REV_ID)    ((CHIP_REV_ID) & 0xff)
 #define   METAL_REV_A0                  0x00
 #define   METAL_REV_A1                  0x01
@@ -870,10 +876,12 @@
 #define  HOSTCC_STATUS_ERROR_ATTN       0x00000004
 #define HOSTCC_RXCOL_TICKS             0x00003c08
 #define  LOW_RXCOL_TICKS                0x00000032
+#define  LOW_RXCOL_TICKS_CLRTCKS        0x00000014
 #define  DEFAULT_RXCOL_TICKS            0x00000048
 #define  HIGH_RXCOL_TICKS               0x00000096
 #define HOSTCC_TXCOL_TICKS             0x00003c0c
 #define  LOW_TXCOL_TICKS                0x00000096
+#define  LOW_TXCOL_TICKS_CLRTCKS        0x00000048
 #define  DEFAULT_TXCOL_TICKS            0x0000012c
 #define  HIGH_TXCOL_TICKS               0x00000145
 #define HOSTCC_RXMAX_FRAMES            0x00003c10
@@ -886,8 +894,10 @@
 #define  HIGH_TXMAX_FRAMES              0x00000052
 #define HOSTCC_RXCOAL_TICK_INT         0x00003c18
 #define  DEFAULT_RXCOAL_TICK_INT        0x00000019
+#define  DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
 #define HOSTCC_TXCOAL_TICK_INT         0x00003c1c
 #define  DEFAULT_TXCOAL_TICK_INT        0x00000019
+#define  DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
 #define HOSTCC_RXCOAL_MAXF_INT         0x00003c20
 #define  DEFAULT_RXCOAL_MAXF_INT        0x00000005
 #define HOSTCC_TXCOAL_MAXF_INT         0x00003c24
@@ -1305,6 +1315,9 @@
 #define  GRC_LCLCTRL_CLEARINT          0x00000002
 #define  GRC_LCLCTRL_SETINT            0x00000004
 #define  GRC_LCLCTRL_INT_ON_ATTN       0x00000008
+#define  GRC_LCLCTRL_GPIO_INPUT3       0x00000020
+#define  GRC_LCLCTRL_GPIO_OE3          0x00000040
+#define  GRC_LCLCTRL_GPIO_OUTPUT3      0x00000080
 #define  GRC_LCLCTRL_GPIO_INPUT0       0x00000100
 #define  GRC_LCLCTRL_GPIO_INPUT1       0x00000200
 #define  GRC_LCLCTRL_GPIO_INPUT2       0x00000400
@@ -1390,6 +1403,20 @@
 #define  FLASH_VENDOR_SAIFUN            0x01000003
 #define  FLASH_VENDOR_SST_SMALL                 0x00000001
 #define  FLASH_VENDOR_SST_LARGE                 0x02000001
+#define  NVRAM_CFG1_5752VENDOR_MASK     0x03c00003
+#define  FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ    0x00000000
+#define  FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ   0x02000000
+#define  FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED  0x02000003
+#define  FLASH_5752VENDOR_ST_M45PE10    0x02400000
+#define  FLASH_5752VENDOR_ST_M45PE20    0x02400002
+#define  FLASH_5752VENDOR_ST_M45PE40    0x02400001
+#define  NVRAM_CFG1_5752PAGE_SIZE_MASK  0x70000000
+#define  FLASH_5752PAGE_SIZE_256        0x00000000
+#define  FLASH_5752PAGE_SIZE_512        0x10000000
+#define  FLASH_5752PAGE_SIZE_1K                 0x20000000
+#define  FLASH_5752PAGE_SIZE_2K                 0x30000000
+#define  FLASH_5752PAGE_SIZE_4K                 0x40000000
+#define  FLASH_5752PAGE_SIZE_264        0x50000000
 #define NVRAM_CFG2                     0x00007018
 #define NVRAM_CFG3                     0x0000701c
 #define NVRAM_SWARB                    0x00007020
@@ -1516,6 +1543,7 @@
 #define  MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
 
 #define MII_TG3_EXT_CTRL               0x10 /* Extended control register */
+#define  MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
 #define  MII_TG3_EXT_CTRL_LNK3_LED_MODE        0x0002
 #define  MII_TG3_EXT_CTRL_TBI          0x8000
 
@@ -1548,20 +1576,6 @@
 #define MII_TG3_INT_DUPLEXCHG          0x0008
 #define MII_TG3_INT_ANEG_PAGE_RX       0x0400
 
-/* XXX Add this to mii.h */
-#ifndef ADVERTISE_PAUSE
-#define ADVERTISE_PAUSE_CAP            0x0400
-#endif
-#ifndef ADVERTISE_PAUSE_ASYM
-#define ADVERTISE_PAUSE_ASYM           0x0800
-#endif
-#ifndef LPA_PAUSE
-#define LPA_PAUSE_CAP                  0x0400
-#endif
-#ifndef LPA_PAUSE_ASYM
-#define LPA_PAUSE_ASYM                 0x0800
-#endif
-
 /* There are two ways to manage the TX descriptors on the tigon3.
  * Either the descriptors are in host DMA'able memory, or they
  * exist only in the cards on-chip SRAM.  All 16 send bds are under
@@ -2013,6 +2027,7 @@ struct tg3 {
 
        struct tg3_hw_status            *hw_status;
        dma_addr_t                      status_mapping;
+       u32                             last_tag;
 
        u32                             msg_enable;
 
@@ -2058,6 +2073,7 @@ struct tg3 {
 
        u32                             rx_offset;
        u32                             tg3_flags;
+#define TG3_FLAG_TAGGED_STATUS         0x00000001
 #define TG3_FLAG_TXD_MBOX_HWBUG                0x00000002
 #define TG3_FLAG_RX_CHECKSUMS          0x00000004
 #define TG3_FLAG_USE_LINKCHG_REG       0x00000008
@@ -2110,6 +2126,10 @@ struct tg3 {
 #define TG3_FLG2_FLASH                 0x00008000
 #define TG3_FLG2_HW_TSO                        0x00010000
 #define TG3_FLG2_SERDES_PREEMPHASIS    0x00020000
+#define TG3_FLG2_5705_PLUS             0x00040000
+#define TG3_FLG2_5750_PLUS             0x00080000
+#define TG3_FLG2_PROTECTED_NVRAM       0x00100000
+#define TG3_FLG2_USING_MSI             0x00200000
 
        u32                             split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ                3
@@ -2155,6 +2175,7 @@ struct tg3 {
 #define PHY_ID_BCM5704                 0x60008190
 #define PHY_ID_BCM5705                 0x600081a0
 #define PHY_ID_BCM5750                 0x60008180
+#define PHY_ID_BCM5752                 0x60008100
 #define PHY_ID_BCM8002                 0x60010140
 #define PHY_ID_INVALID                 0xffffffff
 #define PHY_ID_REV_MASK                        0x0000000f
@@ -2210,7 +2231,7 @@ struct tg3 {
 
 #define SST_25VF0X0_PAGE_SIZE          4098
 
-
+       struct ethtool_coalesce         coal;
 };
 
 #endif /* !(_T3_H) */
linux-2.6