#include <asm/page.h>
#include <asm/system.h>
#include <asm/io.h>
-#include <asm/irq.h>
#include <asm/hardware.h>
#include "gsc.h"
spinlock_t dinosaur_pen;
unsigned long txn_addr; /* EIR addr to generate interrupt */
u32 txn_data; /* EIR data assign to each dino */
- int irq; /* Virtual IRQ dino uses */
- struct irq_region *dino_region; /* region for this Dino */
-
- u32 imr; /* IRQ's which are enabled */
+ u32 imr; /* IRQ's which are enabled */
+ int global_irq[12]; /* map IMR bit to global irq */
#ifdef DINO_DEBUG
- unsigned int dino_irr0; /* save most recent IRQ line stat */
+ unsigned int dino_irr0; /* save most recent IRQ line stat */
#endif
};
struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
- unsigned long base_addr = d->hba.base_addr;
+ void __iomem *base_addr = d->hba.base_addr;
unsigned long flags;
spin_lock_irqsave(&d->dinosaur_pen, flags);
/* tell HW which CFG address */
- gsc_writel(v, base_addr + DINO_PCI_ADDR);
+ __raw_writel(v, base_addr + DINO_PCI_ADDR);
/* generate cfg read cycle */
if (size == 1) {
- *val = gsc_readb(base_addr + DINO_CONFIG_DATA + (where & 3));
+ *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3));
} else if (size == 2) {
- *val = le16_to_cpu(gsc_readw(base_addr +
- DINO_CONFIG_DATA + (where & 2)));
+ *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2));
} else if (size == 4) {
- *val = le32_to_cpu(gsc_readl(base_addr + DINO_CONFIG_DATA));
+ *val = readl(base_addr + DINO_CONFIG_DATA);
}
spin_unlock_irqrestore(&d->dinosaur_pen, flags);
struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
- unsigned long base_addr = d->hba.base_addr;
+ void __iomem *base_addr = d->hba.base_addr;
unsigned long flags;
spin_lock_irqsave(&d->dinosaur_pen, flags);
/* avoid address stepping feature */
- gsc_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR);
- gsc_readl(base_addr + DINO_CONFIG_DATA);
+ __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR);
+ __raw_readl(base_addr + DINO_CONFIG_DATA);
/* tell HW which CFG address */
- gsc_writel(v, base_addr + DINO_PCI_ADDR);
+ __raw_writel(v, base_addr + DINO_PCI_ADDR);
/* generate cfg read cycle */
if (size == 1) {
- gsc_writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3));
+ writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3));
} else if (size == 2) {
- gsc_writew(cpu_to_le16(val),
- base_addr + DINO_CONFIG_DATA + (where & 2));
+ writew(val, base_addr + DINO_CONFIG_DATA + (where & 2));
} else if (size == 4) {
- gsc_writel(cpu_to_le32(val), base_addr + DINO_CONFIG_DATA);
+ writel(val, base_addr + DINO_CONFIG_DATA);
}
spin_unlock_irqrestore(&d->dinosaur_pen, flags);
* I/O port instead of MMIO.
*/
-#define cpu_to_le8(x) (x)
-#define le8_to_cpu(x) (x)
-
#define DINO_PORT_IN(type, size, mask) \
static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \
{ \
unsigned long flags; \
spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
/* tell HW which IO Port address */ \
- gsc_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
+ __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
/* generate I/O PORT read cycle */ \
- v = gsc_read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
+ v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
- return le##size##_to_cpu(v); \
+ return v; \
}
DINO_PORT_IN(b, 8, 3)
unsigned long flags; \
spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
/* tell HW which IO port address */ \
- gsc_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
+ __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
/* generate cfg write cycle */ \
- gsc_write##type(cpu_to_le##size(val), d->base_addr+DINO_IO_DATA+(addr&mask)); \
+ write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \
spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
}
.outl = dino_out32
};
-static void
-dino_mask_irq(void *irq_dev, int irq)
+static void dino_disable_irq(unsigned int irq)
{
- struct dino_device *dino_dev = DINO_DEV(irq_dev);
+ struct dino_device *dino_dev = irq_desc[irq].handler_data;
+ int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, irq);
DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, irq_dev, irq);
- if (NULL == irq_dev || irq > DINO_IRQS || irq < 0) {
- printk(KERN_WARNING "%s(0x%lx, %d) - not a dino irq?\n",
- __FUNCTION__, (long) irq_dev, irq);
- BUG();
- } else {
- /*
- ** Clear the matching bit in the IMR register
- */
- dino_dev->imr &= ~(DINO_MASK_IRQ(irq));
- gsc_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
- }
+ /* Clear the matching bit in the IMR register */
+ dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq));
+ __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
}
-
-static void
-dino_unmask_irq(void *irq_dev, int irq)
+static void dino_enable_irq(unsigned int irq)
{
- struct dino_device *dino_dev = DINO_DEV(irq_dev);
+ struct dino_device *dino_dev = irq_desc[irq].handler_data;
+ int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, irq);
u32 tmp;
DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, irq_dev, irq);
- if (NULL == irq_dev || irq > DINO_IRQS) {
- printk(KERN_WARNING "%s(): %d not a dino irq?\n",
- __FUNCTION__, irq);
- BUG();
- return;
- }
+ /*
+ ** clear pending IRQ bits
+ **
+ ** This does NOT change ILR state!
+ ** See comment below for ILR usage.
+ */
+ __raw_readl(dino_dev->hba.base_addr+DINO_IPR);
/* set the matching bit in the IMR register */
- dino_dev->imr |= DINO_MASK_IRQ(irq); /* used in dino_isr() */
- gsc_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
+ dino_dev->imr |= DINO_MASK_IRQ(local_irq); /* used in dino_isr() */
+ __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
/* Emulate "Level Triggered" Interrupt
** Basically, a driver is blowing it if the IRQ line is asserted
** dino_isr() will read IPR and find nothing. But then catch this
** when it also checks ILR.
*/
- tmp = gsc_readl(dino_dev->hba.base_addr+DINO_ILR);
- if (tmp & DINO_MASK_IRQ(irq)) {
+ tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR);
+ if (tmp & DINO_MASK_IRQ(local_irq)) {
DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n",
__FUNCTION__, tmp);
gsc_writel(dino_dev->txn_data, dino_dev->txn_addr);
}
}
-
-
-static void
-dino_enable_irq(void *irq_dev, int irq)
+static unsigned int dino_startup_irq(unsigned int irq)
{
- struct dino_device *dino_dev = DINO_DEV(irq_dev);
-
- /*
- ** clear pending IRQ bits
- **
- ** This does NOT change ILR state!
- ** See comments in dino_unmask_irq() for ILR usage.
- */
- gsc_readl(dino_dev->hba.base_addr+DINO_IPR);
-
- dino_unmask_irq(irq_dev, irq);
+ dino_enable_irq(irq);
+ return 0;
}
-
-static struct irq_region_ops dino_irq_ops = {
- .disable_irq = dino_mask_irq, /* ??? */
- .enable_irq = dino_enable_irq,
- .mask_irq = dino_mask_irq,
- .unmask_irq = dino_unmask_irq
+static struct hw_interrupt_type dino_interrupt_type = {
+ .typename = "GSC-PCI",
+ .startup = dino_startup_irq,
+ .shutdown = dino_disable_irq,
+ .enable = dino_enable_irq,
+ .disable = dino_disable_irq,
+ .ack = no_ack_irq,
+ .end = no_end_irq,
};
static irqreturn_t
dino_isr(int irq, void *intr_dev, struct pt_regs *regs)
{
- struct dino_device *dino_dev = DINO_DEV(intr_dev);
+ struct dino_device *dino_dev = intr_dev;
u32 mask;
int ilr_loop = 100;
- extern void do_irq(struct irqaction *a, int i, struct pt_regs *p);
-
/* read and acknowledge pending interrupts */
#ifdef DINO_DEBUG
dino_dev->dino_irr0 =
#endif
- mask = gsc_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK;
-
-ilr_again:
- while (mask)
- {
- int irq;
-
- irq = __ffs(mask);
+ mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK;
- mask &= ~(1<<irq);
+ if (mask == 0)
+ return IRQ_NONE;
- DBG(KERN_WARNING "%s(%x, %p) mask %0x\n",
+ilr_again:
+ do {
+ int local_irq = __ffs(mask);
+ int irq = dino_dev->global_irq[local_irq];
+ DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n",
__FUNCTION__, irq, intr_dev, mask);
- do_irq(&dino_dev->dino_region->action[irq],
- dino_dev->dino_region->data.irqbase + irq,
- regs);
-
- }
+ __do_IRQ(irq, regs);
+ mask &= ~(1 << local_irq);
+ } while (mask);
/* Support for level triggered IRQ lines.
**
** device drivers may assume lines are level triggered (and not
** edge triggered like EISA/ISA can be).
*/
- mask = gsc_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr;
+ mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr;
if (mask) {
if (--ilr_loop > 0)
goto ilr_again;
- printk(KERN_ERR "Dino %lx: stuck interrupt %d\n", dino_dev->hba.base_addr, mask);
+ printk(KERN_ERR "Dino 0x%p: stuck interrupt %d\n",
+ dino_dev->hba.base_addr, mask);
return IRQ_NONE;
}
return IRQ_HANDLED;
}
-static int dino_choose_irq(struct parisc_device *dev)
+static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp)
{
- int irq = -1;
+ int irq = gsc_assign_irq(&dino_interrupt_type, dino);
+ if (irq == NO_IRQ)
+ return;
+
+ *irqp = irq;
+ dino->global_irq[local_irq] = irq;
+}
+
+static void dino_choose_irq(struct parisc_device *dev, void *ctrl)
+{
+ int irq;
+ struct dino_device *dino = ctrl;
switch (dev->id.sversion) {
case 0x00084: irq = 8; break; /* PS/2 */
case 0x0008c: irq = 10; break; /* RS232 */
case 0x00096: irq = 8; break; /* PS/2 */
+ default: return; /* Unknown */
}
- return irq;
+ dino_assign_irq(dino, irq, &dev->irq);
}
static void __init
*/
#define _8MB 0x00800000UL
static void __init
-dino_card_setup(struct pci_bus *bus, unsigned long base_addr)
+dino_card_setup(struct pci_bus *bus, void __iomem *base_addr)
{
int i;
struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
res = &dino_dev->hba.lmmio_space;
res->flags = IORESOURCE_MEM;
- size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)", bus->bridge->bus_id);
+ size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)",
+ bus->bridge->bus_id);
res->name = kmalloc(size+1, GFP_KERNEL);
if(res->name)
strcpy((char *)res->name, name);
}
DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %lx\n",
i, res->start, base_addr + DINO_IO_ADDR_EN);
- gsc_writel(1 << i, base_addr + DINO_IO_ADDR_EN);
+ __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN);
}
static void __init
** Set Latency Timer to 0xff (not a shared bus)
** Set CACHELINE_SIZE.
*/
- dino_cfg_write(dev->bus, dev->devfn, PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4);
+ dino_cfg_write(dev->bus, dev->devfn,
+ PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4);
/*
** Program INT_LINE for card-mode devices.
struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
int port_base = HBA_PORT_BASE(dino_dev->hba.hba_num);
- DBG(KERN_WARNING "%s(0x%p) bus %d sysdata 0x%p\n",
- __FUNCTION__, bus, bus->secondary, bus->bridge->platform_data);
+ DBG(KERN_WARNING "%s(0x%p) bus %d platform_data 0x%p\n",
+ __FUNCTION__, bus, bus->secondary,
+ bus->bridge->platform_data);
/* Firmware doesn't set up card-mode dino, so we have to */
if (is_card_dino(&dino_dev->hba.dev->id)) {
for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
- if((bus->self->resource[i].flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
+ if((bus->self->resource[i].flags &
+ (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
continue;
if(bus->self->resource[i].flags & IORESOURCE_MEM) {
u32 irq_pin;
- dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin);
- dev->irq = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ;
- dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq);
- dev->irq += dino_dev->dino_region->data.irqbase;
- printk(KERN_WARNING "Device %s has undefined IRQ, setting to %d\n", dev->slot_name, irq_pin);
+ dino_cfg_read(dev->bus, dev->devfn,
+ PCI_INTERRUPT_PIN, 1, &irq_pin);
+ irq_pin = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ;
+ printk(KERN_WARNING "Device %s has undefined IRQ, "
+ "setting to %d\n", dev->slot_name,
+ irq_pin);
+ dino_cfg_write(dev->bus, dev->devfn,
+ PCI_INTERRUPT_LINE, 1, irq_pin);
+ dino_assign_irq(dino_dev, irq_pin, &dev->irq);
#else
dev->irq = 65535;
printk(KERN_WARNING "Device %s has unassigned IRQ\n", dev->slot_name);
} else {
/* Adjust INT_LINE for that busses region */
- dev->irq += dino_dev->dino_region->data.irqbase;
+ dino_assign_irq(dino_dev, dev->irq, &dev->irq);
}
}
}
{
u32 brdg_feat = 0x00784e05;
- gsc_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK);
- gsc_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN);
- gsc_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR);
+ __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK);
+ __raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN);
+ __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR);
#if 1
/* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */
*/
brdg_feat &= ~0x4; /* UXQL */
#endif
- gsc_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT);
+ __raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT);
/*
** Don't enable address decoding until we know which I/O range
** currently is available from the host. Only affects MMIO
** and not I/O port space.
*/
- gsc_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN);
+ __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN);
- gsc_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE);
- gsc_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR);
- gsc_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR);
+ __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE);
+ __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR);
+ __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR);
- gsc_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM);
- gsc_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL);
- gsc_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM);
+ __raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM);
+ __raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL);
+ __raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM);
/* Disable PAMR before writing PAPR */
- gsc_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR);
- gsc_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR);
- gsc_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR);
+ __raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR);
+ __raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR);
+ __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR);
/*
** Dino ERS encourages enabling FBB (0x6f).
** We can't until we know *all* devices below us can support it.
** (Something in device configuration header tells us).
*/
- gsc_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD);
+ __raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD);
/* Somewhere, the PCI spec says give devices 1 second
** to recover from the #RESET being de-asserted.
* since PDC has already initialized this.
*/
- io_addr = gsc_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN);
+ io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN);
if (io_addr == 0) {
printk(KERN_WARNING "%s: No PCI devices enabled.\n", name);
return -ENODEV;
** still only has 11 IRQ input lines - just map some of them
** to a different processor.
*/
- dino_dev->irq = gsc_alloc_irq(&gsc_irq);
+ dev->irq = gsc_alloc_irq(&gsc_irq);
dino_dev->txn_addr = gsc_irq.txn_addr;
dino_dev->txn_data = gsc_irq.txn_data;
eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data;
** Dino needs a PA "IRQ" to get a processor's attention.
** arch/parisc/kernel/irq.c returns an EIRR bit.
*/
- if (dino_dev->irq < 0) {
+ if (dev->irq < 0) {
printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name);
return 1;
}
- status = request_irq(dino_dev->irq, dino_isr, 0, name, dino_dev);
+ status = request_irq(dev->irq, dino_isr, 0, name, dino_dev);
if (status) {
printk(KERN_WARNING "%s: request_irq() failed with %d\n",
name, status);
return 1;
}
- /*
- ** Tell generic interrupt support we have 11 bits which need
- ** be checked in the interrupt handler.
- */
- dino_dev->dino_region = alloc_irq_region(DINO_IRQS, &dino_irq_ops,
- name, dino_dev);
-
- if (NULL == dino_dev->dino_region) {
- printk(KERN_WARNING "%s: alloc_irq_region() failed\n", name);
- return 1;
- }
-
/* Support the serial port which is sometimes attached on built-in
* Dino / Cujo chips.
*/
- fixup_child_irqs(dev, dino_dev->dino_region->data.irqbase,
- dino_choose_irq);
+ gsc_fixup_irqs(dev, dino_dev, dino_choose_irq);
/*
** This enables DINO to generate interrupts when it sees
** any of its inputs *change*. Just asserting an IRQ
** before it's enabled (ie unmasked) isn't good enough.
*/
- gsc_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
+ __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
/*
** Some platforms don't clear Dino's IRR0 register at boot time.
** Reading will clear it now.
*/
- gsc_readl(dino_dev->hba.base_addr+DINO_IRR0);
+ __raw_readl(dino_dev->hba.base_addr+DINO_IRR0);
/* allocate I/O Port resource region */
res = &dino_dev->hba.io_space;
res->end = res->start + (HBA_PORT_SPACE_SIZE - 1);
res->flags = IORESOURCE_IO; /* do not mark it busy ! */
if (request_resource(&ioport_resource, res) < 0) {
- printk(KERN_ERR "%s: request I/O Port region failed 0x%lx/%lx (hpa 0x%lx)\n",
- name, res->start, res->end, dino_dev->hba.base_addr);
+ printk(KERN_ERR "%s: request I/O Port region failed "
+ "0x%lx/%lx (hpa 0x%p)\n",
+ name, res->start, res->end, dino_dev->hba.base_addr);
return 1;
}
{
struct dino_device *dino_dev; // Dino specific control struct
const char *version = "unknown";
- const int name_len = 32;
- char hw_path[64];
char *name;
int is_cujo = 0;
struct pci_bus *bus;
- name = kmalloc(name_len, GFP_KERNEL);
- if(name) {
- print_pa_hwpath(dev, hw_path);
- snprintf(name, name_len, "Dino [%s]", hw_path);
- }
- else
- name = "Dino";
-
+ name = "Dino";
if (is_card_dino(&dev->id)) {
version = "3.x (card mode)";
} else {
#ifdef CONFIG_IOMMU_CCIO
printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n");
if (dev->hpa == (unsigned long)CUJO_RAVEN_ADDR) {
- ccio_cujo20_fixup(dev->parent, CUJO_RAVEN_BADPAGE);
+ ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE);
} else if (dev->hpa == (unsigned long)CUJO_FIREHAWK_ADDR) {
- ccio_cujo20_fixup(dev->parent, CUJO_FIREHAWK_BADPAGE);
+ ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE);
} else {
printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", dev->hpa);
}
memset(dino_dev, 0, sizeof(struct dino_device));
dino_dev->hba.dev = dev;
- dino_dev->hba.base_addr = dev->hpa; /* faster access */
+ dino_dev->hba.base_addr = ioremap(dev->hpa, 4096); /* faster access */
dino_dev->hba.lmmio_space_offset = 0; /* CPU addrs == bus addrs */
- dino_dev->dinosaur_pen = SPIN_LOCK_UNLOCKED;
+ spin_lock_init(&dino_dev->dinosaur_pen);
dino_dev->hba.iommu = ccio_get_iommu(dev);
if (is_card_dino(&dev->id)) {
git://git.onelab.eu / linux-2.6.git / blobdiff