** Don't even think about messing with it unless you have
** plenty of 710's to sacrifice to the computer gods. :^)
*/
-#undef DEBUG_SBA_ASSERT
#undef DEBUG_SBA_INIT
#undef DEBUG_SBA_RUN
#undef DEBUG_SBA_RUN_SG
#define DBG_RES(x...)
#endif
-#ifdef DEBUG_SBA_ASSERT
-#undef ASSERT
-#define ASSERT(expr) \
- if(!(expr)) { \
- printk("\n%s:%d: Assertion " #expr " failed!\n", \
- __FILE__, __LINE__); \
- panic(#expr); \
- }
-#else
-#define ASSERT(expr)
-#endif
-
-
#if defined(__LP64__) && !defined(CONFIG_PDC_NARROW)
/* "low end" PA8800 machines use ZX1 chipset */
#define ZX1_SUPPORT
#define DEFAULT_DMA_HINT_REG 0
#define ASTRO_RUNWAY_PORT 0x582
-#define ASTRO_ROPES_PORT 0x780
-
#define IKE_MERCED_PORT 0x803
-#define IKE_ROPES_PORT 0x781
-
#define REO_MERCED_PORT 0x804
-#define REO_ROPES_PORT 0x782
-
#define REOG_MERCED_PORT 0x805
-#define REOG_ROPES_PORT 0x783
-
#define PLUTO_MCKINLEY_PORT 0x880
-#define PLUTO_ROPES_PORT 0x784
#define SBA_FUNC_ID 0x0000 /* function id */
#define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
-#define IS_ASTRO(id) \
-(((id)->hversion == ASTRO_RUNWAY_PORT) || ((id)->hversion == ASTRO_ROPES_PORT))
-
-#define IS_IKE(id) \
-(((id)->hversion == IKE_MERCED_PORT) || ((id)->hversion == IKE_ROPES_PORT))
-
-#define IS_PLUTO(id) \
-(((id)->hversion == PLUTO_MCKINLEY_PORT) || ((id)->hversion == PLUTO_ROPES_PORT))
+#define IS_ASTRO(id) ((id)->hversion == ASTRO_RUNWAY_PORT)
+#define IS_IKE(id) ((id)->hversion == IKE_MERCED_PORT)
+#define IS_PLUTO(id) ((id)->hversion == PLUTO_MCKINLEY_PORT)
#define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
-#define ASTRO_IOC_OFFSET 0x20000
-/* Ike's IOC's occupy functions 2 and 3 (not 0 and 1) */
-#define IKE_IOC_OFFSET(p) ((p+2)*SBA_FUNC_SIZE)
-
-#define PLUTO_IOC_OFFSET 0x1000
+#define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
+#define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
+/* Ike's IOC's occupy functions 2 and 3 */
+#define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
#define IOC_CTRL 0x8 /* IOC_CTRL offset */
#define IOC_CTRL_TC (1 << 0) /* TOC Enable */
#define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
#define IOC_CTRL_RM (1 << 8) /* Real Mode */
#define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
+#define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
+#define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
#define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
struct ioc {
- unsigned long ioc_hpa; /* I/O MMU base address */
- char *res_map; /* resource map, bit == pdir entry */
- u64 *pdir_base; /* physical base address */
+ void __iomem *ioc_hpa; /* I/O MMU base address */
+ char *res_map; /* resource map, bit == pdir entry */
+ u64 *pdir_base; /* physical base address */
unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
#ifdef ZX1_SUPPORT
struct parisc_device *dev; /* dev found in bus walk */
struct parisc_device_id *iodc; /* data about dev from firmware */
const char *name;
- unsigned long sba_hpa; /* base address */
+ void __iomem *sba_hpa; /* base address */
spinlock_t sba_lock;
unsigned int flags; /* state/functionality enabled */
unsigned int hw_rev; /* HW revision of chip */
static unsigned long ioc_needs_fdc = 0;
-/* Ratio of Host MEM to IOV Space size */
-static unsigned long sba_mem_ratio = 8;
-
/* global count of IOMMUs in the system */
static unsigned int global_ioc_cnt = 0;
* IO Adapter (aka Bus Converter).
*/
static void
-sba_dump_ranges(unsigned long hpa)
+sba_dump_ranges(void __iomem *hpa)
{
- DBG_INIT("SBA at 0x%lx\n", hpa);
+ DBG_INIT("SBA at 0x%p\n", hpa);
DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
*
* Print the size/location of the IO MMU PDIR.
*/
-static void
-sba_dump_tlb(unsigned long hpa)
+static void sba_dump_tlb(void __iomem *hpa)
{
- DBG_INIT("IO TLB at 0x%lx\n", hpa);
+ DBG_INIT("IO TLB at 0x%p\n", hpa);
DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
unsigned long pide = ~0UL;
- ASSERT(((unsigned long) ioc->res_hint & (sizeof(unsigned long) - 1UL)) == 0);
- ASSERT(res_ptr < res_end);
if (bits_wanted > (BITS_PER_LONG/2)) {
/* Search word at a time - no mask needed */
for(; res_ptr < res_end; ++res_ptr) {
while(res_ptr < res_end)
{
DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
- BUG_ON(0 == mask);
- if(0 == ((*res_ptr) & mask)) {
+ WARN_ON(mask == 0);
+ if(((*res_ptr) & mask) == 0) {
*res_ptr |= mask; /* mark resources busy! */
pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
pide <<= 3; /* convert to bit address */
}
mask >>= o;
bitshiftcnt += o;
- if (0 == mask) {
+ if (mask == 0) {
mask = RESMAP_MASK(bits_wanted);
bitshiftcnt=0;
res_ptr++;
#endif
unsigned long pide;
- ASSERT(pages_needed);
- ASSERT((pages_needed * IOVP_SIZE) <= DMA_CHUNK_SIZE);
- ASSERT(pages_needed <= BITS_PER_LONG);
- ASSERT(0 == (size & ~IOVP_MASK));
-
- /*
- ** "seek and ye shall find"...praying never hurts either...
- ** ggg sacrifices another 710 to the computer gods.
- */
-
pide = sba_search_bitmap(ioc, pages_needed);
if (pide >= (ioc->res_size << 3)) {
pide = sba_search_bitmap(ioc, pages_needed);
if (pide >= (ioc->res_size << 3))
- panic("%s: I/O MMU @ %lx is out of mapping resources\n",
+ panic("%s: I/O MMU @ %p is out of mapping resources\n",
__FILE__, ioc->ioc_hpa);
}
ioc->used_pages -= bits_not_wanted;
#endif
- ASSERT(m != 0);
- ASSERT(bits_not_wanted);
- ASSERT((bits_not_wanted * IOVP_SIZE) <= DMA_CHUNK_SIZE);
- ASSERT(bits_not_wanted <= BITS_PER_LONG);
- ASSERT((*res_ptr & m) == m); /* verify same bits are set */
*res_ptr &= ~m;
}
/**
* sba_io_pdir_entry - fill in one IO PDIR entry
* @pdir_ptr: pointer to IO PDIR entry
- * @sid: process Space ID
+ * @sid: process Space ID - currently only support KERNEL_SPACE
* @vba: Virtual CPU address of buffer to map
+ * @hint: DMA hint set to use for this mapping
*
* SBA Mapping Routine
*
* IOMMU uses little endian for the pdir.
*/
-
void SBA_INLINE
sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
unsigned long hint)
u64 pa; /* physical address */
register unsigned ci; /* coherent index */
- /* We currently only support kernel addresses.
- * fdc instr below will need to reload sr1 with KERNEL_SPACE
- * once we try to support direct DMA to user space.
- */
- ASSERT(sid == KERNEL_SPACE);
-
pa = virt_to_phys(vba);
pa &= IOVP_MASK;
*/
int off = PDIR_INDEX(iovp)*sizeof(u64)+7;
- /* Must be non-zero and rounded up */
- ASSERT(byte_cnt > 0);
- ASSERT(0 == (byte_cnt & ~IOVP_MASK));
-
#ifdef ASSERT_PDIR_SANITY
/* Assert first pdir entry is set */
if (0x80 != (((u8 *) ioc->pdir_base)[off])) {
if (byte_cnt <= IOVP_SIZE)
{
- ASSERT( off < ioc->pdir_size);
-
iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
/*
u32 t = get_order(byte_cnt) + PAGE_SHIFT;
iovp |= t;
- ASSERT(t <= 31); /* 2GB! Max value of "size" field */
-
do {
- /* verify this pdir entry is enabled */
- ASSERT(0x80 == (((u8 *) ioc->pdir_base)[off] & 0x80));
/* clear I/O Pdir entry "valid" bit first */
((u8 *)(ioc->pdir_base))[off] = 0;
off += sizeof(u64);
*
* See Documentation/DMA-mapping.txt
*/
-static int
-sba_dma_supported( struct device *dev, u64 mask)
+static int sba_dma_supported( struct device *dev, u64 mask)
{
+ struct ioc *ioc;
if (dev == NULL) {
printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
BUG();
return(0);
}
- /* only support 32-bit PCI devices - no DAC support (yet) */
- return((int) (mask == 0xffffffffUL));
+ ioc = GET_IOC(dev);
+
+ /* check if mask is > than the largest IO Virt Address */
+
+ return((int) (mask >= (ioc->ibase +
+ (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
}
u64 *pdir_start;
int pide;
- ASSERT(size > 0);
- ASSERT(size <= DMA_CHUNK_SIZE);
-
ioc = GET_IOC(dev);
- ASSERT(ioc);
/* save offset bits */
offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
pdir_start = &(ioc->pdir_base[pide]);
while (size > 0) {
- ASSERT(((u8 *)pdir_start)[7] == 0); /* verify availability */
sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
unsigned long flags;
dma_addr_t offset;
- ioc = GET_IOC(dev);
- ASSERT(ioc);
+ DBG_RUN("%s() iovp 0x%lx/%x\n", __FUNCTION__, (long) iova, size);
+ ioc = GET_IOC(dev);
offset = iova & ~IOVP_MASK;
-
- DBG_RUN("%s() iovp 0x%lx/%x\n",
- __FUNCTION__, (long) iova, size);
-
iova ^= offset; /* clear offset bits */
size += offset;
size = ROUNDUP(size, IOVP_SIZE);
DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
ioc = GET_IOC(dev);
- ASSERT(ioc);
/* Fast path single entry scatterlists. */
if (nents == 1) {
spin_unlock_irqrestore(&ioc->res_lock, flags);
- ASSERT(coalesced == filled);
DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
return filled;
__FUNCTION__, nents, sg_virt_addr(sglist), sglist->length);
ioc = GET_IOC(dev);
- ASSERT(ioc);
#ifdef SBA_COLLECT_STATS
ioc->usg_calls++;
return (void *) pdir_base;
}
-static void
-sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
+/* setup Mercury or Elroy IBASE/IMASK registers. */
+static void setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
{
- /* lba_set_iregs() is in arch/parisc/kernel/lba_pci.c */
+ /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
extern void lba_set_iregs(struct parisc_device *, u32, u32);
+ struct device *dev;
+
+ list_for_each_entry(dev, &sba->dev.children, node) {
+ struct parisc_device *lba = to_parisc_device(dev);
+ int rope_num = (lba->hpa >> 13) & 0xf;
+ if (rope_num >> 3 == ioc_num)
+ lba_set_iregs(lba, ioc->ibase, ioc->imask);
+ }
+}
+static void
+sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
+{
u32 iova_space_mask;
u32 iova_space_size;
int iov_order, tcnfg;
- struct parisc_device *lba;
#if SBA_AGP_SUPPORT
int agp_found = 0;
#endif
ioc->hint_shift_pdir, ioc->hint_mask_pdir);
#endif
- ASSERT((((unsigned long) ioc->pdir_base) & PAGE_MASK) == (unsigned long) ioc->pdir_base);
+ WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
/* build IMASK for IOC and Elroy */
#endif
sba_dump_tlb(ioc->ioc_hpa);
- /*
- ** setup Mercury IBASE/IMASK registers as well.
- */
- for (lba = sba->child; lba; lba = lba->sibling) {
- int rope_num = (lba->hpa >> 13) & 0xf;
- if (rope_num >> 3 == ioc_num)
- lba_set_iregs(lba, ioc->ibase, ioc->imask);
- }
+ setup_ibase_imask(sba, ioc, ioc_num);
WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
static void
sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
{
- /* lba_set_iregs() is in arch/parisc/kernel/lba_pci.c */
- extern void lba_set_iregs(struct parisc_device *, u32, u32);
-
u32 iova_space_size, iova_space_mask;
- int pdir_size, iov_order;
- unsigned long physmem;
- struct parisc_device *lba;
+ unsigned int pdir_size, iov_order;
/*
** Determine IOVA Space size from memory size.
** for DMA hints - ergo only 30 bits max.
*/
- physmem = num_physpages << PAGE_SHIFT;
- iova_space_size = (u32) (physmem/(sba_mem_ratio*global_ioc_cnt));
+ iova_space_size = (u32) (num_physpages/global_ioc_cnt);
/* limit IOVA space size to 1MB-1GB */
- if (iova_space_size < 1024*1024) {
- iova_space_size = 1024*1024;
+ if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
+ iova_space_size = 1 << (20 - PAGE_SHIFT);
}
#ifdef __LP64__
- else if (iova_space_size > 512*1024*1024) {
- iova_space_size = 512*1024*1024;
+ else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
+ iova_space_size = 1 << (30 - PAGE_SHIFT);
}
#endif
** thus, pdir/res_map will also be log2().
** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
*/
- iov_order = get_order(iova_space_size >> (IOVP_SHIFT-PAGE_SHIFT));
- ASSERT(iov_order <= (30 - IOVP_SHIFT)); /* iova_space_size <= 1GB */
- ASSERT(iov_order >= (20 - IOVP_SHIFT)); /* iova_space_size >= 1MB */
- iova_space_size = 1 << (iov_order + IOVP_SHIFT);
-
- ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
+ iov_order = get_order(iova_space_size << PAGE_SHIFT);
- ASSERT(pdir_size < 4*1024*1024); /* max pdir size == 2MB */
+ /* iova_space_size is now bytes, not pages */
+ iova_space_size = 1 << (iov_order + PAGE_SHIFT);
- /* Verify it's a power of two */
- ASSERT((1 << get_order(pdir_size)) == (pdir_size >> PAGE_SHIFT));
+ ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
- DBG_INIT("%s() hpa 0x%lx mem %dMB IOV %dMB (%d bits) PDIR size 0x%0x\n",
- __FUNCTION__, ioc->ioc_hpa, (int) (physmem>>20),
- iova_space_size>>20, iov_order + PAGE_SHIFT, pdir_size);
+ DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
+ __FUNCTION__,
+ ioc->ioc_hpa,
+ (unsigned long) num_physpages >> (20 - PAGE_SHIFT),
+ iova_space_size>>20,
+ iov_order + PAGE_SHIFT);
ioc->pdir_base = sba_alloc_pdir(pdir_size);
ioc->hint_shift_pdir, ioc->hint_mask_pdir);
#endif
- ASSERT((((unsigned long) ioc->pdir_base) & PAGE_MASK) == (unsigned long) ioc->pdir_base);
WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
/* build IMASK for IOC and Elroy */
** can't reprogram them the way drivers want.
*/
- /*
- ** setup Elroy IBASE/IMASK registers as well.
- */
- for (lba = sba->child; lba; lba = lba->sibling) {
- int rope_num = (lba->hpa >> 13) & 0xf;
- if (rope_num >> 3 == ioc_num)
- lba_set_iregs(lba, ioc->ibase, ioc->imask);
- }
+ setup_ibase_imask(sba, ioc, ioc_num);
/*
** Program the IOC's ibase and enable IOVA translation
**
**************************************************************************/
-static void
-sba_hw_init(struct sba_device *sba_dev)
+static void __iomem *ioc_remap(struct sba_device *sba_dev, int offset)
+{
+ return ioremap(sba_dev->dev->hpa + offset, SBA_FUNC_SIZE);
+}
+
+static void sba_hw_init(struct sba_device *sba_dev)
{
int i;
int num_ioc;
if (!is_pdc_pat()) {
/* Shutdown the USB controller on Astro-based workstations.
** Once we reprogram the IOMMU, the next DMA performed by
- ** USB will HPMC the box.
+ ** USB will HPMC the box. USB is only enabled if a
+ ** keyboard is present and found.
+ **
+ ** With serial console, j6k v5.0 firmware says:
+ ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
+ **
+ ** FIXME: Using GFX+USB console at power up but direct
+ ** linux to serial console is still broken.
+ ** USB could generate DMA so we must reset USB.
+ ** The proper sequence would be:
+ ** o block console output
+ ** o reset USB device
+ ** o reprogram serial port
+ ** o unblock console output
*/
- pdc_io_reset_devices();
+ if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
+ pdc_io_reset_devices();
+ }
- /*
- ** XXX May need something more sophisticated to deal
- ** with DMA from LAN. Maybe use page zero boot device
- ** as a handle to talk to PDC about which device to
- ** shutdown. This also needs to work for is_pdc_pat().
- */
}
+
+#if 0
+printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
+ PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
+
+ /*
+ ** Need to deal with DMA from LAN.
+ ** Maybe use page zero boot device as a handle to talk
+ ** to PDC about which device to shutdown.
+ **
+ ** Netbooting, j6k v5.0 firmware says:
+ ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
+ ** ARGH! invalid class.
+ */
+ if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
+ && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
+ pdc_io_reset();
+ }
+#endif
+
if (!IS_PLUTO(sba_dev->iodc)) {
ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
__FUNCTION__, sba_dev->sba_hpa, ioc_ctl);
ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
- ioc_ctl |= IOC_CTRL_TC; /* Astro: firmware enables this */
+ ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
+ /* j6700 v1.6 firmware sets 0x294f */
+ /* A500 firmware sets 0x4d */
WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
if (IS_ASTRO(sba_dev->iodc)) {
int err;
/* PAT_PDC (L-class) also reports the same goofy base */
- sba_dev->ioc[0].ioc_hpa = ASTRO_IOC_OFFSET;
+ sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
num_ioc = 1;
sba_dev->chip_resv.name = "Astro Intr Ack";
* corrected when we add it with IKE's IOC offset.
* Doesnt look clean, but fewer code.
*/
- sba_dev->ioc[0].ioc_hpa = -PLUTO_IOC_OFFSET;
+ sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
num_ioc = 1;
sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
- BUG_ON(err < 0);
+ WARN_ON(err < 0);
sba_dev->iommu_resv.name = "IOVA Space";
sba_dev->iommu_resv.start = 0x40000000UL;
sba_dev->iommu_resv.end = 0x50000000UL - 1;
err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
- BUG_ON(err < 0);
+ WARN_ON(err < 0);
} else {
/* IS_IKE (ie N-class, L3000, L1500) */
- sba_dev->ioc[0].ioc_hpa = sba_dev->ioc[1].ioc_hpa = 0;
+ sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
+ sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
num_ioc = 2;
/* TODO - LOOKUP Ike/Stretch chipset mem map */
}
+ /* XXX: What about Reo? */
sba_dev->num_ioc = num_ioc;
for (i = 0; i < num_ioc; i++) {
- sba_dev->ioc[i].ioc_hpa += sba_dev->sba_hpa + IKE_IOC_OFFSET(i);
-
/*
** Make sure the box crashes if we get any errors on a rope.
*/
/* flush out the writes */
READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
+ DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
+ i,
+ READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
+ READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
+ );
+ DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
+ READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
+ READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
+ );
+
if (IS_PLUTO(sba_dev->iodc)) {
sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
} else {
{ HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
{ HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
{ HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
-/* These two entries commented out because we don't find them in a
- * buswalk yet. If/when we do, they would cause us to think we had
- * many more SBAs then we really do.
- * { HPHW_BCPORT, HVERSION_REV_ANY_ID, ASTRO_ROPES_PORT, 0xc },
- * { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_ROPES_PORT, 0xc },
- */
-/* We shall also comment out Pluto Ropes Port since bus walk doesnt
- * report it yet.
- * { HPHW_BCPORT, HVERSION_REV_ANY_ID, PLUTO_ROPES_PORT, 0xc },
- */
{ 0, }
};
u32 func_class;
int i;
char *version;
+ void __iomem *sba_addr = ioremap(dev->hpa, SBA_FUNC_SIZE);
- sba_dump_ranges(dev->hpa);
+ sba_dump_ranges(sba_addr);
/* Read HW Rev First */
- func_class = READ_REG(dev->hpa + SBA_FCLASS);
+ func_class = READ_REG(sba_addr + SBA_FCLASS);
if (IS_ASTRO(&dev->id)) {
unsigned long fclass;
static char astro_rev[]="Astro ?.?";
/* Astro is broken...Read HW Rev First */
- fclass = READ_REG(dev->hpa);
+ fclass = READ_REG(sba_addr);
astro_rev[6] = '1' + (char) (fclass & 0x7);
astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
MODULE_NAME, version, dev->hpa);
sba_dev = kmalloc(sizeof(struct sba_device), GFP_KERNEL);
- if (NULL == sba_dev) {
+ if (!sba_dev) {
printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
- return(1);
+ return -ENOMEM;
}
- dev->sysdata = (void *) sba_dev;
+ parisc_set_drvdata(dev, sba_dev);
memset(sba_dev, 0, sizeof(struct sba_device));
for(i=0; i<MAX_IOC; i++)
sba_dev->hw_rev = func_class;
sba_dev->iodc = &dev->id;
sba_dev->name = dev->name;
- sba_dev->sba_hpa = dev->hpa; /* faster access */
+ sba_dev->sba_hpa = sba_addr;
sba_get_pat_resources(sba_dev);
sba_hw_init(sba_dev);
#endif
parisc_vmerge_boundary = IOVP_SIZE;
parisc_vmerge_max_size = IOVP_SIZE * BITS_PER_LONG;
-
+ parisc_has_iommu();
return 0;
}
char t = sba_dev->id.hw_type;
int iocnum = (pci_hba->hw_path >> 3); /* rope # */
- BUG_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
+ WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
return &(sba->ioc[iocnum]);
}
/* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
for (i=0; i<4; i++) {
int base, size;
- unsigned long reg = sba->sba_hpa + i*0x18;
+ void __iomem *reg = sba->sba_hpa + i*0x18;
base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
if ((base & 1) == 0)
git://git.onelab.eu / linux-2.6.git / blobdiff