#define SLOT_100MHZ_PCIX_533 0x0f000000
#define SLOT_133MHZ_PCIX_533 0xf0000000
+
+/* Secondary Bus Configuration Register */
+/* For PI = 1, Bits 0 to 2 have been encoded as follows to show current bus speed/mode */
+#define PCI_33MHZ 0x0
+#define PCI_66MHZ 0x1
+#define PCIX_66MHZ 0x2
+#define PCIX_100MHZ 0x3
+#define PCIX_133MHZ 0x4
+
+/* For PI = 2, Bits 0 to 3 have been encoded as follows to show current bus speed/mode */
+#define PCI_33MHZ 0x0
+#define PCI_66MHZ 0x1
+#define PCIX_66MHZ 0x2
+#define PCIX_100MHZ 0x3
+#define PCIX_133MHZ 0x4
+#define PCIX_66MHZ_ECC 0x5
+#define PCIX_100MHZ_ECC 0x6
+#define PCIX_133MHZ_ECC 0x7
+#define PCIX_66MHZ_266 0x9
+#define PCIX_100MHZ_266 0xa
+#define PCIX_133MHZ_266 0xb
+#define PCIX_66MHZ_533 0x11
+#define PCIX_100MHZ_533 0x12
+#define PCIX_133MHZ_533 0x13
+
/* Slot Configuration */
#define SLOT_NUM 0x0000001F
#define FIRST_DEV_NUM 0x00001F00
#define MRLSENSOR 0x40000000
#define ATTN_BUTTON 0x80000000
-/*
- * Interrupt Locator Register definitions
- */
-#define CMD_INTR_PENDING (1 << 0)
-#define SLOT_INTR_PENDING(i) (1 << (i + 1))
+/* Slot Status Field Definitions */
+/* Slot State */
+#define PWR_ONLY 0x0001
+#define ENABLED 0x0002
+#define DISABLED 0x0003
-/*
- * Controller SERR-INT Register
- */
-#define GLOBAL_INTR_MASK (1 << 0)
-#define GLOBAL_SERR_MASK (1 << 1)
-#define COMMAND_INTR_MASK (1 << 2)
-#define ARBITER_SERR_MASK (1 << 3)
-#define COMMAND_DETECTED (1 << 16)
-#define ARBITER_DETECTED (1 << 17)
-#define SERR_INTR_RSVDZ_MASK 0xfffc0000
+/* Power Indicator State */
+#define PWR_LED_ON 0x0004
+#define PWR_LED_BLINK 0x0008
+#define PWR_LED_OFF 0x000c
-/*
- * Logical Slot Register definitions
- */
-#define SLOT_REG(i) (SLOT1 + (4 * i))
-
-#define SLOT_STATE_SHIFT (0)
-#define SLOT_STATE_MASK (3 << 0)
-#define SLOT_STATE_PWRONLY (1)
-#define SLOT_STATE_ENABLED (2)
-#define SLOT_STATE_DISABLED (3)
-#define PWR_LED_STATE_SHIFT (2)
-#define PWR_LED_STATE_MASK (3 << 2)
-#define ATN_LED_STATE_SHIFT (4)
-#define ATN_LED_STATE_MASK (3 << 4)
-#define ATN_LED_STATE_ON (1)
-#define ATN_LED_STATE_BLINK (2)
-#define ATN_LED_STATE_OFF (3)
-#define POWER_FAULT (1 << 6)
-#define ATN_BUTTON (1 << 7)
-#define MRL_SENSOR (1 << 8)
-#define MHZ66_CAP (1 << 9)
-#define PRSNT_SHIFT (10)
-#define PRSNT_MASK (3 << 10)
-#define PCIX_CAP_SHIFT (12)
-#define PCIX_CAP_MASK_PI1 (3 << 12)
-#define PCIX_CAP_MASK_PI2 (7 << 12)
-#define PRSNT_CHANGE_DETECTED (1 << 16)
-#define ISO_PFAULT_DETECTED (1 << 17)
-#define BUTTON_PRESS_DETECTED (1 << 18)
-#define MRL_CHANGE_DETECTED (1 << 19)
-#define CON_PFAULT_DETECTED (1 << 20)
-#define PRSNT_CHANGE_INTR_MASK (1 << 24)
-#define ISO_PFAULT_INTR_MASK (1 << 25)
-#define BUTTON_PRESS_INTR_MASK (1 << 26)
-#define MRL_CHANGE_INTR_MASK (1 << 27)
-#define CON_PFAULT_INTR_MASK (1 << 28)
-#define MRL_CHANGE_SERR_MASK (1 << 29)
-#define CON_PFAULT_SERR_MASK (1 << 30)
-#define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21)
+/* Attention Indicator State */
+#define ATTEN_LED_ON 0x0010
+#define ATTEN_LED_BLINK 0x0020
+#define ATTEN_LED_OFF 0x0030
-/*
- * SHPC Command Code definitnions
- *
- * Slot Operation 00h - 3Fh
- * Set Bus Segment Speed/Mode A 40h - 47h
- * Power-Only All Slots 48h
- * Enable All Slots 49h
- * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh
- * Reserved Command Codes 60h - BFh
- * Vendor Specific Commands C0h - FFh
- */
-#define SET_SLOT_PWR 0x01 /* Slot Operation */
-#define SET_SLOT_ENABLE 0x02
-#define SET_SLOT_DISABLE 0x03
-#define SET_PWR_ON 0x04
-#define SET_PWR_BLINK 0x08
-#define SET_PWR_OFF 0x0c
-#define SET_ATTN_ON 0x10
-#define SET_ATTN_BLINK 0x20
-#define SET_ATTN_OFF 0x30
-#define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */
+/* Power Fault */
+#define pwr_fault 0x0040
+
+/* Attention Button */
+#define ATTEN_BUTTON 0x0080
+
+/* MRL Sensor */
+#define MRL_SENSOR 0x0100
+
+/* 66 MHz Capable */
+#define IS_66MHZ_CAP 0x0200
+
+/* PRSNT1#/PRSNT2# */
+#define SLOT_EMP 0x0c00
+
+/* PCI-X Capability */
+#define NON_PCIX 0x0000
+#define PCIX_66 0x1000
+#define PCIX_133 0x3000
+#define PCIX_266 0x4000 /* For PI = 2 only */
+#define PCIX_533 0x5000 /* For PI = 2 only */
+
+/* SHPC 'write' operations/commands */
+
+/* Slot operation - 0x00h to 0x3Fh */
+
+#define NO_CHANGE 0x00
+
+/* Slot state - Bits 0 & 1 of controller command register */
+#define SET_SLOT_PWR 0x01
+#define SET_SLOT_ENABLE 0x02
+#define SET_SLOT_DISABLE 0x03
+
+/* Power indicator state - Bits 2 & 3 of controller command register*/
+#define SET_PWR_ON 0x04
+#define SET_PWR_BLINK 0x08
+#define SET_PWR_OFF 0x0C
+
+/* Attention indicator state - Bits 4 & 5 of controller command register*/
+#define SET_ATTN_ON 0x010
+#define SET_ATTN_BLINK 0x020
+#define SET_ATTN_OFF 0x030
+
+/* Set bus speed/mode A - 0x40h to 0x47h */
+#define SETA_PCI_33MHZ 0x40
#define SETA_PCI_66MHZ 0x41
#define SETA_PCIX_66MHZ 0x42
#define SETA_PCIX_100MHZ 0x43
#define SETA_PCIX_133MHZ 0x44
-#define SETA_RESERVED1 0x45
-#define SETA_RESERVED2 0x46
-#define SETA_RESERVED3 0x47
-#define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */
-#define SET_ENABLE_ALL 0x49 /* Enable All Slots */
-#define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */
+#define RESERV_1 0x45
+#define RESERV_2 0x46
+#define RESERV_3 0x47
+
+/* Set bus speed/mode B - 0x50h to 0x5fh */
+#define SETB_PCI_33MHZ 0x50
#define SETB_PCI_66MHZ 0x51
#define SETB_PCIX_66MHZ_PM 0x52
#define SETB_PCIX_100MHZ_PM 0x53
#define SETB_PCIX_66MHZ_533 0x5b
#define SETB_PCIX_100MHZ_533 0x5c
#define SETB_PCIX_133MHZ_533 0x5d
-#define SETB_RESERVED1 0x5e
-#define SETB_RESERVED2 0x5f
-/*
- * SHPC controller command error code
- */
+
+/* Power-on all slots - 0x48h */
+#define SET_PWR_ON_ALL 0x48
+
+/* Enable all slots - 0x49h */
+#define SET_ENABLE_ALL 0x49
+
+/* SHPC controller command error code */
#define SWITCH_OPEN 0x1
#define INVALID_CMD 0x2
#define INVALID_SPEED_MODE 0x4
-/*
- * For accessing SHPC Working Register Set via PCI Configuration Space
- */
+/* For accessing SHPC Working Register Set */
#define DWORD_SELECT 0x2
#define DWORD_DATA 0x4
+#define BASE_OFFSET 0x0
/* Field Offset in Logical Slot Register - byte boundary */
#define SLOT_EVENT_LATCH 0x2
#define SLOT_SERR_INT_MASK 0x3
+static spinlock_t hpc_event_lock;
+
DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
static int ctlr_seq_num = 0; /* Controller sequenc # */
static spinlock_t list_lock;
-static atomic_t shpchp_num_controllers = ATOMIC_INIT(0);
+static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs);
-static irqreturn_t shpc_isr(int irq, void *dev_id, struct pt_regs *regs);
-static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec);
-static int hpc_check_cmd_status(struct controller *ctrl);
-
-static inline u8 shpc_readb(struct controller *ctrl, int reg)
-{
- return readb(ctrl->hpc_ctlr_handle->creg + reg);
-}
-
-static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
-{
- writeb(val, ctrl->hpc_ctlr_handle->creg + reg);
-}
+static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
-static inline u16 shpc_readw(struct controller *ctrl, int reg)
+/* This is the interrupt polling timeout function. */
+static void int_poll_timeout(unsigned long lphp_ctlr)
{
- return readw(ctrl->hpc_ctlr_handle->creg + reg);
-}
+ struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
-static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
-{
- writew(val, ctrl->hpc_ctlr_handle->creg + reg);
-}
+ DBG_ENTER_ROUTINE
-static inline u32 shpc_readl(struct controller *ctrl, int reg)
-{
- return readl(ctrl->hpc_ctlr_handle->creg + reg);
-}
+ if ( !php_ctlr ) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return;
+ }
-static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
-{
- writel(val, ctrl->hpc_ctlr_handle->creg + reg);
-}
+ /* Poll for interrupt events. regs == NULL => polling */
+ shpc_isr( 0, (void *)php_ctlr, NULL );
-static inline int shpc_indirect_read(struct controller *ctrl, int index,
- u32 *value)
-{
- int rc;
- u32 cap_offset = ctrl->cap_offset;
- struct pci_dev *pdev = ctrl->pci_dev;
+ init_timer(&php_ctlr->int_poll_timer);
+ if (!shpchp_poll_time)
+ shpchp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
- rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
- if (rc)
- return rc;
- return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
+ start_int_poll_timer(php_ctlr, shpchp_poll_time);
+
+ return;
}
-/*
- * This is the interrupt polling timeout function.
- */
-static void int_poll_timeout(unsigned long lphp_ctlr)
+/* This function starts the interrupt polling timer. */
+static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
{
- struct php_ctlr_state_s *php_ctlr =
- (struct php_ctlr_state_s *)lphp_ctlr;
-
- DBG_ENTER_ROUTINE
-
- /* Poll for interrupt events. regs == NULL => polling */
- shpc_isr(0, php_ctlr->callback_instance_id, NULL);
-
- init_timer(&php_ctlr->int_poll_timer);
- if (!shpchp_poll_time)
- shpchp_poll_time = 2; /* default polling interval is 2 sec */
+ if (!php_ctlr) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return;
+ }
- start_int_poll_timer(php_ctlr, shpchp_poll_time);
+ if ( ( seconds <= 0 ) || ( seconds > 60 ) )
+ seconds = 2; /* Clamp to sane value */
- DBG_LEAVE_ROUTINE
-}
+ php_ctlr->int_poll_timer.function = &int_poll_timeout;
+ php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
+ php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
+ add_timer(&php_ctlr->int_poll_timer);
-/*
- * This function starts the interrupt polling timer.
- */
-static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec)
-{
- /* Clamp to sane value */
- if ((sec <= 0) || (sec > 60))
- sec = 2;
-
- php_ctlr->int_poll_timer.function = &int_poll_timeout;
- php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr;
- php_ctlr->int_poll_timer.expires = jiffies + sec * HZ;
- add_timer(&php_ctlr->int_poll_timer);
+ return;
}
static inline int shpc_wait_cmd(struct controller *ctrl)
static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
{
- struct controller *ctrl = slot->ctrl;
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
u16 cmd_status;
int retval = 0;
u16 temp_word;
int i;
DBG_ENTER_ROUTINE
-
- mutex_lock(&slot->ctrl->cmd_lock);
+
+ if (!php_ctlr) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
for (i = 0; i < 10; i++) {
- cmd_status = shpc_readw(ctrl, CMD_STATUS);
+ cmd_status = readw(php_ctlr->creg + CMD_STATUS);
if (!(cmd_status & 0x1))
break;
msleep(100);
}
- cmd_status = shpc_readw(ctrl, CMD_STATUS);
+ cmd_status = readw(php_ctlr->creg + CMD_STATUS);
if (cmd_status & 0x1) {
/* After 1 sec and and the controller is still busy */
err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__);
- retval = -EBUSY;
- goto out;
+ return -1;
}
++t_slot;
* command.
*/
slot->ctrl->cmd_busy = 1;
- shpc_writew(ctrl, CMD, temp_word);
+ writew(temp_word, php_ctlr->creg + CMD);
/*
* Wait for command completion.
*/
retval = shpc_wait_cmd(slot->ctrl);
- if (retval)
- goto out;
-
- cmd_status = hpc_check_cmd_status(slot->ctrl);
- if (cmd_status) {
- err("%s: Failed to issued command 0x%x (error code = %d)\n",
- __FUNCTION__, cmd, cmd_status);
- retval = -EIO;
- }
- out:
- mutex_unlock(&slot->ctrl->cmd_lock);
DBG_LEAVE_ROUTINE
return retval;
static int hpc_check_cmd_status(struct controller *ctrl)
{
+ struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
u16 cmd_status;
int retval = 0;
DBG_ENTER_ROUTINE
+
+ if (!ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
- cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
+ cmd_status = readw(php_ctlr->creg + CMD_STATUS) & 0x000F;
switch (cmd_status >> 1) {
case 0:
static int hpc_get_attention_status(struct slot *slot, u8 *status)
{
- struct controller *ctrl = slot->ctrl;
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
u32 slot_reg;
- u8 state;
+ u16 slot_status;
+ u8 atten_led_state;
DBG_ENTER_ROUTINE
- slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
- state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
+
+ slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
+ slot_status = (u16) slot_reg;
+ atten_led_state = (slot_status & 0x0030) >> 4;
- switch (state) {
- case ATN_LED_STATE_ON:
+ switch (atten_led_state) {
+ case 0:
+ *status = 0xFF; /* Reserved */
+ break;
+ case 1:
*status = 1; /* On */
break;
- case ATN_LED_STATE_BLINK:
+ case 2:
*status = 2; /* Blink */
break;
- case ATN_LED_STATE_OFF:
+ case 3:
*status = 0; /* Off */
break;
default:
- *status = 0xFF; /* Reserved */
+ *status = 0xFF;
break;
}
static int hpc_get_power_status(struct slot * slot, u8 *status)
{
- struct controller *ctrl = slot->ctrl;
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
u32 slot_reg;
- u8 state;
+ u16 slot_status;
+ u8 slot_state;
+ int retval = 0;
DBG_ENTER_ROUTINE
- slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
- state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
- switch (state) {
- case SLOT_STATE_PWRONLY:
+ slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
+ slot_status = (u16) slot_reg;
+ slot_state = (slot_status & 0x0003);
+
+ switch (slot_state) {
+ case 0:
+ *status = 0xFF;
+ break;
+ case 1:
*status = 2; /* Powered only */
break;
- case SLOT_STATE_ENABLED:
+ case 2:
*status = 1; /* Enabled */
break;
- case SLOT_STATE_DISABLED:
+ case 3:
*status = 0; /* Disabled */
break;
default:
- *status = 0xFF; /* Reserved */
+ *status = 0xFF;
break;
}
DBG_LEAVE_ROUTINE
- return 0;
+ return retval;
}
static int hpc_get_latch_status(struct slot *slot, u8 *status)
{
- struct controller *ctrl = slot->ctrl;
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
u32 slot_reg;
+ u16 slot_status;
DBG_ENTER_ROUTINE
- slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
- *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
+
+ slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
+ slot_status = (u16)slot_reg;
+
+ *status = ((slot_status & 0x0100) == 0) ? 0 : 1; /* 0 -> close; 1 -> open */
+
DBG_LEAVE_ROUTINE
return 0;
static int hpc_get_adapter_status(struct slot *slot, u8 *status)
{
- struct controller *ctrl = slot->ctrl;
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
u32 slot_reg;
- u8 state;
+ u16 slot_status;
+ u8 card_state;
DBG_ENTER_ROUTINE
- slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
- state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
- *status = (state != 0x3) ? 1 : 0;
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
+
+ slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
+ slot_status = (u16)slot_reg;
+ card_state = (u8)((slot_status & 0x0C00) >> 10);
+ *status = (card_state != 0x3) ? 1 : 0;
DBG_LEAVE_ROUTINE
return 0;
static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
{
- struct controller *ctrl = slot->ctrl;
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
DBG_ENTER_ROUTINE
+
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
- *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
+ *prog_int = readb(php_ctlr->creg + PROG_INTERFACE);
DBG_LEAVE_ROUTINE
return 0;
static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
{
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
+ u32 slot_reg;
+ u16 slot_status, sec_bus_status;
+ u8 m66_cap, pcix_cap, pi;
int retval = 0;
- struct controller *ctrl = slot->ctrl;
- u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
- u8 m66_cap = !!(slot_reg & MHZ66_CAP);
- u8 pi, pcix_cap;
DBG_ENTER_ROUTINE
- if ((retval = hpc_get_prog_int(slot, &pi)))
- return retval;
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
- switch (pi) {
- case 1:
- pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
- break;
- case 2:
- pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
- break;
- default:
- return -ENODEV;
+ if (slot->hp_slot >= php_ctlr->num_slots) {
+ err("%s: Invalid HPC slot number!\n", __FUNCTION__);
+ return -1;
}
+
+ pi = readb(php_ctlr->creg + PROG_INTERFACE);
+ slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
+ dbg("%s: pi = %d, slot_reg = %x\n", __FUNCTION__, pi, slot_reg);
+ slot_status = (u16) slot_reg;
+ dbg("%s: slot_status = %x\n", __FUNCTION__, slot_status);
+ sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
- dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
- __FUNCTION__, slot_reg, pcix_cap, m66_cap);
+ pcix_cap = (u8) ((slot_status & 0x3000) >> 12);
+ dbg("%s: pcix_cap = %x\n", __FUNCTION__, pcix_cap);
+ m66_cap = (u8) ((slot_status & 0x0200) >> 9);
+ dbg("%s: m66_cap = %x\n", __FUNCTION__, m66_cap);
- switch (pcix_cap) {
- case 0x0:
- *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
- break;
- case 0x1:
- *value = PCI_SPEED_66MHz_PCIX;
- break;
- case 0x3:
- *value = PCI_SPEED_133MHz_PCIX;
- break;
- case 0x4:
- *value = PCI_SPEED_133MHz_PCIX_266;
- break;
- case 0x5:
- *value = PCI_SPEED_133MHz_PCIX_533;
- break;
- case 0x2:
- default:
- *value = PCI_SPEED_UNKNOWN;
- retval = -ENODEV;
- break;
+
+ if (pi == 2) {
+ switch (pcix_cap) {
+ case 0:
+ *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
+ break;
+ case 1:
+ *value = PCI_SPEED_66MHz_PCIX;
+ break;
+ case 3:
+ *value = PCI_SPEED_133MHz_PCIX;
+ break;
+ case 4:
+ *value = PCI_SPEED_133MHz_PCIX_266;
+ break;
+ case 5:
+ *value = PCI_SPEED_133MHz_PCIX_533;
+ break;
+ case 2: /* Reserved */
+ default:
+ *value = PCI_SPEED_UNKNOWN;
+ retval = -ENODEV;
+ break;
+ }
+ } else {
+ switch (pcix_cap) {
+ case 0:
+ *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
+ break;
+ case 1:
+ *value = PCI_SPEED_66MHz_PCIX;
+ break;
+ case 3:
+ *value = PCI_SPEED_133MHz_PCIX;
+ break;
+ case 2: /* Reserved */
+ default:
+ *value = PCI_SPEED_UNKNOWN;
+ retval = -ENODEV;
+ break;
+ }
}
dbg("Adapter speed = %d\n", *value);
+
DBG_LEAVE_ROUTINE
return retval;
}
static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
{
- struct controller *ctrl = slot->ctrl;
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
u16 sec_bus_status;
u8 pi;
int retval = 0;
DBG_ENTER_ROUTINE
- pi = shpc_readb(ctrl, PROG_INTERFACE);
- sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
+
+ pi = readb(php_ctlr->creg + PROG_INTERFACE);
+ sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
if (pi == 2) {
*mode = (sec_bus_status & 0x0100) >> 8;
static int hpc_query_power_fault(struct slot * slot)
{
- struct controller *ctrl = slot->ctrl;
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
u32 slot_reg;
+ u16 slot_status;
+ u8 pwr_fault_state, status;
DBG_ENTER_ROUTINE
- slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
+
+ slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
+ slot_status = (u16) slot_reg;
+ pwr_fault_state = (slot_status & 0x0040) >> 7;
+ status = (pwr_fault_state == 1) ? 0 : 1;
DBG_LEAVE_ROUTINE
/* Note: Logic 0 => fault */
- return !(slot_reg & POWER_FAULT);
+ return status;
}
static int hpc_set_attention_status(struct slot *slot, u8 value)
{
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
u8 slot_cmd = 0;
+ int rc = 0;
+
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
+
+ if (slot->hp_slot >= php_ctlr->num_slots) {
+ err("%s: Invalid HPC slot number!\n", __FUNCTION__);
+ return -1;
+ }
switch (value) {
case 0 :
- slot_cmd = SET_ATTN_OFF; /* OFF */
+ slot_cmd = 0x30; /* OFF */
break;
case 1:
- slot_cmd = SET_ATTN_ON; /* ON */
+ slot_cmd = 0x10; /* ON */
break;
case 2:
- slot_cmd = SET_ATTN_BLINK; /* BLINK */
+ slot_cmd = 0x20; /* BLINK */
break;
default:
return -1;
}
- return shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
+ shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
+
+ return rc;
}
static void hpc_set_green_led_on(struct slot *slot)
{
- shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
+ u8 slot_cmd;
+
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return ;
+ }
+
+ if (slot->hp_slot >= php_ctlr->num_slots) {
+ err("%s: Invalid HPC slot number!\n", __FUNCTION__);
+ return ;
+ }
+
+ slot_cmd = 0x04;
+
+ shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
+
+ return;
}
static void hpc_set_green_led_off(struct slot *slot)
{
- shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
+ u8 slot_cmd;
+
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return ;
+ }
+
+ if (slot->hp_slot >= php_ctlr->num_slots) {
+ err("%s: Invalid HPC slot number!\n", __FUNCTION__);
+ return ;
+ }
+
+ slot_cmd = 0x0C;
+
+ shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
+
+ return;
}
static void hpc_set_green_led_blink(struct slot *slot)
{
- shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
+ u8 slot_cmd;
+
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return ;
+ }
+
+ if (slot->hp_slot >= php_ctlr->num_slots) {
+ err("%s: Invalid HPC slot number!\n", __FUNCTION__);
+ return ;
+ }
+
+ slot_cmd = 0x08;
+
+ shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
+
+ return;
}
int shpc_get_ctlr_slot_config(struct controller *ctrl,
int *updown, /* physical_slot_num increament: 1 or -1 */
int *flags)
{
- u32 slot_config;
+ struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
DBG_ENTER_ROUTINE
- slot_config = shpc_readl(ctrl, SLOT_CONFIG);
- *first_device_num = (slot_config & FIRST_DEV_NUM) >> 8;
- *num_ctlr_slots = slot_config & SLOT_NUM;
- *physical_slot_num = (slot_config & PSN) >> 16;
- *updown = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
+ if (!ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
+
+ *first_device_num = php_ctlr->slot_device_offset; /* Obtained in shpc_init() */
+ *num_ctlr_slots = php_ctlr->num_slots; /* Obtained in shpc_init() */
+ *physical_slot_num = (readl(php_ctlr->creg + SLOT_CONFIG) & PSN) >> 16;
dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num);
+ *updown = ((readl(php_ctlr->creg + SLOT_CONFIG) & UPDOWN ) >> 29) ? 1 : -1;
DBG_LEAVE_ROUTINE
return 0;
{
struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
struct php_ctlr_state_s *p, *p_prev;
- int i;
- u32 slot_reg, serr_int;
DBG_ENTER_ROUTINE
- /*
- * Mask event interrupts and SERRs of all slots
- */
- for (i = 0; i < ctrl->num_slots; i++) {
- slot_reg = shpc_readl(ctrl, SLOT_REG(i));
- slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
- BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
- CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
- CON_PFAULT_SERR_MASK);
- slot_reg &= ~SLOT_REG_RSVDZ_MASK;
- shpc_writel(ctrl, SLOT_REG(i), slot_reg);
+ if (!ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return ;
}
- cleanup_slots(ctrl);
-
- /*
- * Mask SERR and System Interrut generation
- */
- serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
- serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
- COMMAND_INTR_MASK | ARBITER_SERR_MASK);
- serr_int &= ~SERR_INTR_RSVDZ_MASK;
- shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
-
if (shpchp_poll_mode) {
del_timer(&php_ctlr->int_poll_timer);
} else {
pci_disable_msi(php_ctlr->pci_dev);
}
}
-
if (php_ctlr->pci_dev) {
iounmap(php_ctlr->creg);
release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
kfree(php_ctlr);
- /*
- * If this is the last controller to be released, destroy the
- * shpchpd work queue
- */
- if (atomic_dec_and_test(&shpchp_num_controllers))
- destroy_workqueue(shpchp_wq);
-
DBG_LEAVE_ROUTINE
}
static int hpc_power_on_slot(struct slot * slot)
{
- int retval;
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
+ u8 slot_cmd;
+ int retval = 0;
DBG_ENTER_ROUTINE
- retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
+
+ if (slot->hp_slot >= php_ctlr->num_slots) {
+ err("%s: Invalid HPC slot number!\n", __FUNCTION__);
+ return -1;
+ }
+ slot_cmd = 0x01;
+
+ retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
+
if (retval) {
err("%s: Write command failed!\n", __FUNCTION__);
- return retval;
+ return -1;
}
DBG_LEAVE_ROUTINE
- return 0;
+ return retval;
}
static int hpc_slot_enable(struct slot * slot)
{
- int retval;
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
+ u8 slot_cmd;
+ int retval = 0;
DBG_ENTER_ROUTINE
- /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
- retval = shpc_write_cmd(slot, slot->hp_slot,
- SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
+
+ if (slot->hp_slot >= php_ctlr->num_slots) {
+ err("%s: Invalid HPC slot number!\n", __FUNCTION__);
+ return -1;
+ }
+ /* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
+ slot_cmd = 0x3A;
+
+ retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
+
if (retval) {
err("%s: Write command failed!\n", __FUNCTION__);
- return retval;
+ return -1;
}
DBG_LEAVE_ROUTINE
- return 0;
+ return retval;
}
static int hpc_slot_disable(struct slot * slot)
{
- int retval;
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
+ u8 slot_cmd;
+ int retval = 0;
DBG_ENTER_ROUTINE
- /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
- retval = shpc_write_cmd(slot, slot->hp_slot,
- SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
+
+ if (slot->hp_slot >= php_ctlr->num_slots) {
+ err("%s: Invalid HPC slot number!\n", __FUNCTION__);
+ return -1;
+ }
+
+ /* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */
+ slot_cmd = 0x1F;
+
+ retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
+
if (retval) {
err("%s: Write command failed!\n", __FUNCTION__);
- return retval;
+ return -1;
}
DBG_LEAVE_ROUTINE
- return 0;
+ return retval;
}
static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
{
- int retval;
- struct controller *ctrl = slot->ctrl;
- u8 pi, cmd;
+ u8 slot_cmd;
+ u8 pi;
+ int retval = 0;
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
DBG_ENTER_ROUTINE
+
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
- pi = shpc_readb(ctrl, PROG_INTERFACE);
- if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
- return -EINVAL;
+ pi = readb(php_ctlr->creg + PROG_INTERFACE);
+
+ if (pi == 1) {
+ switch (value) {
+ case 0:
+ slot_cmd = SETA_PCI_33MHZ;
+ break;
+ case 1:
+ slot_cmd = SETA_PCI_66MHZ;
+ break;
+ case 2:
+ slot_cmd = SETA_PCIX_66MHZ;
+ break;
+ case 3:
+ slot_cmd = SETA_PCIX_100MHZ;
+ break;
+ case 4:
+ slot_cmd = SETA_PCIX_133MHZ;
+ break;
+ default:
+ slot_cmd = PCI_SPEED_UNKNOWN;
+ retval = -ENODEV;
+ return retval;
+ }
+ } else {
+ switch (value) {
+ case 0:
+ slot_cmd = SETB_PCI_33MHZ;
+ break;
+ case 1:
+ slot_cmd = SETB_PCI_66MHZ;
+ break;
+ case 2:
+ slot_cmd = SETB_PCIX_66MHZ_PM;
+ break;
+ case 3:
+ slot_cmd = SETB_PCIX_100MHZ_PM;
+ break;
+ case 4:
+ slot_cmd = SETB_PCIX_133MHZ_PM;
+ break;
+ case 5:
+ slot_cmd = SETB_PCIX_66MHZ_EM;
+ break;
+ case 6:
+ slot_cmd = SETB_PCIX_100MHZ_EM;
+ break;
+ case 7:
+ slot_cmd = SETB_PCIX_133MHZ_EM;
+ break;
+ case 8:
+ slot_cmd = SETB_PCIX_66MHZ_266;
+ break;
+ case 0x9:
+ slot_cmd = SETB_PCIX_100MHZ_266;
+ break;
+ case 0xa:
+ slot_cmd = SETB_PCIX_133MHZ_266;
+ break;
+ case 0xb:
+ slot_cmd = SETB_PCIX_66MHZ_533;
+ break;
+ case 0xc:
+ slot_cmd = SETB_PCIX_100MHZ_533;
+ break;
+ case 0xd:
+ slot_cmd = SETB_PCIX_133MHZ_533;
+ break;
+ default:
+ slot_cmd = PCI_SPEED_UNKNOWN;
+ retval = -ENODEV;
+ return retval;
+ }
- switch (value) {
- case PCI_SPEED_33MHz:
- cmd = SETA_PCI_33MHZ;
- break;
- case PCI_SPEED_66MHz:
- cmd = SETA_PCI_66MHZ;
- break;
- case PCI_SPEED_66MHz_PCIX:
- cmd = SETA_PCIX_66MHZ;
- break;
- case PCI_SPEED_100MHz_PCIX:
- cmd = SETA_PCIX_100MHZ;
- break;
- case PCI_SPEED_133MHz_PCIX:
- cmd = SETA_PCIX_133MHZ;
- break;
- case PCI_SPEED_66MHz_PCIX_ECC:
- cmd = SETB_PCIX_66MHZ_EM;
- break;
- case PCI_SPEED_100MHz_PCIX_ECC:
- cmd = SETB_PCIX_100MHZ_EM;
- break;
- case PCI_SPEED_133MHz_PCIX_ECC:
- cmd = SETB_PCIX_133MHZ_EM;
- break;
- case PCI_SPEED_66MHz_PCIX_266:
- cmd = SETB_PCIX_66MHZ_266;
- break;
- case PCI_SPEED_100MHz_PCIX_266:
- cmd = SETB_PCIX_100MHZ_266;
- break;
- case PCI_SPEED_133MHz_PCIX_266:
- cmd = SETB_PCIX_133MHZ_266;
- break;
- case PCI_SPEED_66MHz_PCIX_533:
- cmd = SETB_PCIX_66MHZ_533;
- break;
- case PCI_SPEED_100MHz_PCIX_533:
- cmd = SETB_PCIX_100MHZ_533;
- break;
- case PCI_SPEED_133MHz_PCIX_533:
- cmd = SETB_PCIX_133MHZ_533;
- break;
- default:
- return -EINVAL;
}
-
- retval = shpc_write_cmd(slot, 0, cmd);
- if (retval)
+ retval = shpc_write_cmd(slot, 0, slot_cmd);
+ if (retval) {
err("%s: Write command failed!\n", __FUNCTION__);
+ return -1;
+ }
DBG_LEAVE_ROUTINE
return retval;
}
-static irqreturn_t shpc_isr(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
{
- struct controller *ctrl = (struct controller *)dev_id;
- struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
- u32 serr_int, slot_reg, intr_loc, intr_loc2;
+ struct controller *ctrl = NULL;
+ struct php_ctlr_state_s *php_ctlr;
+ u8 schedule_flag = 0;
+ u8 temp_byte;
+ u32 temp_dword, intr_loc, intr_loc2;
int hp_slot;
+ if (!dev_id)
+ return IRQ_NONE;
+
+ if (!shpchp_poll_mode) {
+ ctrl = (struct controller *)dev_id;
+ php_ctlr = ctrl->hpc_ctlr_handle;
+ } else {
+ php_ctlr = (struct php_ctlr_state_s *) dev_id;
+ ctrl = (struct controller *)php_ctlr->callback_instance_id;
+ }
+
+ if (!ctrl)
+ return IRQ_NONE;
+
+ if (!php_ctlr || !php_ctlr->creg)
+ return IRQ_NONE;
+
/* Check to see if it was our interrupt */
- intr_loc = shpc_readl(ctrl, INTR_LOC);
+ intr_loc = readl(php_ctlr->creg + INTR_LOC);
+
if (!intr_loc)
return IRQ_NONE;
-
dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
if(!shpchp_poll_mode) {
- /*
- * Mask Global Interrupt Mask - see implementation
- * note on p. 139 of SHPC spec rev 1.0
- */
- serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
- serr_int |= GLOBAL_INTR_MASK;
- serr_int &= ~SERR_INTR_RSVDZ_MASK;
- shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
+ /* Mask Global Interrupt Mask - see implementation note on p. 139 */
+ /* of SHPC spec rev 1.0*/
+ temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
+ temp_dword |= 0x00000001;
+ writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
- intr_loc2 = shpc_readl(ctrl, INTR_LOC);
+ intr_loc2 = readl(php_ctlr->creg + INTR_LOC);
dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
}
- if (intr_loc & CMD_INTR_PENDING) {
+ if (intr_loc & 0x0001) {
/*
* Command Complete Interrupt Pending
* RO only - clear by writing 1 to the Command Completion
* Detect bit in Controller SERR-INT register
*/
- serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
- serr_int &= ~SERR_INTR_RSVDZ_MASK;
- shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
-
+ temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
+ temp_dword &= 0xfffdffff;
+ writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
ctrl->cmd_busy = 0;
wake_up_interruptible(&ctrl->queue);
}
- if (!(intr_loc & ~CMD_INTR_PENDING))
- goto out;
-
- for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
- /* To find out which slot has interrupt pending */
- if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
- continue;
-
- slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
- dbg("%s: Slot %x with intr, slot register = %x\n",
- __FUNCTION__, hp_slot, slot_reg);
-
- if (slot_reg & MRL_CHANGE_DETECTED)
- php_ctlr->switch_change_callback(
- hp_slot, php_ctlr->callback_instance_id);
-
- if (slot_reg & BUTTON_PRESS_DETECTED)
- php_ctlr->attention_button_callback(
- hp_slot, php_ctlr->callback_instance_id);
-
- if (slot_reg & PRSNT_CHANGE_DETECTED)
- php_ctlr->presence_change_callback(
- hp_slot , php_ctlr->callback_instance_id);
+ if ((intr_loc = (intr_loc >> 1)) == 0) {
+ /* Unmask Global Interrupt Mask */
+ temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
+ temp_dword &= 0xfffffffe;
+ writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
- if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))
- php_ctlr->power_fault_callback(
- hp_slot, php_ctlr->callback_instance_id);
+ return IRQ_NONE;
+ }
- /* Clear all slot events */
- slot_reg &= ~SLOT_REG_RSVDZ_MASK;
- shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
+ for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
+ /* To find out which slot has interrupt pending */
+ if ((intr_loc >> hp_slot) & 0x01) {
+ temp_dword = readl(php_ctlr->creg + SLOT1 + (4*hp_slot));
+ dbg("%s: Slot %x with intr, slot register = %x\n",
+ __FUNCTION__, hp_slot, temp_dword);
+ temp_byte = (temp_dword >> 16) & 0xFF;
+ if ((php_ctlr->switch_change_callback) && (temp_byte & 0x08))
+ schedule_flag += php_ctlr->switch_change_callback(
+ hp_slot, php_ctlr->callback_instance_id);
+ if ((php_ctlr->attention_button_callback) && (temp_byte & 0x04))
+ schedule_flag += php_ctlr->attention_button_callback(
+ hp_slot, php_ctlr->callback_instance_id);
+ if ((php_ctlr->presence_change_callback) && (temp_byte & 0x01))
+ schedule_flag += php_ctlr->presence_change_callback(
+ hp_slot , php_ctlr->callback_instance_id);
+ if ((php_ctlr->power_fault_callback) && (temp_byte & 0x12))
+ schedule_flag += php_ctlr->power_fault_callback(
+ hp_slot, php_ctlr->callback_instance_id);
+
+ /* Clear all slot events */
+ temp_dword = 0xe01f3fff;
+ writel(temp_dword, php_ctlr->creg + SLOT1 + (4*hp_slot));
+
+ intr_loc2 = readl(php_ctlr->creg + INTR_LOC);
+ dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
+ }
}
- out:
if (!shpchp_poll_mode) {
/* Unmask Global Interrupt Mask */
- serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
- serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
- shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
+ temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
+ temp_dword &= 0xfffffffe;
+ writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
}
return IRQ_HANDLED;
static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
{
- int retval = 0;
- struct controller *ctrl = slot->ctrl;
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
- u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
- u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
- u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
+ int retval = 0;
+ u8 pi;
+ u32 slot_avail1, slot_avail2;
DBG_ENTER_ROUTINE
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
+ }
+
+ if (slot->hp_slot >= php_ctlr->num_slots) {
+ err("%s: Invalid HPC slot number!\n", __FUNCTION__);
+ return -1;
+ }
+
+ pi = readb(php_ctlr->creg + PROG_INTERFACE);
+ slot_avail1 = readl(php_ctlr->creg + SLOT_AVAIL1);
+ slot_avail2 = readl(php_ctlr->creg + SLOT_AVAIL2);
+
if (pi == 2) {
if (slot_avail2 & SLOT_133MHZ_PCIX_533)
- bus_speed = PCI_SPEED_133MHz_PCIX_533;
+ bus_speed = PCIX_133MHZ_533;
else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
- bus_speed = PCI_SPEED_100MHz_PCIX_533;
+ bus_speed = PCIX_100MHZ_533;
else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
- bus_speed = PCI_SPEED_66MHz_PCIX_533;
+ bus_speed = PCIX_66MHZ_533;
else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
- bus_speed = PCI_SPEED_133MHz_PCIX_266;
+ bus_speed = PCIX_133MHZ_266;
else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
- bus_speed = PCI_SPEED_100MHz_PCIX_266;
+ bus_speed = PCIX_100MHZ_266;
else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
- bus_speed = PCI_SPEED_66MHz_PCIX_266;
- }
-
- if (bus_speed == PCI_SPEED_UNKNOWN) {
+ bus_speed = PCIX_66MHZ_266;
+ else if (slot_avail1 & SLOT_133MHZ_PCIX)
+ bus_speed = PCIX_133MHZ;
+ else if (slot_avail1 & SLOT_100MHZ_PCIX)
+ bus_speed = PCIX_100MHZ;
+ else if (slot_avail1 & SLOT_66MHZ_PCIX)
+ bus_speed = PCIX_66MHZ;
+ else if (slot_avail2 & SLOT_66MHZ)
+ bus_speed = PCI_66MHZ;
+ else if (slot_avail1 & SLOT_33MHZ)
+ bus_speed = PCI_33MHZ;
+ else bus_speed = PCI_SPEED_UNKNOWN;
+ } else {
if (slot_avail1 & SLOT_133MHZ_PCIX)
- bus_speed = PCI_SPEED_133MHz_PCIX;
+ bus_speed = PCIX_133MHZ;
else if (slot_avail1 & SLOT_100MHZ_PCIX)
- bus_speed = PCI_SPEED_100MHz_PCIX;
+ bus_speed = PCIX_100MHZ;
else if (slot_avail1 & SLOT_66MHZ_PCIX)
- bus_speed = PCI_SPEED_66MHz_PCIX;
+ bus_speed = PCIX_66MHZ;
else if (slot_avail2 & SLOT_66MHZ)
- bus_speed = PCI_SPEED_66MHz;
+ bus_speed = PCI_66MHZ;
else if (slot_avail1 & SLOT_33MHZ)
- bus_speed = PCI_SPEED_33MHz;
- else
- retval = -ENODEV;
+ bus_speed = PCI_33MHZ;
+ else bus_speed = PCI_SPEED_UNKNOWN;
}
*value = bus_speed;
static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
{
- int retval = 0;
- struct controller *ctrl = slot->ctrl;
+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
- u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
- u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
- u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
+ u16 sec_bus_status;
+ int retval = 0;
+ u8 pi;
DBG_ENTER_ROUTINE
- if ((pi == 1) && (speed_mode > 4)) {
- *value = PCI_SPEED_UNKNOWN;
- return -ENODEV;
+ if (!slot->ctrl->hpc_ctlr_handle) {
+ err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
+ return -1;
}
- switch (speed_mode) {
- case 0x0:
- *value = PCI_SPEED_33MHz;
- break;
- case 0x1:
- *value = PCI_SPEED_66MHz;
- break;
- case 0x2:
- *value = PCI_SPEED_66MHz_PCIX;
- break;
- case 0x3:
- *value = PCI_SPEED_100MHz_PCIX;
- break;
- case 0x4:
- *value = PCI_SPEED_133MHz_PCIX;
- break;
- case 0x5:
- *value = PCI_SPEED_66MHz_PCIX_ECC;
- break;
- case 0x6:
- *value = PCI_SPEED_100MHz_PCIX_ECC;
- break;
- case 0x7:
- *value = PCI_SPEED_133MHz_PCIX_ECC;
- break;
- case 0x8:
- *value = PCI_SPEED_66MHz_PCIX_266;
- break;
- case 0x9:
- *value = PCI_SPEED_100MHz_PCIX_266;
- break;
- case 0xa:
- *value = PCI_SPEED_133MHz_PCIX_266;
- break;
- case 0xb:
- *value = PCI_SPEED_66MHz_PCIX_533;
- break;
- case 0xc:
- *value = PCI_SPEED_100MHz_PCIX_533;
- break;
- case 0xd:
- *value = PCI_SPEED_133MHz_PCIX_533;
- break;
- default:
- *value = PCI_SPEED_UNKNOWN;
- retval = -ENODEV;
- break;
+ if (slot->hp_slot >= php_ctlr->num_slots) {
+ err("%s: Invalid HPC slot number!\n", __FUNCTION__);
+ return -1;
}
+ pi = readb(php_ctlr->creg + PROG_INTERFACE);
+ sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
+
+ if (pi == 2) {
+ switch (sec_bus_status & 0x000f) {
+ case 0:
+ bus_speed = PCI_SPEED_33MHz;
+ break;
+ case 1:
+ bus_speed = PCI_SPEED_66MHz;
+ break;
+ case 2:
+ bus_speed = PCI_SPEED_66MHz_PCIX;
+ break;
+ case 3:
+ bus_speed = PCI_SPEED_100MHz_PCIX;
+ break;
+ case 4:
+ bus_speed = PCI_SPEED_133MHz_PCIX;
+ break;
+ case 5:
+ bus_speed = PCI_SPEED_66MHz_PCIX_ECC;
+ break;
+ case 6:
+ bus_speed = PCI_SPEED_100MHz_PCIX_ECC;
+ break;
+ case 7:
+ bus_speed = PCI_SPEED_133MHz_PCIX_ECC;
+ break;
+ case 8:
+ bus_speed = PCI_SPEED_66MHz_PCIX_266;
+ break;
+ case 9:
+ bus_speed = PCI_SPEED_100MHz_PCIX_266;
+ break;
+ case 0xa:
+ bus_speed = PCI_SPEED_133MHz_PCIX_266;
+ break;
+ case 0xb:
+ bus_speed = PCI_SPEED_66MHz_PCIX_533;
+ break;
+ case 0xc:
+ bus_speed = PCI_SPEED_100MHz_PCIX_533;
+ break;
+ case 0xd:
+ bus_speed = PCI_SPEED_133MHz_PCIX_533;
+ break;
+ case 0xe:
+ case 0xf:
+ default:
+ bus_speed = PCI_SPEED_UNKNOWN;
+ break;
+ }
+ } else {
+ /* In the case where pi is undefined, default it to 1 */
+ switch (sec_bus_status & 0x0007) {
+ case 0:
+ bus_speed = PCI_SPEED_33MHz;
+ break;
+ case 1:
+ bus_speed = PCI_SPEED_66MHz;
+ break;
+ case 2:
+ bus_speed = PCI_SPEED_66MHz_PCIX;
+ break;
+ case 3:
+ bus_speed = PCI_SPEED_100MHz_PCIX;
+ break;
+ case 4:
+ bus_speed = PCI_SPEED_133MHz_PCIX;
+ break;
+ case 5:
+ bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
+ break;
+ case 6:
+ bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
+ break;
+ case 7:
+ bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
+ break;
+ default:
+ bus_speed = PCI_SPEED_UNKNOWN;
+ break;
+ }
+ }
+
+ *value = bus_speed;
dbg("Current bus speed = %d\n", bus_speed);
DBG_LEAVE_ROUTINE
return retval;
.green_led_blink = hpc_set_green_led_blink,
.release_ctlr = hpc_release_ctlr,
+ .check_cmd_status = hpc_check_cmd_status,
};
+inline static int shpc_indirect_creg_read(struct controller *ctrl, int index,
+ u32 *value)
+{
+ int rc;
+ u32 cap_offset = ctrl->cap_offset;
+ struct pci_dev *pdev = ctrl->pci_dev;
+
+ rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
+ if (rc)
+ return rc;
+ return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
+}
+
int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
{
struct php_ctlr_state_s *php_ctlr, *p;
void *instance_id = ctrl;
int rc, num_slots = 0;
u8 hp_slot;
+ static int first = 1;
u32 shpc_base_offset;
- u32 tempdword, slot_reg, slot_config;
+ u32 tempdword, slot_reg;
u8 i;
DBG_ENTER_ROUTINE
ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
spin_lock_init(&list_lock);
- php_ctlr = kzalloc(sizeof(*php_ctlr), GFP_KERNEL);
+ php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL);
if (!php_ctlr) { /* allocate controller state data */
err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
goto abort;
}
+ memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s));
+
php_ctlr->pci_dev = pdev; /* save pci_dev in context */
if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
}
dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset);
- rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
+ rc = shpc_indirect_creg_read(ctrl, 0, &shpc_base_offset);
if (rc) {
err("%s: cannot read base_offset\n", __FUNCTION__);
goto abort_free_ctlr;
}
- rc = shpc_indirect_read(ctrl, 3, &tempdword);
+ rc = shpc_indirect_creg_read(ctrl, 3, &tempdword);
if (rc) {
err("%s: cannot read slot config\n", __FUNCTION__);
goto abort_free_ctlr;
dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots);
for (i = 0; i < 9 + num_slots; i++) {
- rc = shpc_indirect_read(ctrl, i, &tempdword);
+ rc = shpc_indirect_creg_read(ctrl, i, &tempdword);
if (rc) {
err("%s: cannot read creg (index = %d)\n",
__FUNCTION__, i);
ctrl->mmio_size = 0x24 + 0x4 * num_slots;
}
+ if (first) {
+ spin_lock_init(&hpc_event_lock);
+ first = 0;
+ }
+
info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
pdev->subsystem_device);
}
dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg);
- mutex_init(&ctrl->crit_sect);
- mutex_init(&ctrl->cmd_lock);
-
+ init_MUTEX(&ctrl->crit_sect);
/* Setup wait queue */
init_waitqueue_head(&ctrl->queue);
php_ctlr->power_fault_callback = shpchp_handle_power_fault;
php_ctlr->callback_instance_id = instance_id;
- ctrl->hpc_ctlr_handle = php_ctlr;
- ctrl->hpc_ops = &shpchp_hpc_ops;
-
/* Return PCI Controller Info */
- slot_config = shpc_readl(ctrl, SLOT_CONFIG);
- php_ctlr->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
- php_ctlr->num_slots = slot_config & SLOT_NUM;
+ php_ctlr->slot_device_offset = (readl(php_ctlr->creg + SLOT_CONFIG) & FIRST_DEV_NUM ) >> 8;
+ php_ctlr->num_slots = readl(php_ctlr->creg + SLOT_CONFIG) & SLOT_NUM;
dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset);
dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots);
/* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
- tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
+ tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
- tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
- COMMAND_INTR_MASK | ARBITER_SERR_MASK);
- tempdword &= ~SERR_INTR_RSVDZ_MASK;
- shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
- tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
+ tempdword = 0x0003000f;
+ writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE);
+ tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
/* Mask the MRL sensor SERR Mask of individual slot in
* Slot SERR-INT Mask & clear all the existing event if any
*/
for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
- slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
+ slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot );
dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
hp_slot, slot_reg);
- slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
- BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
- CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
- CON_PFAULT_SERR_MASK);
- slot_reg &= ~SLOT_REG_RSVDZ_MASK;
- shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
+ tempdword = 0xffff3fff;
+ writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot));
}
if (shpchp_poll_mode) {/* Install interrupt polling code */
} else
php_ctlr->irq = pdev->irq;
- rc = request_irq(php_ctlr->irq, shpc_isr, IRQF_SHARED, MY_NAME, (void *) ctrl);
+ rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
if (rc) {
err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
}
spin_unlock(&list_lock);
- ctlr_seq_num++;
- /*
- * If this is the first controller to be initialized,
- * initialize the shpchpd work queue
- */
- if (atomic_add_return(1, &shpchp_num_controllers) == 1) {
- shpchp_wq = create_singlethread_workqueue("shpchpd");
- if (!shpchp_wq)
- return -ENOMEM;
- }
+ ctlr_seq_num++;
+ ctrl->hpc_ctlr_handle = php_ctlr;
+ ctrl->hpc_ops = &shpchp_hpc_ops;
- /*
- * Unmask all event interrupts of all slots
- */
for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
- slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
+ slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot );
dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
hp_slot, slot_reg);
- slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
- BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
- CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
- shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
+ tempdword = 0xe01f3fff;
+ writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot));
}
if (!shpchp_poll_mode) {
/* Unmask all general input interrupts and SERR */
- tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
- tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
- SERR_INTR_RSVDZ_MASK);
- shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
- tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
+ tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
+ tempdword = 0x0000000a;
+ writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE);
+ tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
}
git://git.onelab.eu / linux-2.6.git / blobdiff