and other provisions required by the GPL. If you do not delete
the provisions above, a recipient may use your version of this
file under either the MPL or the GPL.
-
+
======================================================================*/
#if !defined(_PCMCIA_SA1100_H)
# define _PCMCIA_SA1100_H
-#include <pcmcia/cs_types.h>
-#include <pcmcia/ss.h>
-#include <pcmcia/bulkmem.h>
-#include <pcmcia/cistpl.h>
-#include "cs_internal.h"
-#include "sa1100_generic.h"
+/* SA-1100 PCMCIA Memory and I/O timing
+ * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+ * The SA-1110 Developer's Manual, section 10.2.5, says the following:
+ *
+ * "To calculate the recommended BS_xx value for each address space:
+ * divide the command width time (the greater of twIOWR and twIORD,
+ * or the greater of twWE and twOE) by processor cycle time; divide
+ * by 2; divide again by 3 (number of BCLK's per command assertion);
+ * round up to the next whole number; and subtract 1."
+ */
/* MECR: Expansion Memory Configuration Register
* (SA-1100 Developers Manual, p.10-13; SA-1110 Developers Manual, p.10-24)
*
- * MECR layout is:
+ * MECR layout is:
*
* FAST1 BSM1<4:0> BSA1<4:0> BSIO1<4:0> FAST0 BSM0<4:0> BSA0<4:0> BSIO0<4:0>
*
return (t / 1000000) + (((t % 1000000) == 0) ? 0 : 1);
}
-/* This function returns the (approxmiate) command assertion period, in
+/* This function returns the (approximate) command assertion period, in
* nanoseconds, for a given CPU clock frequency and MECR BS value:
*/
static inline unsigned int sa1100_pcmcia_cmd_time(unsigned int cpu_clock_khz,
}
-/* SA-1100 PCMCIA Memory and I/O timing
- * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
- * The SA-1110 Developer's Manual, section 10.2.5, says the following:
- *
- * "To calculate the recommended BS_xx value for each address space:
- * divide the command width time (the greater of twIOWR and twIORD,
- * or the greater of twWE and twOE) by processor cycle time; divide
- * by 2; divide again by 3 (number of BCLK's per command assertion);
- * round up to the next whole number; and subtract 1."
- *
- * The PC Card Standard, Release 7, section 4.13.4, says that twIORD
- * has a minimum value of 165ns. Section 4.13.5 says that twIOWR has
- * a minimum value of 165ns, as well. Section 4.7.2 (describing
- * common and attribute memory write timing) says that twWE has a
- * minimum value of 150ns for a 250ns cycle time (for 5V operation;
- * see section 4.7.4), or 300ns for a 600ns cycle time (for 3.3V
- * operation, also section 4.7.4). Section 4.7.3 says that taOE
- * has a maximum value of 150ns for a 300ns cycle time (for 5V
- * operation), or 300ns for a 600ns cycle time (for 3.3V operation).
- *
- * When configuring memory maps, Card Services appears to adopt the policy
- * that a memory access time of "0" means "use the default." The default
- * PCMCIA I/O command width time is 165ns. The default PCMCIA 5V attribute
- * and memory command width time is 150ns; the PCMCIA 3.3V attribute and
- * memory command width time is 300ns.
- */
-#define SA1100_PCMCIA_IO_ACCESS (165)
-#define SA1100_PCMCIA_5V_MEM_ACCESS (150)
-#define SA1100_PCMCIA_3V_MEM_ACCESS (300)
-
-
-/* The socket driver actually works nicely in interrupt-driven form,
- * so the (relatively infrequent) polling is "just to be sure."
- */
-#define SA1100_PCMCIA_POLL_PERIOD (2*HZ)
-
-struct pcmcia_low_level;
-
-/* I/O pins replacing memory pins
- * (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75)
- *
- * These signals change meaning when going from memory-only to
- * memory-or-I/O interface:
- */
-#define iostschg bvd1
-#define iospkr bvd2
+extern int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr);
#endif /* !defined(_PCMCIA_SA1100_H) */
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