* QLogic QLA1280 (Ultra2) and QLA12160 (Ultra3) SCSI driver
* Copyright (C) 2000 Qlogic Corporation (www.qlogic.com)
* Copyright (C) 2001-2004 Jes Sorensen, Wild Open Source Inc.
-* Copyright (C) 2003 Christoph Hellwig
+* Copyright (C) 2003-2004 Christoph Hellwig
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* General Public License for more details.
*
******************************************************************************/
-#define QLA1280_VERSION "3.24.3"
+#define QLA1280_VERSION "3.24.4"
/*****************************************************************************
Revision History:
+ Rev 3.24.4 June 7, 2004 Christoph Hellwig
+ - restructure firmware loading, cleanup initialization code
+ - prepare support for ISP1020/1040 chips
Rev 3.24.3 January 19, 2004, Jes Sorensen
- Handle PCI DMA mask settings correctly
- Correct order of error handling in probe_one, free_irq should not
#define ia64_platform_is(foo) (!strcmp(x, platform_name))
#endif
+
+#define IS_ISP1040(ha) (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP1020)
+#define IS_ISP1x40(ha) (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP1020 || \
+ ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP1240)
+#define IS_ISP1x160(ha) (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP10160 || \
+ ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP12160)
+
+
static int qla1280_probe_one(struct pci_dev *, const struct pci_device_id *);
static void qla1280_remove_one(struct pci_dev *);
/*
* QLogic ISP1280 Hardware Support Function Prototypes.
*/
-static int qla1280_isp_firmware(struct scsi_qla_host *);
-static int qla1280_chip_diag(struct scsi_qla_host *);
-static int qla1280_setup_chip(struct scsi_qla_host *);
+static int qla1280_load_firmware(struct scsi_qla_host *);
static int qla1280_init_rings(struct scsi_qla_host *);
static int qla1280_nvram_config(struct scsi_qla_host *);
static int qla1280_mailbox_command(struct scsi_qla_host *,
uint8_t mr;
uint16_t mb[MAILBOX_REGISTER_COUNT];
struct nvram *nv;
- int is1x160, status;
+ int status;
nv = &ha->nvram;
- if (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP12160 ||
- ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP10160)
- is1x160 = 1;
- else
- is1x160 = 0;
-
mr = BIT_3 | BIT_2 | BIT_1 | BIT_0;
/* Set Target Parameters. */
mb[2] = (nv->bus[bus].target[target].parameter.c << 8);
- if (is1x160)
- mb[3] = nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8;
- else
- mb[3] = nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8;
- mb[3] |= nv->bus[bus].target[target].sync_period;
-
- if (is1x160) {
+ if (IS_ISP1x160(ha)) {
mb[2] |= nv->bus[bus].target[target].ppr_1x160.flags.enable_ppr << 5;
- mb[6] = nv->bus[bus].target[target].ppr_1x160.flags.ppr_options << 8;
- mb[6] |= nv->bus[bus].target[target].ppr_1x160.flags.ppr_bus_width;
+ mb[3] = (nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8) |
+ nv->bus[bus].target[target].sync_period;
+ mb[6] = (nv->bus[bus].target[target].ppr_1x160.flags.ppr_options << 8) |
+ nv->bus[bus].target[target].ppr_1x160.flags.ppr_bus_width;
mr |= BIT_6;
+ } else {
+ mb[3] = (nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8) |
+ nv->bus[bus].target[target].sync_period;
}
status = qla1280_mailbox_command(ha, mr, &mb[0]);
(driver_setup.wide_mask &&
(~driver_setup.wide_mask & (1 << target))))
nv->bus[bus].target[target].parameter.f.enable_wide = 0;
- if (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP12160 ||
- ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP10160) {
+ if (IS_ISP1x160(ha)) {
if (driver_setup.no_ppr ||
(driver_setup.ppr_mask &&
(~driver_setup.ppr_mask & (1 << target))))
*/
spin_lock_irqsave(HOST_LOCK, flags);
#endif
- /* If firmware needs to be loaded */
- if (qla1280_isp_firmware(ha)) {
- if (!(status = qla1280_chip_diag(ha))) {
- status = qla1280_setup_chip(ha);
- }
- } else {
- printk(KERN_ERR "scsi(%li): isp_firmware() failed!\n",
- ha->host_no);
- status = 1;
- }
+ status = qla1280_load_firmware(ha);
if (status) {
printk(KERN_ERR "scsi(%li): initialize: pci probe failed!\n",
ha->host_no);
dprintk(1, "scsi(%ld): Configure NVRAM parameters\n", ha->host_no);
qla1280_nvram_config(ha);
- if (!ha->flags.disable_host_adapter && !qla1280_init_rings(ha)) {
- /* Issue SCSI reset. */
- /* dg 03/13 if we can't reset twice then bus is dead */
- for (bus = 0; bus < ha->ports; bus++) {
- if (!ha->bus_settings[bus].disable_scsi_reset){
- if (qla1280_bus_reset(ha, bus)) {
- if (qla1280_bus_reset(ha, bus)) {
- ha->bus_settings[bus].scsi_bus_dead = 1;
- }
- }
- }
- }
+ if (ha->flags.disable_host_adapter) {
+ status = 1;
+ goto out;
+ }
- /*
- * qla1280_bus_reset() will take care of issueing markers,
- * no need to do that here as well!
- */
-#if 0
- /* Issue marker command. */
- ha->flags.reset_marker = 0;
- for (bus = 0; bus < ha->ports; bus++) {
- ha->bus_settings[bus].reset_marker = 0;
- qla1280_marker(ha, bus, 0, 0, MK_SYNC_ALL);
- }
-#endif
+ status = qla1280_init_rings(ha);
+ if (status)
+ goto out;
- ha->flags.online = 1;
- } else
- status = 1;
+ /* Issue SCSI reset, if we can't reset twice then bus is dead */
+ for (bus = 0; bus < ha->ports; bus++) {
+ if (!ha->bus_settings[bus].disable_scsi_reset &&
+ qla1280_bus_reset(ha, bus) &&
+ qla1280_bus_reset(ha, bus))
+ ha->bus_settings[bus].scsi_bus_dead = 1;
+ }
+ ha->flags.online = 1;
out:
#if LINUX_VERSION_CODE >= 0x020500
spin_unlock_irqrestore(HOST_LOCK, flags);
int status = 0;
int cnt;
uint16_t data;
-
dprintk(3, "qla1280_chip_diag: testing device at 0x%p \n", ®->id_l);
dprintk(1, "scsi(%ld): Verifying chip\n", ha->host_no);
/* Soft reset chip and wait for it to finish. */
WRT_REG_WORD(®->ictrl, ISP_RESET);
+
/*
* We can't do a traditional PCI write flush here by reading
* back the register. The card will not respond once the reset
data = RD_REG_WORD(®->ictrl);
}
- if (cnt) {
- /* Reset register cleared by chip reset. */
- dprintk(3, "qla1280_chip_diag: reset register cleared by "
- "chip reset\n");
+ if (!cnt)
+ goto fail;
- WRT_REG_WORD(®->cfg_1, 0);
+ /* Reset register cleared by chip reset. */
+ dprintk(3, "qla1280_chip_diag: reset register cleared by chip reset\n");
- /* Reset RISC and disable BIOS which
- allows RISC to execute out of RAM. */
-#if 0
- WRT_REG_WORD(®->host_cmd, HC_RESET_RISC);
- RD_REG_WORD(®->id_l); /* Flush PCI write */
- WRT_REG_WORD(®->host_cmd, HC_RELEASE_RISC);
- RD_REG_WORD(®->id_l); /* Flush PCI write */
- WRT_REG_WORD(®->host_cmd, HC_DISABLE_BIOS);
-#else
- WRT_REG_WORD(®->host_cmd, HC_RESET_RISC |
- HC_RELEASE_RISC | HC_DISABLE_BIOS);
-#endif
- RD_REG_WORD(®->id_l); /* Flush PCI write */
- data = qla1280_debounce_register(®->mailbox0);
- /*
- * I *LOVE* this code!
- */
- for (cnt = 1000000; cnt && data == MBS_BUSY; cnt--) {
- udelay(5);
- data = RD_REG_WORD(®->mailbox0);
- }
+ WRT_REG_WORD(®->cfg_1, 0);
- if (cnt) {
- /* Check product ID of chip */
- dprintk(3, "qla1280_chip_diag: Checking product "
- "ID of chip\n");
-
- if (RD_REG_WORD(®->mailbox1) != PROD_ID_1 ||
- (RD_REG_WORD(®->mailbox2) != PROD_ID_2 &&
- RD_REG_WORD(®->mailbox2) != PROD_ID_2a) ||
- RD_REG_WORD(®->mailbox3) != PROD_ID_3 ||
- RD_REG_WORD(®->mailbox4) != PROD_ID_4) {
- printk(KERN_INFO "qla1280: Wrong product ID = "
- "0x%x,0x%x,0x%x,0x%x\n",
- RD_REG_WORD(®->mailbox1),
- RD_REG_WORD(®->mailbox2),
- RD_REG_WORD(®->mailbox3),
- RD_REG_WORD(®->mailbox4));
- status = 1;
- } else {
- /*
- * Enable ints early!!!
- */
- qla1280_enable_intrs(ha);
-
- dprintk(1, "qla1280_chip_diag: Checking "
- "mailboxes of chip\n");
- /* Wrap Incoming Mailboxes Test. */
- mb[0] = MBC_MAILBOX_REGISTER_TEST;
- mb[1] = 0xAAAA;
- mb[2] = 0x5555;
- mb[3] = 0xAA55;
- mb[4] = 0x55AA;
- mb[5] = 0xA5A5;
- mb[6] = 0x5A5A;
- mb[7] = 0x2525;
- if (!(status = qla1280_mailbox_command(ha,
- 0xff,
- &mb
- [0]))) {
- if (mb[1] != 0xAAAA ||
- mb[2] != 0x5555 ||
- mb[3] != 0xAA55 ||
- mb[4] != 0x55AA ||
- mb[5] != 0xA5A5 ||
- mb[6] != 0x5A5A ||
- mb[7] != 0x2525) {
- status = 1;
- printk(KERN_INFO "qla1280: "
- "Failed mbox check\n");
- }
- }
- }
- } else
- status = 1;
- } else
- status = 1;
+ /* Reset RISC and disable BIOS which
+ allows RISC to execute out of RAM. */
+ WRT_REG_WORD(®->host_cmd, HC_RESET_RISC |
+ HC_RELEASE_RISC | HC_DISABLE_BIOS);
+ RD_REG_WORD(®->id_l); /* Flush PCI write */
+ data = qla1280_debounce_register(®->mailbox0);
+
+ /*
+ * I *LOVE* this code!
+ */
+ for (cnt = 1000000; cnt && data == MBS_BUSY; cnt--) {
+ udelay(5);
+ data = RD_REG_WORD(®->mailbox0);
+ }
+
+ if (!cnt)
+ goto fail;
+
+ /* Check product ID of chip */
+ dprintk(3, "qla1280_chip_diag: Checking product ID of chip\n");
+
+ if (RD_REG_WORD(®->mailbox1) != PROD_ID_1 ||
+ (RD_REG_WORD(®->mailbox2) != PROD_ID_2 &&
+ RD_REG_WORD(®->mailbox2) != PROD_ID_2a) ||
+ RD_REG_WORD(®->mailbox3) != PROD_ID_3 ||
+ RD_REG_WORD(®->mailbox4) != PROD_ID_4) {
+ printk(KERN_INFO "qla1280: Wrong product ID = "
+ "0x%x,0x%x,0x%x,0x%x\n",
+ RD_REG_WORD(®->mailbox1),
+ RD_REG_WORD(®->mailbox2),
+ RD_REG_WORD(®->mailbox3),
+ RD_REG_WORD(®->mailbox4));
+ goto fail;
+ }
+
+ /*
+ * Enable ints early!!!
+ */
+ qla1280_enable_intrs(ha);
+
+ dprintk(1, "qla1280_chip_diag: Checking mailboxes of chip\n");
+ /* Wrap Incoming Mailboxes Test. */
+ mb[0] = MBC_MAILBOX_REGISTER_TEST;
+ mb[1] = 0xAAAA;
+ mb[2] = 0x5555;
+ mb[3] = 0xAA55;
+ mb[4] = 0x55AA;
+ mb[5] = 0xA5A5;
+ mb[6] = 0x5A5A;
+ mb[7] = 0x2525;
+
+ status = qla1280_mailbox_command(ha, 0xff, mb);
if (status)
- dprintk(2, "qla1280_chip_diag: **** FAILED ****\n");
- else
- dprintk(3, "qla1280_chip_diag: exiting normally\n");
+ goto fail;
+
+ if (mb[1] != 0xAAAA || mb[2] != 0x5555 || mb[3] != 0xAA55 ||
+ mb[4] != 0x55AA || mb[5] != 0xA5A5 || mb[6] != 0x5A5A ||
+ mb[7] != 0x2525) {
+ printk(KERN_INFO "qla1280: Failed mbox check\n");
+ goto fail;
+ }
+ dprintk(3, "qla1280_chip_diag: exiting normally\n");
+ return 0;
+ fail:
+ dprintk(2, "qla1280_chip_diag: **** FAILED ****\n");
return status;
}
-/*
- * Setup chip
- * Load and start RISC firmware.
- *
- * Input:
- * ha = adapter block pointer.
- *
- * Returns:
- * 0 = success.
- */
-#define DUMP_IT_BACK 0 /* for debug of RISC loading */
static int
-qla1280_setup_chip(struct scsi_qla_host *ha)
+qla1280_load_firmware_pio(struct scsi_qla_host *ha)
{
- int status = 0;
- uint16_t risc_address;
- uint16_t *risc_code_address;
- int risc_code_size;
- uint16_t mb[MAILBOX_REGISTER_COUNT];
- uint16_t cnt;
- int num, i;
-#if DUMP_IT_BACK
- uint8_t *sp;
- uint8_t *tbuf;
- dma_addr_t p_tbuf;
-#endif
+ uint16_t risc_address, *risc_code_address, risc_code_size;
+ uint16_t mb[MAILBOX_REGISTER_COUNT], i;
+ int err;
- ENTER("qla1280_setup_chip");
+ /* Load RISC code. */
+ risc_address = *ql1280_board_tbl[ha->devnum].fwstart;
+ risc_code_address = ql1280_board_tbl[ha->devnum].fwcode;
+ risc_code_size = *ql1280_board_tbl[ha->devnum].fwlen;
+
+ for (i = 0; i < risc_code_size; i++) {
+ mb[0] = MBC_WRITE_RAM_WORD;
+ mb[1] = risc_address + i;
+ mb[2] = risc_code_address[i];
+
+ err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb);
+ if (err) {
+ printk(KERN_ERR "scsi(%li): Failed to load firmware\n",
+ ha->host_no);
+ return err;
+ }
+ }
- dprintk(1, "scsi(%ld): Setup chip\n", ha->host_no);
+ return 0;
+}
+#define DUMP_IT_BACK 0 /* for debug of RISC loading */
+static int
+qla1280_load_firmware_dma(struct scsi_qla_host *ha)
+{
+ uint16_t risc_address, *risc_code_address, risc_code_size;
+ uint16_t mb[MAILBOX_REGISTER_COUNT], cnt;
+ int err = 0, num, i;
#if DUMP_IT_BACK
- /* get consistent memory allocated for setup_chip */
+ uint8_t *sp, *tbuf;
+ dma_addr_t p_tbuf;
+
tbuf = pci_alloc_consistent(ha->pdev, 8000, &p_tbuf);
+ if (!tbuf)
+ return -ENOMEM;
#endif
/* Load RISC code. */
risc_address = *ql1280_board_tbl[ha->devnum].fwstart;
risc_code_address = ql1280_board_tbl[ha->devnum].fwcode;
- risc_code_size = (int) *ql1280_board_tbl[ha->devnum].fwlen;
+ risc_code_size = *ql1280_board_tbl[ha->devnum].fwlen;
- dprintk(1, "qla1280_setup_chip: DMA RISC code (%i) words\n",
- risc_code_size);
+ dprintk(1, "%s: DMA RISC code (%i) words\n",
+ __FUNCTION__, risc_code_size);
num = 0;
- while (risc_code_size > 0 && !status) {
+ while (risc_code_size > 0) {
int warn __attribute__((unused)) = 0;
cnt = 2000 >> 1;
mb[2] = (ha->request_dma >> 16) & 0xffff;
mb[7] = pci_dma_hi32(ha->request_dma) & 0xffff;
mb[6] = pci_dma_hi32(ha->request_dma) >> 16;
- dprintk(2, "qla1280_setup_chip: op=%d 0x%p = 0x%4x,0x%4x,"
- "0x%4x,0x%4x\n", mb[0], (void *)(long)ha->request_dma,
- mb[6], mb[7], mb[2], mb[3]);
- if ((status = qla1280_mailbox_command(ha, BIT_4 | BIT_3 |
- BIT_2 | BIT_1 | BIT_0,
- &mb[0]))) {
+ dprintk(2, "%s: op=%d 0x%p = 0x%4x,0x%4x,0x%4x,0x%4x\n",
+ __FUNCTION__, mb[0],
+ (void *)(long)ha->request_dma,
+ mb[6], mb[7], mb[2], mb[3]);
+ err = qla1280_mailbox_command(ha, BIT_4 | BIT_3 | BIT_2 |
+ BIT_1 | BIT_0, mb);
+ if (err) {
printk(KERN_ERR "scsi(%li): Failed to load partial "
"segment of f\n", ha->host_no);
- break;
+ goto out;
}
#if DUMP_IT_BACK
mb[7] = pci_dma_hi32(p_tbuf) & 0xffff;
mb[6] = pci_dma_hi32(p_tbuf) >> 16;
- if ((status = qla1280_mailbox_command(ha,
- BIT_4 | BIT_3 | BIT_2 |
- BIT_1 | BIT_0,
- &mb[0]))) {
+ err = qla1280_mailbox_command(ha, BIT_4 | BIT_3 | BIT_2 |
+ BIT_1 | BIT_0, mb);
+ if (err) {
printk(KERN_ERR
"Failed to dump partial segment of f/w\n");
- break;
+ goto out;
}
sp = (uint8_t *)ha->request_ring;
for (i = 0; i < (cnt << 1); i++) {
if (tbuf[i] != sp[i] && warn++ < 10) {
- printk(KERN_ERR "qla1280_setup_chip: FW "
- "compare error @ byte(0x%x) loop#=%x\n",
- i, num);
- printk(KERN_ERR "setup_chip: FWbyte=%x "
- "FWfromChip=%x\n", sp[i], tbuf[i]);
+ printk(KERN_ERR "%s: FW compare error @ "
+ "byte(0x%x) loop#=%x\n",
+ __FUNCTION__, i, num);
+ printk(KERN_ERR "%s: FWbyte=%x "
+ "FWfromChip=%x\n",
+ __FUNCTION__, sp[i], tbuf[i]);
/*break; */
}
}
num++;
}
+ out:
+#if DUMP_IT_BACK
+ pci_free_consistent(ha->pdev, 8000, tbuf, p_tbuf);
+#endif
+ return err;
+}
+
+static int
+qla1280_start_firmware(struct scsi_qla_host *ha)
+{
+ uint16_t mb[MAILBOX_REGISTER_COUNT];
+ int err;
+
+ dprintk(1, "%s: Verifying checksum of loaded RISC code.\n",
+ __FUNCTION__);
+
/* Verify checksum of loaded RISC code. */
- if (!status) {
- dprintk(1, "qla1280_setup_chip: Verifying checksum of "
- "loaded RISC code.\n");
- mb[0] = MBC_VERIFY_CHECKSUM;
- /* mb[1] = ql12_risc_code_addr01; */
- mb[1] = *ql1280_board_tbl[ha->devnum].fwstart;
+ mb[0] = MBC_VERIFY_CHECKSUM;
+ /* mb[1] = ql12_risc_code_addr01; */
+ mb[1] = *ql1280_board_tbl[ha->devnum].fwstart;
+ err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
+ if (err) {
+ printk(KERN_ERR "scsi(%li): Failed checksum\n", ha->host_no);
+ return err;
+ }
- if (!(status =
- qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]))) {
- /* Start firmware execution. */
- dprintk(1,
- "qla1280_setup_chip: start firmware running.\n");
- mb[0] = MBC_EXECUTE_FIRMWARE;
- mb[1] = *ql1280_board_tbl[ha->devnum].fwstart;
- qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
- } else
- printk(KERN_ERR "scsi(%li): qla1280_setup_chip: "
- "Failed checksum\n", ha->host_no);
+ /* Start firmware execution. */
+ dprintk(1, "%s: start firmware running.\n", __FUNCTION__);
+ mb[0] = MBC_EXECUTE_FIRMWARE;
+ mb[1] = *ql1280_board_tbl[ha->devnum].fwstart;
+ err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
+ if (err) {
+ printk(KERN_ERR "scsi(%li): Failed to start firmware\n",
+ ha->host_no);
}
-#if DUMP_IT_BACK
- /* free consistent memory allocated for setup_chip */
- pci_free_consistent(ha->pdev, 8000, tbuf, p_tbuf);
-#endif
+ return err;
+}
- if (status)
- dprintk(2, "qla1280_setup_chip: **** FAILED ****\n");
+static int
+qla1280_load_firmware(struct scsi_qla_host *ha)
+{
+ int err = -ENODEV;
- LEAVE("qla1280_setup_chip");
- return status;
+ /* If firmware needs to be loaded */
+ if (!qla1280_isp_firmware(ha)) {
+ printk(KERN_ERR "scsi(%li): isp_firmware() failed!\n",
+ ha->host_no);
+ goto out;
+ }
+
+ err = qla1280_chip_diag(ha);
+ if (err)
+ goto out;
+ if (IS_ISP1040(ha))
+ err = qla1280_load_firmware_pio(ha);
+ else
+ err = qla1280_load_firmware_dma(ha);
+ if (err)
+ goto out;
+ err = qla1280_start_firmware(ha);
+ out:
+ return err;
}
/*
return status;
}
-/*
- * NVRAM configuration.
- *
- * Input:
- * ha = adapter block pointer.
- * ha->request_ring = request ring virtual address
- *
- * Output:
- * host adapters parameters in host adapter block
- *
- * Returns:
- * 0 = success.
- */
-static int
-qla1280_nvram_config(struct scsi_qla_host *ha)
+static void
+qla1280_print_settings(struct nvram *nv)
{
- struct device_reg *reg = ha->iobase;
- struct nvram *nv;
- int is1x160, status = 0;
- int bus, target, lun;
- uint16_t mb[MAILBOX_REGISTER_COUNT];
- uint16_t mask;
-
- ENTER("qla1280_nvram_config");
-
- if (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP12160 ||
- ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP10160)
- is1x160 = 1;
- else
- is1x160 = 0;
-
- nv = &ha->nvram;
- if (!ha->nvram_valid) {
- dprintk(1, "Using defaults for NVRAM: \n");
- memset(nv, 0, sizeof(struct nvram));
-
- /* nv->cntr_flags_1.disable_loading_risc_code = 1; */
- nv->firmware_feature.f.enable_fast_posting = 1;
- nv->firmware_feature.f.disable_synchronous_backoff = 1;
-
- nv->termination.f.scsi_bus_0_control = 3;
- nv->termination.f.scsi_bus_1_control = 3;
- nv->termination.f.auto_term_support = 1;
-
- /*
- * Set default FIFO magic - What appropriate values
- * would be here is unknown. This is what I have found
- * testing with 12160s.
- * Now, I would love the magic decoder ring for this one,
- * the header file provided by QLogic seems to be bogus
- * or incomplete at best.
- */
- nv->isp_config.c = 0x44;
-
- if (is1x160)
- nv->isp_parameter = 0x01;
-
- for (bus = 0; bus < MAX_BUSES; bus++) {
- nv->bus[bus].config_1.initiator_id = 7;
- nv->bus[bus].bus_reset_delay = 5;
- /* 8 = 5.0 clocks */
- nv->bus[bus].config_2.async_data_setup_time = 8;
- nv->bus[bus].config_2.req_ack_active_negation = 1;
- nv->bus[bus].config_2.data_line_active_negation = 1;
- nv->bus[bus].selection_timeout = 250;
- nv->bus[bus].max_queue_depth = 256;
-
- for (target = 0; target < MAX_TARGETS; target++) {
- nv->bus[bus].target[target].parameter.f.
- renegotiate_on_error = 1;
- nv->bus[bus].target[target].parameter.f.
- auto_request_sense = 1;
- nv->bus[bus].target[target].parameter.f.
- tag_queuing = 1;
- nv->bus[bus].target[target].parameter.f.
- enable_sync = 1;
-#if 1 /* Some SCSI Processors do not seem to like this */
- nv->bus[bus].target[target].parameter.f.
- enable_wide = 1;
-#endif
- nv->bus[bus].target[target].parameter.f.
- parity_checking = 1;
- nv->bus[bus].target[target].parameter.f.
- disconnect_allowed = 1;
- nv->bus[bus].target[target].execution_throttle=
- nv->bus[bus].max_queue_depth - 1;
- if (is1x160) {
- nv->bus[bus].target[target].flags.
- flags1x160.device_enable = 1;
- nv->bus[bus].target[target].flags.
- flags1x160.sync_offset = 0x0e;
- nv->bus[bus].target[target].
- sync_period = 9;
- nv->bus[bus].target[target].
- ppr_1x160.flags.enable_ppr = 1;
- nv->bus[bus].target[target].ppr_1x160.
- flags.ppr_options = 2;
- nv->bus[bus].target[target].ppr_1x160.
- flags.ppr_bus_width = 1;
- } else {
- nv->bus[bus].target[target].flags.
- flags1x80.device_enable = 1;
- nv->bus[bus].target[target].flags.
- flags1x80.sync_offset = 0x8;
- nv->bus[bus].target[target].
- sync_period = 10;
- }
- }
- }
- } else {
- /* Always force AUTO sense for LINUX SCSI */
- for (bus = 0; bus < MAX_BUSES; bus++)
- for (target = 0; target < MAX_TARGETS; target++) {
- nv->bus[bus].target[target].parameter.f.
- auto_request_sense = 1;
- }
- }
dprintk(1, "qla1280 : initiator scsi id bus[0]=%d\n",
nv->bus[0].config_1.initiator_id);
dprintk(1, "qla1280 : initiator scsi id bus[1]=%d\n",
nv->bus[0].max_queue_depth);
dprintk(1, "qla1280 : max queue depth[1]=%d\n",
nv->bus[1].max_queue_depth);
+}
+
+static void
+qla1280_set_target_defaults(struct scsi_qla_host *ha, int bus, int target)
+{
+ struct nvram *nv = &ha->nvram;
+
+ nv->bus[bus].target[target].parameter.f.renegotiate_on_error = 1;
+ nv->bus[bus].target[target].parameter.f.auto_request_sense = 1;
+ nv->bus[bus].target[target].parameter.f.tag_queuing = 1;
+ nv->bus[bus].target[target].parameter.f.enable_sync = 1;
+#if 1 /* Some SCSI Processors do not seem to like this */
+ nv->bus[bus].target[target].parameter.f.enable_wide = 1;
+#endif
+ if (!IS_ISP1040(ha))
+ nv->bus[bus].target[target].parameter.f.parity_checking = 1;
+
+ nv->bus[bus].target[target].parameter.f.disconnect_allowed = 1;
+ nv->bus[bus].target[target].execution_throttle =
+ nv->bus[bus].max_queue_depth - 1;
+
+ if (IS_ISP1x160(ha)) {
+ nv->bus[bus].target[target].flags.flags1x160.device_enable = 1;
+ nv->bus[bus].target[target].flags.flags1x160.sync_offset = 0x0e;
+ nv->bus[bus].target[target].sync_period = 9;
+ nv->bus[bus].target[target].ppr_1x160.flags.enable_ppr = 1;
+ nv->bus[bus].target[target].ppr_1x160.flags.ppr_options = 2;
+ nv->bus[bus].target[target].ppr_1x160.flags.ppr_bus_width = 1;
+ } else {
+ nv->bus[bus].target[target].flags.flags1x80.device_enable = 1;
+ nv->bus[bus].target[target].flags.flags1x80.sync_offset = 12;
+ nv->bus[bus].target[target].sync_period = 10;
+ }
+}
+
+static void
+qla1280_set_defaults(struct scsi_qla_host *ha)
+{
+ struct nvram *nv = &ha->nvram;
+ int bus, target;
+
+ dprintk(1, "Using defaults for NVRAM: \n");
+ memset(nv, 0, sizeof(struct nvram));
+
+ /* nv->cntr_flags_1.disable_loading_risc_code = 1; */
+ nv->firmware_feature.f.enable_fast_posting = 1;
+ nv->firmware_feature.f.disable_synchronous_backoff = 1;
+ nv->termination.f.scsi_bus_0_control = 3;
+ nv->termination.f.scsi_bus_1_control = 3;
+ nv->termination.f.auto_term_support = 1;
+
+ /*
+ * Set default FIFO magic - What appropriate values would be here
+ * is unknown. This is what I have found testing with 12160s.
+ *
+ * Now, I would love the magic decoder ring for this one, the
+ * header file provided by QLogic seems to be bogus or incomplete
+ * at best.
+ */
+ nv->isp_config.c = ISP_CFG1_BENAB|ISP_CFG1_F128;
+ if (IS_ISP1x160(ha))
+ nv->isp_parameter = 0x01; /* fast memory enable */
+
+ for (bus = 0; bus < MAX_BUSES; bus++) {
+ nv->bus[bus].config_1.initiator_id = 7;
+ nv->bus[bus].config_2.req_ack_active_negation = 1;
+ nv->bus[bus].config_2.data_line_active_negation = 1;
+ nv->bus[bus].selection_timeout = 250;
+ nv->bus[bus].max_queue_depth = 256;
+
+ if (IS_ISP1040(ha)) {
+ nv->bus[bus].bus_reset_delay = 3;
+ nv->bus[bus].config_2.async_data_setup_time = 6;
+ nv->bus[bus].retry_delay = 1;
+ } else {
+ nv->bus[bus].bus_reset_delay = 5;
+ nv->bus[bus].config_2.async_data_setup_time = 8;
+ }
+
+ for (target = 0; target < MAX_TARGETS; target++)
+ qla1280_set_target_defaults(ha, bus, target);
+ }
+}
+
+static int
+qla1280_config_target(struct scsi_qla_host *ha, int bus, int target)
+{
+ struct nvram *nv = &ha->nvram;
+ uint16_t mb[MAILBOX_REGISTER_COUNT];
+ int status, lun;
+
+ /* Set Target Parameters. */
+ mb[0] = MBC_SET_TARGET_PARAMETERS;
+ mb[1] = (uint16_t) (bus ? target | BIT_7 : target);
+ mb[1] <<= 8;
+
+ /*
+ * Do not enable wide, sync, and ppr for the initial
+ * INQUIRY run. We enable this later if we determine
+ * the target actually supports it.
+ */
+ nv->bus[bus].target[target].parameter.f.
+ auto_request_sense = 1;
+ nv->bus[bus].target[target].parameter.f.
+ stop_queue_on_check = 0;
+
+ if (IS_ISP1x160(ha))
+ nv->bus[bus].target[target].ppr_1x160.
+ flags.enable_ppr = 0;
+
+ /*
+ * No sync, wide, etc. while probing
+ */
+ mb[2] = (nv->bus[bus].target[target].parameter.c << 8) &
+ ~(TP_SYNC /*| TP_WIDE | TP_PPR*/);
+
+ if (IS_ISP1x160(ha))
+ mb[3] = nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8;
+ else
+ mb[3] = nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8;
+ mb[3] |= nv->bus[bus].target[target].sync_period;
+
+ status = qla1280_mailbox_command(ha, BIT_3 | BIT_2 | BIT_1 | BIT_0, &mb[0]);
+
+ /* Save Tag queuing enable flag. */
+ mb[0] = BIT_0 << target;
+ if (nv->bus[bus].target[target].parameter.f.tag_queuing)
+ ha->bus_settings[bus].qtag_enables |= mb[0];
+
+ /* Save Device enable flag. */
+ if (IS_ISP1x160(ha)) {
+ if (nv->bus[bus].target[target].flags.flags1x160.device_enable)
+ ha->bus_settings[bus].device_enables |= mb[0];
+ ha->bus_settings[bus].lun_disables |= 0;
+ } else {
+ if (nv->bus[bus].target[target].flags.flags1x80.device_enable)
+ ha->bus_settings[bus].device_enables |= mb[0];
+ /* Save LUN disable flag. */
+ if (nv->bus[bus].target[target].flags.flags1x80.lun_disable)
+ ha->bus_settings[bus].lun_disables |= mb[0];
+ }
+
+ /* Set Device Queue Parameters. */
+ for (lun = 0; lun < MAX_LUNS; lun++) {
+ mb[0] = MBC_SET_DEVICE_QUEUE;
+ mb[1] = (uint16_t)(bus ? target | BIT_7 : target);
+ mb[1] = mb[1] << 8 | lun;
+ mb[2] = nv->bus[bus].max_queue_depth;
+ mb[3] = nv->bus[bus].target[target].execution_throttle;
+ status |= qla1280_mailbox_command(ha, 0x0f, &mb[0]);
+ }
+
+ return status;
+}
+
+static int
+qla1280_config_bus(struct scsi_qla_host *ha, int bus)
+{
+ struct nvram *nv = &ha->nvram;
+ uint16_t mb[MAILBOX_REGISTER_COUNT];
+ int target, status;
+
+ /* SCSI Reset Disable. */
+ ha->bus_settings[bus].disable_scsi_reset =
+ nv->bus[bus].config_1.scsi_reset_disable;
+
+ /* Initiator ID. */
+ ha->bus_settings[bus].id = nv->bus[bus].config_1.initiator_id;
+ mb[0] = MBC_SET_INITIATOR_ID;
+ mb[1] = bus ? ha->bus_settings[bus].id | BIT_7 :
+ ha->bus_settings[bus].id;
+ status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
+
+ /* Reset Delay. */
+ ha->bus_settings[bus].bus_reset_delay =
+ nv->bus[bus].bus_reset_delay;
+
+ /* Command queue depth per device. */
+ ha->bus_settings[bus].hiwat = nv->bus[bus].max_queue_depth - 1;
+
+ /* Set target parameters. */
+ for (target = 0; target < MAX_TARGETS; target++)
+ status |= qla1280_config_target(ha, bus, target);
+
+ return status;
+}
+
+static int
+qla1280_nvram_config(struct scsi_qla_host *ha)
+{
+ struct device_reg *reg = ha->iobase;
+ struct nvram *nv = &ha->nvram;
+ int bus, target, status = 0;
+ uint16_t mb[MAILBOX_REGISTER_COUNT];
+ uint16_t mask;
+
+ ENTER("qla1280_nvram_config");
+
+ if (ha->nvram_valid) {
+ /* Always force AUTO sense for LINUX SCSI */
+ for (bus = 0; bus < MAX_BUSES; bus++)
+ for (target = 0; target < MAX_TARGETS; target++) {
+ nv->bus[bus].target[target].parameter.f.
+ auto_request_sense = 1;
+ }
+ } else {
+ qla1280_set_defaults(ha);
+ }
+
+ qla1280_print_settings(nv);
/* Disable RISC load of firmware. */
ha->flags.disable_risc_code_load =
nv->cntr_flags_1.disable_loading_risc_code;
- /* Set ISP hardware DMA burst */
- mb[0] = nv->isp_config.c;
- /* Enable DMA arbitration on dual channel controllers */
- if (ha->ports > 1)
- mb[0] |= BIT_13;
- WRT_REG_WORD(®->cfg_1, mb[0]);
-
-#if 1 /* Is this safe? */
- /* Set SCSI termination. */
- WRT_REG_WORD(®->gpio_enable, (BIT_3 + BIT_2 + BIT_1 + BIT_0));
- mb[0] = nv->termination.c & (BIT_3 + BIT_2 + BIT_1 + BIT_0);
- WRT_REG_WORD(®->gpio_data, mb[0]);
-#endif
+ if (IS_ISP1040(ha)) {
+ uint16_t hwrev, cfg1, cdma_conf, ddma_conf;
+
+ hwrev = RD_REG_WORD(®->cfg_0) & ISP_CFG0_HWMSK;
+
+ cfg1 = RD_REG_WORD(®->cfg_1);
+ cdma_conf = RD_REG_WORD(®->cdma_cfg);
+ ddma_conf = RD_REG_WORD(®->ddma_cfg);
+
+ /* Busted fifo, says mjacob. */
+ if (hwrev == ISP_CFG0_1040A)
+ WRT_REG_WORD(®->cfg_1, cfg1 | ISP_CFG1_F64);
+ else
+ WRT_REG_WORD(®->cfg_1, cfg1 | ISP_CFG1_F64 | ISP_CFG1_BENAB);
+
+ WRT_REG_WORD(®->cdma_cfg, cdma_conf | CDMA_CONF_BENAB);
+ WRT_REG_WORD(®->ddma_cfg, cdma_conf | DDMA_CONF_BENAB);
+ } else {
+ /* Set ISP hardware DMA burst */
+ mb[0] = nv->isp_config.c;
+ /* Enable DMA arbitration on dual channel controllers */
+ if (ha->ports > 1)
+ mb[0] |= BIT_13;
+ WRT_REG_WORD(®->cfg_1, mb[0]);
+
+ /* Set SCSI termination. */
+ WRT_REG_WORD(®->gpio_enable, (BIT_3 + BIT_2 + BIT_1 + BIT_0));
+ mb[0] = nv->termination.c & (BIT_3 + BIT_2 + BIT_1 + BIT_0);
+ WRT_REG_WORD(®->gpio_data, mb[0]);
+ }
/* ISP parameter word. */
mb[0] = MBC_SET_SYSTEM_PARAMETER;
mb[1] = nv->isp_parameter;
status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
-#if 0
- /* clock rate - for qla1240 and older, only */
- mb[0] = MBC_SET_CLOCK_RATE;
- mb[1] = 0x50;
- status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
-#endif
+ if (IS_ISP1x40(ha)) {
+ /* clock rate - for qla1240 and older, only */
+ mb[0] = MBC_SET_CLOCK_RATE;
+ mb[1] = 40;
+ status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
+ }
+
/* Firmware feature word. */
mb[0] = MBC_SET_FIRMWARE_FEATURES;
mask = BIT_5 | BIT_1 | BIT_0;
mb[2] = 2; /* Command DMA Channel Burst Enable */
status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
+ mb[0] = MBC_SET_TAG_AGE_LIMIT;
+ mb[1] = 8;
+ status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
+
/* Selection timeout. */
mb[0] = MBC_SET_SELECTION_TIMEOUT;
mb[1] = nv->bus[0].selection_timeout;
mb[2] = nv->bus[1].selection_timeout;
status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
- for (bus = 0; bus < ha->ports; bus++) {
- /* SCSI Reset Disable. */
- ha->bus_settings[bus].disable_scsi_reset =
- nv->bus[bus].config_1.scsi_reset_disable;
-
- /* Initiator ID. */
- ha->bus_settings[bus].id = nv->bus[bus].config_1.initiator_id;
- mb[0] = MBC_SET_INITIATOR_ID;
- mb[1] = bus ? ha->bus_settings[bus].id | BIT_7 :
- ha->bus_settings[bus].id;
- status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
-
- /* Reset Delay. */
- ha->bus_settings[bus].bus_reset_delay =
- nv->bus[bus].bus_reset_delay;
-
- /* Command queue depth per device. */
- ha->bus_settings[bus].hiwat = nv->bus[bus].max_queue_depth - 1;
-
- /* Set target parameters. */
- for (target = 0; target < MAX_TARGETS; target++) {
- uint8_t mr = BIT_2 | BIT_1 | BIT_0;
-
- /* Set Target Parameters. */
- mb[0] = MBC_SET_TARGET_PARAMETERS;
- mb[1] = (uint16_t) (bus ? target | BIT_7 : target);
- mb[1] <<= 8;
- /*
- * Do not enable wide, sync, and ppr for the initial
- * INQUIRY run. We enable this later if we determine
- * the target actually supports it.
- */
- nv->bus[bus].target[target].parameter.f.
- auto_request_sense = 1;
- nv->bus[bus].target[target].parameter.f.
- stop_queue_on_check = 0;
-
- if (is1x160)
- nv->bus[bus].target[target].ppr_1x160.
- flags.enable_ppr = 0;
- /*
- * No sync, wide, etc. while probing
- */
- mb[2] = (nv->bus[bus].target[target].parameter.c << 8)&
- ~(TP_SYNC /*| TP_WIDE | TP_PPR*/);
-
- if (is1x160)
- mb[3] = nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8;
- else
- mb[3] = nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8;
- mb[3] |= nv->bus[bus].target[target].sync_period;
- mr |= BIT_3;
-
- /*
- * We don't want to enable ppr etc. before we have
- * determined that the target actually supports it
- */
-#if 0
- if (is1x160) {
- mb[2] |= nv->bus[bus].target[target].ppr_1x160.flags.enable_ppr << 5;
-
- mb[6] = nv->bus[bus].target[target].ppr_1x160.flags.ppr_options << 8;
- mb[6] |= nv->bus[bus].target[target].ppr_1x160.flags.ppr_bus_width;
- mr |= BIT_6;
- }
-#endif
-
- status = qla1280_mailbox_command(ha, mr, &mb[0]);
-
- /* Save Tag queuing enable flag. */
- mb[0] = BIT_0 << target;
- if (nv->bus[bus].target[target].parameter.f.tag_queuing)
- ha->bus_settings[bus].qtag_enables |= mb[0];
-
- /* Save Device enable flag. */
- if (is1x160) {
- if (nv->bus[bus].target[target].flags.flags1x160.device_enable)
- ha->bus_settings[bus].device_enables |= mb[0];
- ha->bus_settings[bus].lun_disables |= 0;
- } else {
- if (nv->bus[bus].target[target].flags.flags1x80.device_enable)
- ha->bus_settings[bus].device_enables |= mb[0];
- /* Save LUN disable flag. */
- if (nv->bus[bus].target[target].flags.flags1x80.lun_disable)
- ha->bus_settings[bus].lun_disables |= mb[0];
- }
-
-
- /* Set Device Queue Parameters. */
- for (lun = 0; lun < MAX_LUNS; lun++) {
- mb[0] = MBC_SET_DEVICE_QUEUE;
- mb[1] = (uint16_t)(bus ? target | BIT_7 : target);
- mb[1] = mb[1] << 8 | lun;
- mb[2] = nv->bus[bus].max_queue_depth;
- mb[3] = nv->bus[bus].target[target].execution_throttle;
- status |= qla1280_mailbox_command(ha, 0x0f,
- &mb[0]);
- }
- }
- }
+ for (bus = 0; bus < ha->ports; bus++)
+ status |= qla1280_config_bus(ha, bus);
if (status)
dprintk(2, "qla1280_nvram_config: **** FAILED ****\n");
static int
qla1280_abort_isp(struct scsi_qla_host *ha)
{
+ struct device_reg *reg = ha->iobase;
struct srb *sp;
int status = 0;
int cnt;
ENTER("qla1280_abort_isp");
- if (!ha->flags.abort_isp_active && ha->flags.online) {
- struct device_reg *reg = ha->iobase;
- ha->flags.abort_isp_active = 1;
-
- /* Disable ISP interrupts. */
- qla1280_disable_intrs(ha);
- WRT_REG_WORD(®->host_cmd, HC_PAUSE_RISC);
- RD_REG_WORD(®->id_l);
+ if (ha->flags.abort_isp_active || !ha->flags.online)
+ goto out;
+
+ ha->flags.abort_isp_active = 1;
- printk(KERN_INFO "scsi(%li): dequeuing outstanding commands\n",
- ha->host_no);
- /* Dequeue all commands in outstanding command list. */
- for (cnt = 0; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
- struct scsi_cmnd *cmd;
- sp = ha->outstanding_cmds[cnt];
- if (sp) {
+ /* Disable ISP interrupts. */
+ qla1280_disable_intrs(ha);
+ WRT_REG_WORD(®->host_cmd, HC_PAUSE_RISC);
+ RD_REG_WORD(®->id_l);
- cmd = sp->cmd;
- CMD_RESULT(cmd) = DID_RESET << 16;
+ printk(KERN_INFO "scsi(%li): dequeuing outstanding commands\n",
+ ha->host_no);
+ /* Dequeue all commands in outstanding command list. */
+ for (cnt = 0; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
+ struct scsi_cmnd *cmd;
+ sp = ha->outstanding_cmds[cnt];
+ if (sp) {
- sp->cmd = NULL;
- ha->outstanding_cmds[cnt] = NULL;
+ cmd = sp->cmd;
+ CMD_RESULT(cmd) = DID_RESET << 16;
- (*cmd->scsi_done)(cmd);
+ sp->cmd = NULL;
+ ha->outstanding_cmds[cnt] = NULL;
- sp->flags = 0;
- }
- }
+ (*cmd->scsi_done)(cmd);
- /* If firmware needs to be loaded */
- if (qla1280_isp_firmware (ha)) {
- if (!(status = qla1280_chip_diag(ha)))
- status = qla1280_setup_chip(ha);
+ sp->flags = 0;
}
+ }
- if (!status) {
- /* Setup adapter based on NVRAM parameters. */
- qla1280_nvram_config (ha);
+ status = qla1280_load_firmware(ha);
+ if (status)
+ goto out;
- if (!(status = qla1280_init_rings(ha))) {
- /* Issue SCSI reset. */
- for (bus = 0; bus < ha->ports; bus++) {
- qla1280_bus_reset(ha, bus);
- }
- /*
- * qla1280_bus_reset() will do the marker
- * dance - no reason to repeat here!
- */
-#if 0
- /* Issue marker command. */
- ha->flags.reset_marker = 0;
- for (bus = 0; bus < ha->ports; bus++) {
- ha->bus_settings[bus].
- reset_marker = 0;
- qla1280_marker(ha, bus, 0, 0,
- MK_SYNC_ALL);
- }
-#endif
- ha->flags.abort_isp_active = 0;
- }
- }
- }
+ /* Setup adapter based on NVRAM parameters. */
+ qla1280_nvram_config (ha);
+ status = qla1280_init_rings(ha);
+ if (status)
+ goto out;
+
+ /* Issue SCSI reset. */
+ for (bus = 0; bus < ha->ports; bus++)
+ qla1280_bus_reset(ha, bus);
+
+ ha->flags.abort_isp_active = 0;
+ out:
if (status) {
printk(KERN_WARNING
"qla1280: ISP error recovery failed, board disabled");
MODULE_AUTHOR("Qlogic & Jes Sorensen");
MODULE_DESCRIPTION("Qlogic ISP SCSI (qla1x80/qla1x160) driver");
MODULE_LICENSE("GPL");
+MODULE_VERSION(QLA1280_VERSION);
/*
* Overrides for Emacs so that we almost follow Linus's tabbing style.
git://git.onelab.eu / linux-2.6.git / blobdiff