/*
- * QLOGIC LINUX SOFTWARE
- *
- * QLogic ISP2x00 device driver for Linux 2.6.x
- * Copyright (C) 2003-2004 QLogic Corporation
- * (www.qlogic.com)
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2, or (at your option) any
- * later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
+ * QLogic Fibre Channel HBA Driver
+ * Copyright (c) 2003-2005 QLogic Corporation
*
+ * See LICENSE.qla2xxx for copyright and licensing details.
*/
#include "qla_def.h"
uint16_t mb0, mb2;
uint32_t stat;
- device_reg_t __iomem *reg = ha->iobase;
+ struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
uint16_t __iomem *dmp_reg;
unsigned long flags;
struct qla2300_fw_dump *fw;
fw->hccr = RD_REG_WORD(®->hccr);
/* Pause RISC. */
- WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
+ WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
if (IS_QLA2300(ha)) {
for (cnt = 30000;
(RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
if (rval == QLA_SUCCESS) {
dmp_reg = (uint16_t __iomem *)(reg + 0);
- for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
- for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
fw->risc_host_reg[cnt] = RD_REG_WORD(dmp_reg++);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x40);
- for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->ctrl_status, 0x40);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++)
fw->resp_dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->ctrl_status, 0x50);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->ctrl_status, 0x00);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
- for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2000);
+ WRT_REG_WORD(®->pcr, 0x2000);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2200);
+ WRT_REG_WORD(®->pcr, 0x2200);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2400);
+ WRT_REG_WORD(®->pcr, 0x2400);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2600);
+ WRT_REG_WORD(®->pcr, 0x2600);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2800);
+ WRT_REG_WORD(®->pcr, 0x2800);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2A00);
+ WRT_REG_WORD(®->pcr, 0x2A00);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2C00);
+ WRT_REG_WORD(®->pcr, 0x2C00);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2E00);
+ WRT_REG_WORD(®->pcr, 0x2E00);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->ctrl_status, 0x10);
+ WRT_REG_WORD(®->ctrl_status, 0x10);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->ctrl_status, 0x20);
+ WRT_REG_WORD(®->ctrl_status, 0x20);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->ctrl_status, 0x30);
+ WRT_REG_WORD(®->ctrl_status, 0x30);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
/* Reset RISC. */
fw = ha->fw_dump;
qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
- qla2x00_get_fw_version_str(ha, fw_info));
+ ha->isp_ops.fw_version_str(ha, fw_info));
qla_uprintf(&uiter, "\n[==>BEG]\n");
uint32_t cnt, timer;
uint16_t risc_address;
uint16_t mb0, mb2;
- device_reg_t __iomem *reg = ha->iobase;
+ struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
uint16_t __iomem *dmp_reg;
unsigned long flags;
struct qla2100_fw_dump *fw;
fw->hccr = RD_REG_WORD(®->hccr);
/* Pause RISC. */
- WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
+ WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
rval == QLA_SUCCESS; cnt--) {
if (cnt)
}
if (rval == QLA_SUCCESS) {
dmp_reg = (uint16_t __iomem *)(reg + 0);
- for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
}
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x20);
- for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->ctrl_status, 0x00);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
- for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2000);
+ WRT_REG_WORD(®->pcr, 0x2000);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2100);
+ WRT_REG_WORD(®->pcr, 0x2100);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2200);
+ WRT_REG_WORD(®->pcr, 0x2200);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2300);
+ WRT_REG_WORD(®->pcr, 0x2300);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2400);
+ WRT_REG_WORD(®->pcr, 0x2400);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2500);
+ WRT_REG_WORD(®->pcr, 0x2500);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2600);
+ WRT_REG_WORD(®->pcr, 0x2600);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->pcr, 0x2700);
+ WRT_REG_WORD(®->pcr, 0x2700);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->ctrl_status, 0x10);
+ WRT_REG_WORD(®->ctrl_status, 0x10);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->ctrl_status, 0x20);
+ WRT_REG_WORD(®->ctrl_status, 0x20);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
- WRT_REG_WORD(®->ctrl_status, 0x30);
+ WRT_REG_WORD(®->ctrl_status, 0x30);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
- for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
+ for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
/* Reset the ISP. */
if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
(RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) {
- WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
+ WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
for (cnt = 30000;
(RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
rval == QLA_SUCCESS; cnt--) {
fw = ha->fw_dump;
qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
- qla2x00_get_fw_version_str(ha, fw_info));
+ ha->isp_ops.fw_version_str(ha, fw_info));
qla_uprintf(&uiter, "\n[==>BEG]\n");
int iter, len;
char buf[128];
va_list args;
-
+
va_start(args, fmt);
len = vsprintf(buf, fmt, args);
va_end(args);
return (len);
}
-//FIXME
+
+void
+qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
+{
+ int rval;
+ uint32_t cnt, timer;
+ uint32_t risc_address;
+ uint16_t mb[4], wd;
+
+ uint32_t stat;
+ struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
+ uint32_t __iomem *dmp_reg;
+ uint32_t *iter_reg;
+ uint16_t __iomem *mbx_reg;
+ unsigned long flags;
+ struct qla24xx_fw_dump *fw;
+ uint32_t ext_mem_cnt;
+
+ risc_address = ext_mem_cnt = 0;
+ memset(mb, 0, sizeof(mb));
+ flags = 0;
+
+ if (!hardware_locked)
+ spin_lock_irqsave(&ha->hardware_lock, flags);
+
+ if (!ha->fw_dump24) {
+ qla_printk(KERN_WARNING, ha,
+ "No buffer available for dump!!!\n");
+ goto qla24xx_fw_dump_failed;
+ }
+
+ if (ha->fw_dumped) {
+ qla_printk(KERN_WARNING, ha,
+ "Firmware has been previously dumped (%p) -- ignoring "
+ "request...\n", ha->fw_dump24);
+ goto qla24xx_fw_dump_failed;
+ }
+ fw = (struct qla24xx_fw_dump *) ha->fw_dump24;
+
+ rval = QLA_SUCCESS;
+ fw->host_status = RD_REG_DWORD(®->host_status);
+
+ /* Pause RISC. */
+ if ((RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0) {
+ WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET |
+ HCCRX_CLR_HOST_INT);
+ RD_REG_DWORD(®->hccr); /* PCI Posting. */
+ WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
+ for (cnt = 30000;
+ (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 &&
+ rval == QLA_SUCCESS; cnt--) {
+ if (cnt)
+ udelay(100);
+ else
+ rval = QLA_FUNCTION_TIMEOUT;
+ }
+ }
+
+ if (rval == QLA_SUCCESS) {
+ /* Host interface registers. */
+ dmp_reg = (uint32_t __iomem *)(reg + 0);
+ for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
+ fw->host_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+ /* Disable interrupts. */
+ WRT_REG_DWORD(®->ictrl, 0);
+ RD_REG_DWORD(®->ictrl);
+
+ /* Shadow registers. */
+ WRT_REG_DWORD(®->iobase_addr, 0x0F70);
+ RD_REG_DWORD(®->iobase_addr);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
+ WRT_REG_DWORD(dmp_reg, 0xB0000000);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
+ fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg);
+
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
+ WRT_REG_DWORD(dmp_reg, 0xB0100000);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
+ fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg);
+
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
+ WRT_REG_DWORD(dmp_reg, 0xB0200000);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
+ fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg);
+
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
+ WRT_REG_DWORD(dmp_reg, 0xB0300000);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
+ fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg);
+
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
+ WRT_REG_DWORD(dmp_reg, 0xB0400000);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
+ fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg);
+
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
+ WRT_REG_DWORD(dmp_reg, 0xB0500000);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
+ fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg);
+
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
+ WRT_REG_DWORD(dmp_reg, 0xB0600000);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
+ fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg);
+
+ /* Mailbox registers. */
+ mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
+ for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
+ fw->mailbox_reg[cnt] = RD_REG_WORD(mbx_reg++);
+
+ /* Transfer sequence registers. */
+ iter_reg = fw->xseq_gp_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0xBF00);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xBF10);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xBF20);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xBF30);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xBF40);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xBF50);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xBF60);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xBF70);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xBFE0);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++)
+ fw->xseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xBFF0);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++)
+ fw->xseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+ /* Receive sequence registers. */
+ iter_reg = fw->rseq_gp_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0xFF00);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xFF10);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xFF20);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xFF30);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xFF40);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xFF50);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xFF60);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xFF70);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xFFD0);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++)
+ fw->rseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xFFE0);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++)
+ fw->rseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0xFFF0);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++)
+ fw->rseq_2_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+ /* Command DMA registers. */
+ WRT_REG_DWORD(®->iobase_addr, 0x7100);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++)
+ fw->cmd_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+ /* Queues. */
+ iter_reg = fw->req0_dma_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0x7200);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 8; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
+ for (cnt = 0; cnt < 7; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ iter_reg = fw->resp0_dma_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0x7300);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 8; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
+ for (cnt = 0; cnt < 7; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ iter_reg = fw->req1_dma_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0x7400);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 8; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
+ for (cnt = 0; cnt < 7; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ /* Transmit DMA registers. */
+ iter_reg = fw->xmt0_dma_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0x7600);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x7610);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ iter_reg = fw->xmt1_dma_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0x7620);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x7630);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ iter_reg = fw->xmt2_dma_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0x7640);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x7650);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ iter_reg = fw->xmt3_dma_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0x7660);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x7670);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ iter_reg = fw->xmt4_dma_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0x7680);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x7690);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x76A0);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++)
+ fw->xmt_data_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+ /* Receive DMA registers. */
+ iter_reg = fw->rcvt0_data_dma_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0x7700);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x7710);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ iter_reg = fw->rcvt1_data_dma_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0x7720);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x7730);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ /* RISC registers. */
+ iter_reg = fw->risc_gp_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0x0F00);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x0F10);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x0F20);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x0F30);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x0F40);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x0F50);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x0F60);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x0F70);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ /* Local memory controller registers. */
+ iter_reg = fw->lmc_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0x3000);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x3010);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x3020);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x3030);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x3040);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x3050);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x3060);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ /* Fibre Protocol Module registers. */
+ iter_reg = fw->fpm_hdw_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0x4000);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x4010);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x4020);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x4030);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x4040);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x4050);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x4060);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x4070);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x4080);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x4090);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x40A0);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x40B0);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ /* Frame Buffer registers. */
+ iter_reg = fw->fb_hdw_reg;
+ WRT_REG_DWORD(®->iobase_addr, 0x6000);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x6010);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x6020);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x6030);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x6040);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x6100);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x6130);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x6150);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x6170);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x6190);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ WRT_REG_DWORD(®->iobase_addr, 0x61B0);
+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+ for (cnt = 0; cnt < 16; cnt++)
+ *iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+ /* Reset RISC. */
+ WRT_REG_DWORD(®->ctrl_status,
+ CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
+ for (cnt = 0; cnt < 30000; cnt++) {
+ if ((RD_REG_DWORD(®->ctrl_status) &
+ CSRX_DMA_ACTIVE) == 0)
+ break;
+
+ udelay(10);
+ }
+
+ WRT_REG_DWORD(®->ctrl_status,
+ CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
+ pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
+
+ udelay(100);
+ /* Wait for firmware to complete NVRAM accesses. */
+ mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0);
+ for (cnt = 10000 ; cnt && mb[0]; cnt--) {
+ udelay(5);
+ mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0);
+ barrier();
+ }
+
+ /* Wait for soft-reset to complete. */
+ for (cnt = 0; cnt < 30000; cnt++) {
+ if ((RD_REG_DWORD(®->ctrl_status) &
+ CSRX_ISP_SOFT_RESET) == 0)
+ break;
+
+ udelay(10);
+ }
+ WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET);
+ RD_REG_DWORD(®->hccr); /* PCI Posting. */
+ }
+
+ for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 &&
+ rval == QLA_SUCCESS; cnt--) {
+ if (cnt)
+ udelay(100);
+ else
+ rval = QLA_FUNCTION_TIMEOUT;
+ }
+
+ /* Memory. */
+ if (rval == QLA_SUCCESS) {
+ /* Code RAM. */
+ risc_address = 0x20000;
+ WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED);
+ clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
+ }
+ for (cnt = 0; cnt < sizeof(fw->code_ram) / 4 && rval == QLA_SUCCESS;
+ cnt++, risc_address++) {
+ WRT_REG_WORD(®->mailbox1, LSW(risc_address));
+ WRT_REG_WORD(®->mailbox8, MSW(risc_address));
+ RD_REG_WORD(®->mailbox8);
+ WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT);
+
+ for (timer = 6000000; timer; timer--) {
+ /* Check for pending interrupts. */
+ stat = RD_REG_DWORD(®->host_status);
+ if (stat & HSRX_RISC_INT) {
+ stat &= 0xff;
+
+ if (stat == 0x1 || stat == 0x2 ||
+ stat == 0x10 || stat == 0x11) {
+ set_bit(MBX_INTERRUPT,
+ &ha->mbx_cmd_flags);
+
+ mb[0] = RD_REG_WORD(®->mailbox0);
+ mb[2] = RD_REG_WORD(®->mailbox2);
+ mb[3] = RD_REG_WORD(®->mailbox3);
+
+ WRT_REG_DWORD(®->hccr,
+ HCCRX_CLR_RISC_INT);
+ RD_REG_DWORD(®->hccr);
+ break;
+ }
+
+ /* Clear this intr; it wasn't a mailbox intr */
+ WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
+ RD_REG_DWORD(®->hccr);
+ }
+ udelay(5);
+ }
+
+ if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
+ rval = mb[0] & MBS_MASK;
+ fw->code_ram[cnt] = (mb[3] << 16) | mb[2];
+ } else {
+ rval = QLA_FUNCTION_FAILED;
+ }
+ }
+
+ if (rval == QLA_SUCCESS) {
+ /* External Memory. */
+ risc_address = 0x100000;
+ ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
+ WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED);
+ clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
+ }
+ for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS;
+ cnt++, risc_address++) {
+ WRT_REG_WORD(®->mailbox1, LSW(risc_address));
+ WRT_REG_WORD(®->mailbox8, MSW(risc_address));
+ RD_REG_WORD(®->mailbox8);
+ WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT);
+
+ for (timer = 6000000; timer; timer--) {
+ /* Check for pending interrupts. */
+ stat = RD_REG_DWORD(®->host_status);
+ if (stat & HSRX_RISC_INT) {
+ stat &= 0xff;
+
+ if (stat == 0x1 || stat == 0x2 ||
+ stat == 0x10 || stat == 0x11) {
+ set_bit(MBX_INTERRUPT,
+ &ha->mbx_cmd_flags);
+
+ mb[0] = RD_REG_WORD(®->mailbox0);
+ mb[2] = RD_REG_WORD(®->mailbox2);
+ mb[3] = RD_REG_WORD(®->mailbox3);
+
+ WRT_REG_DWORD(®->hccr,
+ HCCRX_CLR_RISC_INT);
+ RD_REG_DWORD(®->hccr);
+ break;
+ }
+
+ /* Clear this intr; it wasn't a mailbox intr */
+ WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
+ RD_REG_DWORD(®->hccr);
+ }
+ udelay(5);
+ }
+
+ if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
+ rval = mb[0] & MBS_MASK;
+ fw->ext_mem[cnt] = (mb[3] << 16) | mb[2];
+ } else {
+ rval = QLA_FUNCTION_FAILED;
+ }
+ }
+
+ if (rval != QLA_SUCCESS) {
+ qla_printk(KERN_WARNING, ha,
+ "Failed to dump firmware (%x)!!!\n", rval);
+ ha->fw_dumped = 0;
+
+ } else {
+ qla_printk(KERN_INFO, ha,
+ "Firmware dump saved to temp buffer (%ld/%p).\n",
+ ha->host_no, ha->fw_dump24);
+ ha->fw_dumped = 1;
+ }
+
+qla24xx_fw_dump_failed:
+ if (!hardware_locked)
+ spin_unlock_irqrestore(&ha->hardware_lock, flags);
+}
+
+void
+qla24xx_ascii_fw_dump(scsi_qla_host_t *ha)
+{
+ uint32_t cnt;
+ char *uiter;
+ struct qla24xx_fw_dump *fw;
+ uint32_t ext_mem_cnt;
+
+ uiter = ha->fw_dump_buffer;
+ fw = ha->fw_dump24;
+
+ qla_uprintf(&uiter, "ISP FW Version %d.%02d.%02d Attributes %04x\n",
+ ha->fw_major_version, ha->fw_minor_version,
+ ha->fw_subminor_version, ha->fw_attributes);
+
+ qla_uprintf(&uiter, "\nR2H Status Register\n%04x\n", fw->host_status);
+
+ qla_uprintf(&uiter, "\nHost Interface Registers");
+ for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nShadow Registers");
+ for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nMailbox Registers");
+ for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->mailbox_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXSEQ GP Registers");
+ for (cnt = 0; cnt < sizeof(fw->xseq_gp_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xseq_gp_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXSEQ-0 Registers");
+ for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xseq_0_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXSEQ-1 Registers");
+ for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xseq_1_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRSEQ GP Registers");
+ for (cnt = 0; cnt < sizeof(fw->rseq_gp_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->rseq_gp_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRSEQ-0 Registers");
+ for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->rseq_0_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRSEQ-1 Registers");
+ for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->rseq_1_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRSEQ-2 Registers");
+ for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->rseq_2_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nCommand DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->cmd_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRequest0 Queue DMA Channel Registers");
+ for (cnt = 0; cnt < sizeof(fw->req0_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->req0_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nResponse0 Queue DMA Channel Registers");
+ for (cnt = 0; cnt < sizeof(fw->resp0_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->resp0_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRequest1 Queue DMA Channel Registers");
+ for (cnt = 0; cnt < sizeof(fw->req1_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->req1_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXMT0 Data DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->xmt0_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xmt0_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXMT1 Data DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->xmt1_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xmt1_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXMT2 Data DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->xmt2_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xmt2_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXMT3 Data DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->xmt3_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xmt3_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXMT4 Data DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->xmt4_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xmt4_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXMT Data DMA Common Registers");
+ for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xmt_data_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRCV Thread 0 Data DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->rcvt0_data_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->rcvt0_data_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRCV Thread 1 Data DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->rcvt1_data_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->rcvt1_data_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRISC GP Registers");
+ for (cnt = 0; cnt < sizeof(fw->risc_gp_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nLMC Registers");
+ for (cnt = 0; cnt < sizeof(fw->lmc_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->lmc_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nFPM Hardware Registers");
+ for (cnt = 0; cnt < sizeof(fw->fpm_hdw_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->fpm_hdw_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nFB Hardware Registers");
+ for (cnt = 0; cnt < sizeof(fw->fb_hdw_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->fb_hdw_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nCode RAM");
+ for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
+ if (cnt % 8 == 0) {
+ qla_uprintf(&uiter, "\n%08x: ", cnt + 0x20000);
+ }
+ qla_uprintf(&uiter, "%08x ", fw->code_ram[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nExternal Memory");
+ ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
+ for (cnt = 0; cnt < ext_mem_cnt; cnt++) {
+ if (cnt % 8 == 0) {
+ qla_uprintf(&uiter, "\n%08x: ", cnt + 0x100000);
+ }
+ qla_uprintf(&uiter, "%08x ", fw->ext_mem[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n[<==END] ISP Debug Dump");
+}
+
/****************************************************************************/
/* Driver Debug Functions. */
/****************************************************************************/
-void
-qla2x00_dump_regs(scsi_qla_host_t *ha)
+void
+qla2x00_dump_regs(scsi_qla_host_t *ha)
{
- device_reg_t __iomem *reg = ha->iobase;
+ struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
printk("Mailbox registers:\n");
printk("scsi(%ld): mbox 0 0x%04x \n",
void
-qla2x00_dump_buffer(uint8_t * b, uint32_t size)
+qla2x00_dump_buffer(uint8_t * b, uint32_t size)
{
uint32_t cnt;
uint8_t c;
/**************************************************************************
* qla2x00_print_scsi_cmd
* Dumps out info about the scsi cmd and srb.
- * Input
+ * Input
* cmd : struct scsi_cmnd
**************************************************************************/
void
-qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd)
+qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd)
{
int i;
struct scsi_qla_host *ha;
cmd->request_buffer, cmd->request_bufflen);
printk(" tag=%d, transfersize=0x%x\n",
cmd->tag, cmd->transfersize);
- printk(" serial_number=%lx, SP=%p\n", cmd->serial_number, sp);
+ printk(" serial_number=%lx, SP=%p\n", cmd->serial_number, sp);
printk(" data direction=%d\n", cmd->sc_data_direction);
if (!sp)
return;
printk(" sp flags=0x%x\n", sp->flags);
- printk(" r_start=0x%lx, u_start=0x%lx, f_start=0x%lx, state=%d\n",
- sp->r_start, sp->u_start, sp->f_start, sp->state);
+ printk(" state=%d\n", sp->state);
+}
+
+void
+qla2x00_dump_pkt(void *pkt)
+{
+ uint32_t i;
+ uint8_t *data = (uint8_t *) pkt;
+
+ for (i = 0; i < 64; i++) {
+ if (!(i % 4))
+ printk("\n%02x: ", i);
+
+ printk("%02x ", data[i]);
+ }
+ printk("\n");
}
#if defined(QL_DEBUG_ROUTINES)
* count = number of words.
*/
void
-qla2x00_formatted_dump_buffer(char *string, uint8_t * buffer,
- uint8_t wd_size, uint32_t count)
+qla2x00_formatted_dump_buffer(char *string, uint8_t * buffer,
+ uint8_t wd_size, uint32_t count)
{
uint32_t cnt;
uint16_t *buf16;
git://git.onelab.eu / linux-2.6.git / blobdiff