#include <asm/io.h>
#define DRV_NAME "sata_sil24"
-#define DRV_VERSION "0.3"
+#define DRV_VERSION "0.23"
/*
* Port request block (PRB) 32 bytes
*/
struct sil24_prb {
- __le16 ctrl;
- __le16 prot;
- __le32 rx_cnt;
+ u16 ctrl;
+ u16 prot;
+ u32 rx_cnt;
u8 fis[6 * 4];
};
* Scatter gather entry (SGE) 16 bytes
*/
struct sil24_sge {
- __le64 addr;
- __le32 cnt;
- __le32 flags;
+ u64 addr;
+ u32 cnt;
+ u32 flags;
};
/*
* Port multiplier
*/
struct sil24_port_multiplier {
- __le32 diag;
- __le32 sactive;
+ u32 diag;
+ u32 sactive;
};
enum {
/* HOST_SLOT_STAT bits */
HOST_SSTAT_ATTN = (1 << 31),
- /* HOST_CTRL bits */
- HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
- HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
- HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
- HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
- HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
- HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
-
/*
* Port registers
* (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
*/
PORT_REGS_SIZE = 0x2000,
-
- PORT_LRAM = 0x0000, /* 31 LRAM slots and PM regs */
- PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
+ PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
/* 32 bit regs */
PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
- PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
- PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
- PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
- PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
- PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
- PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
-
- DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
- PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
- PORT_IRQ_UNK_FIS,
+ PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */
+ PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */
/* bits[27:16] are unmasked (raw) */
PORT_IRQ_RAW_SHIFT = 16,
PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
- PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
+ PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */
PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
SGE_DRD = (1 << 29), /* discard data read (/dev/null)
data address ignored */
- SIL24_MAX_CMDS = 31,
-
/* board id */
BID_SIL3124 = 0,
BID_SIL3132 = 1,
BID_SIL3131 = 2,
- /* host flags */
- SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
- ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
- ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY,
- SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
-
IRQ_STAT_4PORTS = 0xf,
};
struct sil24_atapi_block atapi;
};
-static struct sil24_cerr_info {
- unsigned int err_mask, action;
- const char *desc;
-} sil24_cerr_db[] = {
- [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
- "device error" },
- [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
- "device error via D2H FIS" },
- [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
- "device error via SDB FIS" },
- [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
- "error in data FIS" },
- [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
- "failed to transmit command FIS" },
- [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
- "protocol mismatch" },
- [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
- "data directon mismatch" },
- [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
- "ran out of SGEs while writing" },
- [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
- "ran out of SGEs while reading" },
- [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
- "invalid data directon for ATAPI CDB" },
- [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
- "SGT no on qword boundary" },
- [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
- "PCI target abort while fetching SGT" },
- [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
- "PCI master abort while fetching SGT" },
- [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
- "PCI parity error while fetching SGT" },
- [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
- "PRB not on qword boundary" },
- [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
- "PCI target abort while fetching PRB" },
- [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
- "PCI master abort while fetching PRB" },
- [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
- "PCI parity error while fetching PRB" },
- [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
- "undefined error while transferring data" },
- [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
- "PCI target abort while transferring data" },
- [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
- "PCI master abort while transferring data" },
- [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
- "PCI parity error while transferring data" },
- [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
- "FIS received while sending service FIS" },
-};
-
/*
* ap->private_data
*
static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
+static void sil24_phy_reset(struct ata_port *ap);
static void sil24_qc_prep(struct ata_queued_cmd *qc);
-static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
+static int sil24_qc_issue(struct ata_queued_cmd *qc);
static void sil24_irq_clear(struct ata_port *ap);
+static void sil24_eng_timeout(struct ata_port *ap);
static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
-static void sil24_freeze(struct ata_port *ap);
-static void sil24_thaw(struct ata_port *ap);
-static void sil24_error_handler(struct ata_port *ap);
-static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
static int sil24_port_start(struct ata_port *ap);
static void sil24_port_stop(struct ata_port *ap);
static void sil24_host_stop(struct ata_host_set *host_set);
static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
-static int sil24_pci_device_resume(struct pci_dev *pdev);
static const struct pci_device_id sil24_pci_tbl[] = {
{ 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
.id_table = sil24_pci_tbl,
.probe = sil24_init_one,
.remove = ata_pci_remove_one, /* safe? */
- .suspend = ata_pci_device_suspend,
- .resume = sil24_pci_device_resume,
};
static struct scsi_host_template sil24_sht = {
.name = DRV_NAME,
.ioctl = ata_scsi_ioctl,
.queuecommand = ata_scsi_queuecmd,
- .change_queue_depth = ata_scsi_change_queue_depth,
- .can_queue = SIL24_MAX_CMDS,
+ .eh_strategy_handler = ata_scsi_error,
+ .can_queue = ATA_DEF_QUEUE,
.this_id = ATA_SHT_THIS_ID,
.sg_tablesize = LIBATA_MAX_PRD,
+ .max_sectors = ATA_MAX_SECTORS,
.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
.emulated = ATA_SHT_EMULATED,
.use_clustering = ATA_SHT_USE_CLUSTERING,
.proc_name = DRV_NAME,
.dma_boundary = ATA_DMA_BOUNDARY,
.slave_configure = ata_scsi_slave_config,
- .slave_destroy = ata_scsi_slave_destroy,
.bios_param = ata_std_bios_param,
- .suspend = ata_scsi_device_suspend,
- .resume = ata_scsi_device_resume,
};
static const struct ata_port_operations sil24_ops = {
.tf_read = sil24_tf_read,
+ .phy_reset = sil24_phy_reset,
+
.qc_prep = sil24_qc_prep,
.qc_issue = sil24_qc_issue,
+ .eng_timeout = sil24_eng_timeout,
+
.irq_handler = sil24_interrupt,
.irq_clear = sil24_irq_clear,
.scr_read = sil24_scr_read,
.scr_write = sil24_scr_write,
- .freeze = sil24_freeze,
- .thaw = sil24_thaw,
- .error_handler = sil24_error_handler,
- .post_internal_cmd = sil24_post_internal_cmd,
-
.port_start = sil24_port_start,
.port_stop = sil24_port_stop,
.host_stop = sil24_host_stop,
/* sil_3124 */
{
.sht = &sil24_sht,
- .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
- SIL24_FLAG_PCIX_IRQ_WOC,
+ .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
+ ATA_FLAG_SRST | ATA_FLAG_MMIO |
+ ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(4),
.pio_mask = 0x1f, /* pio0-4 */
.mwdma_mask = 0x07, /* mwdma0-2 */
.udma_mask = 0x3f, /* udma0-5 */
.port_ops = &sil24_ops,
},
- /* sil_3132 */
+ /* sil_3132 */
{
.sht = &sil24_sht,
- .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
+ .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
+ ATA_FLAG_SRST | ATA_FLAG_MMIO |
+ ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(2),
.pio_mask = 0x1f, /* pio0-4 */
.mwdma_mask = 0x07, /* mwdma0-2 */
.udma_mask = 0x3f, /* udma0-5 */
/* sil_3131/sil_3531 */
{
.sht = &sil24_sht,
- .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
+ .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
+ ATA_FLAG_SRST | ATA_FLAG_MMIO |
+ ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(1),
.pio_mask = 0x1f, /* pio0-4 */
.mwdma_mask = 0x07, /* mwdma0-2 */
.udma_mask = 0x3f, /* udma0-5 */
},
};
-static int sil24_tag(int tag)
-{
- if (unlikely(ata_tag_internal(tag)))
- return 0;
- return tag;
-}
-
static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev)
{
void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
- if (dev->cdb_len == 16)
+ if (ap->cdb_len == 16)
writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
else
writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
*tf = pp->tf;
}
-static int sil24_init_port(struct ata_port *ap)
-{
- void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
- u32 tmp;
-
- writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
- ata_wait_register(port + PORT_CTRL_STAT,
- PORT_CS_INIT, PORT_CS_INIT, 10, 100);
- tmp = ata_wait_register(port + PORT_CTRL_STAT,
- PORT_CS_RDY, 0, 10, 100);
-
- if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
- return -EIO;
- return 0;
-}
-
-static int sil24_softreset(struct ata_port *ap, unsigned int *class)
+static int sil24_issue_SRST(struct ata_port *ap)
{
void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
struct sil24_port_priv *pp = ap->private_data;
struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
dma_addr_t paddr = pp->cmd_block_dma;
- u32 mask, irq_stat;
- const char *reason;
-
- DPRINTK("ENTER\n");
+ u32 irq_enable, irq_stat;
+ int cnt;
- if (ata_port_offline(ap)) {
- DPRINTK("PHY reports no device\n");
- *class = ATA_DEV_NONE;
- goto out;
- }
+ /* temporarily turn off IRQs during SRST */
+ irq_enable = readl(port + PORT_IRQ_ENABLE_SET);
+ writel(irq_enable, port + PORT_IRQ_ENABLE_CLR);
- /* put the port into known state */
- if (sil24_init_port(ap)) {
- reason ="port not ready";
- goto err;
- }
+ /*
+ * XXX: Not sure whether the following sleep is needed or not.
+ * The original driver had it. So....
+ */
+ msleep(10);
- /* do SRST */
- prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
+ prb->ctrl = PRB_CTRL_SRST;
prb->fis[1] = 0; /* no PM yet */
writel((u32)paddr, port + PORT_CMD_ACTIVATE);
- writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
- mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
- irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
- 100, ATA_TMOUT_BOOT / HZ * 1000);
+ for (cnt = 0; cnt < 100; cnt++) {
+ irq_stat = readl(port + PORT_IRQ_STAT);
+ writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
- writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
- irq_stat >>= PORT_IRQ_RAW_SHIFT;
+ irq_stat >>= PORT_IRQ_RAW_SHIFT;
+ if (irq_stat & (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR))
+ break;
- if (!(irq_stat & PORT_IRQ_COMPLETE)) {
- if (irq_stat & PORT_IRQ_ERROR)
- reason = "SRST command error";
- else
- reason = "timeout";
- goto err;
+ msleep(1);
}
- sil24_update_tf(ap);
- *class = ata_dev_classify(&pp->tf);
+ /* restore IRQs */
+ writel(irq_enable, port + PORT_IRQ_ENABLE_SET);
- if (*class == ATA_DEV_UNKNOWN)
- *class = ATA_DEV_NONE;
+ if (!(irq_stat & PORT_IRQ_COMPLETE))
+ return -1;
- out:
- DPRINTK("EXIT, class=%u\n", *class);
+ /* update TF */
+ sil24_update_tf(ap);
return 0;
-
- err:
- ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
- return -EIO;
}
-static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
+static void sil24_phy_reset(struct ata_port *ap)
{
- void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
- const char *reason;
- int tout_msec, rc;
- u32 tmp;
-
- /* sil24 does the right thing(tm) without any protection */
- sata_set_spd(ap);
-
- tout_msec = 100;
- if (ata_port_online(ap))
- tout_msec = 5000;
-
- writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
- tmp = ata_wait_register(port + PORT_CTRL_STAT,
- PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
+ struct sil24_port_priv *pp = ap->private_data;
- /* SStatus oscillates between zero and valid status after
- * DEV_RST, debounce it.
- */
- rc = sata_phy_debounce(ap, sata_deb_timing_long);
- if (rc) {
- reason = "PHY debouncing failed";
- goto err;
- }
+ __sata_phy_reset(ap);
+ if (ap->flags & ATA_FLAG_PORT_DISABLED)
+ return;
- if (tmp & PORT_CS_DEV_RST) {
- if (ata_port_offline(ap))
- return 0;
- reason = "link not ready";
- goto err;
+ if (sil24_issue_SRST(ap) < 0) {
+ printk(KERN_ERR DRV_NAME
+ " ata%u: SRST failed, disabling port\n", ap->id);
+ ap->ops->port_disable(ap);
+ return;
}
- /* Sil24 doesn't store signature FIS after hardreset, so we
- * can't wait for BSY to clear. Some devices take a long time
- * to get ready and those devices will choke if we don't wait
- * for BSY clearance here. Tell libata to perform follow-up
- * softreset.
- */
- return -EAGAIN;
-
- err:
- ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
- return -EIO;
+ ap->device->class = ata_dev_classify(&pp->tf);
}
static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
{
struct ata_port *ap = qc->ap;
struct sil24_port_priv *pp = ap->private_data;
- union sil24_cmd_block *cb;
+ union sil24_cmd_block *cb = pp->cmd_block + qc->tag;
struct sil24_prb *prb;
struct sil24_sge *sge;
- u16 ctrl = 0;
-
- cb = &pp->cmd_block[sil24_tag(qc->tag)];
switch (qc->tf.protocol) {
case ATA_PROT_PIO:
case ATA_PROT_DMA:
- case ATA_PROT_NCQ:
case ATA_PROT_NODATA:
prb = &cb->ata.prb;
sge = cb->ata.sge;
+ prb->ctrl = 0;
break;
case ATA_PROT_ATAPI:
prb = &cb->atapi.prb;
sge = cb->atapi.sge;
memset(cb->atapi.cdb, 0, 32);
- memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
+ memcpy(cb->atapi.cdb, qc->cdb, ap->cdb_len);
if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
if (qc->tf.flags & ATA_TFLAG_WRITE)
- ctrl = PRB_CTRL_PACKET_WRITE;
+ prb->ctrl = PRB_CTRL_PACKET_WRITE;
else
- ctrl = PRB_CTRL_PACKET_READ;
- }
+ prb->ctrl = PRB_CTRL_PACKET_READ;
+ } else
+ prb->ctrl = 0;
+
break;
default:
BUG();
}
- prb->ctrl = cpu_to_le16(ctrl);
ata_tf_to_fis(&qc->tf, prb->fis, 0);
if (qc->flags & ATA_QCFLAG_DMAMAP)
sil24_fill_sg(qc, sge);
}
-static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
+static int sil24_qc_issue(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
- struct sil24_port_priv *pp = ap->private_data;
void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
- unsigned int tag = sil24_tag(qc->tag);
- dma_addr_t paddr;
- void __iomem *activate;
-
- paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
- activate = port + PORT_CMD_ACTIVATE + tag * 8;
-
- writel((u32)paddr, activate);
- writel((u64)paddr >> 32, activate + 4);
+ struct sil24_port_priv *pp = ap->private_data;
+ dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
+ writel((u32)paddr, port + PORT_CMD_ACTIVATE);
return 0;
}
/* unused */
}
-static void sil24_freeze(struct ata_port *ap)
+static int __sil24_restart_controller(void __iomem *port)
{
- void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
+ u32 tmp;
+ int cnt;
- /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
- * PORT_IRQ_ENABLE instead.
- */
- writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
-}
+ writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
-static void sil24_thaw(struct ata_port *ap)
-{
- void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
- u32 tmp;
+ /* Max ~10ms */
+ for (cnt = 0; cnt < 10000; cnt++) {
+ tmp = readl(port + PORT_CTRL_STAT);
+ if (tmp & PORT_CS_RDY)
+ return 0;
+ udelay(1);
+ }
- /* clear IRQ */
- tmp = readl(port + PORT_IRQ_STAT);
- writel(tmp, port + PORT_IRQ_STAT);
+ return -1;
+}
- /* turn IRQ back on */
- writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
+static void sil24_restart_controller(struct ata_port *ap)
+{
+ if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr))
+ printk(KERN_ERR DRV_NAME
+ " ata%u: failed to restart controller\n", ap->id);
}
-static void sil24_error_intr(struct ata_port *ap)
+static int __sil24_reset_controller(void __iomem *port)
{
- void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
- struct ata_eh_info *ehi = &ap->eh_info;
- int freeze = 0;
- u32 irq_stat;
+ int cnt;
+ u32 tmp;
- /* on error, we need to clear IRQ explicitly */
- irq_stat = readl(port + PORT_IRQ_STAT);
- writel(irq_stat, port + PORT_IRQ_STAT);
+ /* Reset controller state. Is this correct? */
+ writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
+ readl(port + PORT_CTRL_STAT); /* sync */
- /* first, analyze and record host port events */
- ata_ehi_clear_desc(ehi);
+ /* Max ~100ms */
+ for (cnt = 0; cnt < 1000; cnt++) {
+ udelay(100);
+ tmp = readl(port + PORT_CTRL_STAT);
+ if (!(tmp & PORT_CS_DEV_RST))
+ break;
+ }
- ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
+ if (tmp & PORT_CS_DEV_RST)
+ return -1;
- if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
- ata_ehi_hotplugged(ehi);
- ata_ehi_push_desc(ehi, ", %s",
- irq_stat & PORT_IRQ_PHYRDY_CHG ?
- "PHY RDY changed" : "device exchanged");
- freeze = 1;
- }
+ if (tmp & PORT_CS_RDY)
+ return 0;
- if (irq_stat & PORT_IRQ_UNK_FIS) {
- ehi->err_mask |= AC_ERR_HSM;
- ehi->action |= ATA_EH_SOFTRESET;
- ata_ehi_push_desc(ehi , ", unknown FIS");
- freeze = 1;
- }
+ return __sil24_restart_controller(port);
+}
- /* deal with command error */
- if (irq_stat & PORT_IRQ_ERROR) {
- struct sil24_cerr_info *ci = NULL;
- unsigned int err_mask = 0, action = 0;
- struct ata_queued_cmd *qc;
- u32 cerr;
-
- /* analyze CMD_ERR */
- cerr = readl(port + PORT_CMD_ERR);
- if (cerr < ARRAY_SIZE(sil24_cerr_db))
- ci = &sil24_cerr_db[cerr];
-
- if (ci && ci->desc) {
- err_mask |= ci->err_mask;
- action |= ci->action;
- ata_ehi_push_desc(ehi, ", %s", ci->desc);
- } else {
- err_mask |= AC_ERR_OTHER;
- action |= ATA_EH_SOFTRESET;
- ata_ehi_push_desc(ehi, ", unknown command error %d",
- cerr);
- }
+static void sil24_reset_controller(struct ata_port *ap)
+{
+ printk(KERN_NOTICE DRV_NAME
+ " ata%u: resetting controller...\n", ap->id);
+ if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr))
+ printk(KERN_ERR DRV_NAME
+ " ata%u: failed to reset controller\n", ap->id);
+}
- /* record error info */
- qc = ata_qc_from_tag(ap, ap->active_tag);
- if (qc) {
- sil24_update_tf(ap);
- qc->err_mask |= err_mask;
- } else
- ehi->err_mask |= err_mask;
+static void sil24_eng_timeout(struct ata_port *ap)
+{
+ struct ata_queued_cmd *qc;
- ehi->action |= action;
+ qc = ata_qc_from_tag(ap, ap->active_tag);
+ if (!qc) {
+ printk(KERN_ERR "ata%u: BUG: timeout without command\n",
+ ap->id);
+ return;
}
- /* freeze or abort */
- if (freeze)
- ata_port_freeze(ap);
- else
- ata_port_abort(ap);
-}
+ /*
+ * hack alert! We cannot use the supplied completion
+ * function from inside the ->eh_strategy_handler() thread.
+ * libata is the only user of ->eh_strategy_handler() in
+ * any kernel, so the default scsi_done() assumes it is
+ * not being called from the SCSI EH.
+ */
+ printk(KERN_ERR "ata%u: command timeout\n", ap->id);
+ qc->scsidone = scsi_finish_command;
+ qc->err_mask |= AC_ERR_OTHER;
+ ata_qc_complete(qc);
-static void sil24_finish_qc(struct ata_queued_cmd *qc)
-{
- if (qc->flags & ATA_QCFLAG_RESULT_TF)
- sil24_update_tf(qc->ap);
+ sil24_reset_controller(ap);
}
-static inline void sil24_host_intr(struct ata_port *ap)
+static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
{
+ struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
+ struct sil24_port_priv *pp = ap->private_data;
void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
- u32 slot_stat, qc_active;
- int rc;
+ u32 irq_stat, cmd_err, sstatus, serror;
+ unsigned int err_mask;
- slot_stat = readl(port + PORT_SLOT_STAT);
+ irq_stat = readl(port + PORT_IRQ_STAT);
+ writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
- if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
- sil24_error_intr(ap);
+ if (!(irq_stat & PORT_IRQ_ERROR)) {
+ /* ignore non-completion, non-error irqs for now */
+ printk(KERN_WARNING DRV_NAME
+ "ata%u: non-error exception irq (irq_stat %x)\n",
+ ap->id, irq_stat);
return;
}
- if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
- writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
+ cmd_err = readl(port + PORT_CMD_ERR);
+ sstatus = readl(port + PORT_SSTATUS);
+ serror = readl(port + PORT_SERROR);
+ if (serror)
+ writel(serror, port + PORT_SERROR);
- qc_active = slot_stat & ~HOST_SSTAT_ATTN;
- rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
- if (rc > 0)
- return;
- if (rc < 0) {
- struct ata_eh_info *ehi = &ap->eh_info;
- ehi->err_mask |= AC_ERR_HSM;
- ehi->action |= ATA_EH_SOFTRESET;
- ata_port_freeze(ap);
- return;
+ /*
+ * Don't log ATAPI device errors. They're supposed to happen
+ * and any serious errors will be logged using sense data by
+ * the SCSI layer.
+ */
+ if (ap->device[0].class != ATA_DEV_ATAPI || cmd_err > PORT_CERR_SDB)
+ printk("ata%u: error interrupt on port%d\n"
+ " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
+ ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
+
+ if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
+ /*
+ * Device is reporting error, tf registers are valid.
+ */
+ sil24_update_tf(ap);
+ err_mask = ac_err_mask(pp->tf.command);
+ sil24_restart_controller(ap);
+ } else {
+ /*
+ * Other errors. libata currently doesn't have any
+ * mechanism to report these errors. Just turn on
+ * ATA_ERR.
+ */
+ err_mask = AC_ERR_OTHER;
+ sil24_reset_controller(ap);
+ }
+
+ if (qc) {
+ qc->err_mask |= err_mask;
+ ata_qc_complete(qc);
}
+}
+
+static inline void sil24_host_intr(struct ata_port *ap)
+{
+ struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
+ void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
+ u32 slot_stat;
+
+ slot_stat = readl(port + PORT_SLOT_STAT);
+ if (!(slot_stat & HOST_SSTAT_ATTN)) {
+ struct sil24_port_priv *pp = ap->private_data;
+ /*
+ * !HOST_SSAT_ATTN guarantees successful completion,
+ * so reading back tf registers is unnecessary for
+ * most commands. TODO: read tf registers for
+ * commands which require these values on successful
+ * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
+ * DEVICE RESET and READ PORT MULTIPLIER (any more?).
+ */
+ sil24_update_tf(ap);
- if (ata_ratelimit())
- ata_port_printk(ap, KERN_INFO, "spurious interrupt "
- "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
- slot_stat, ap->active_tag, ap->sactive);
+ if (qc) {
+ qc->err_mask |= ac_err_mask(pp->tf.command);
+ ata_qc_complete(qc);
+ }
+ } else
+ sil24_error_intr(ap, slot_stat);
}
static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
for (i = 0; i < host_set->n_ports; i++)
if (status & (1 << i)) {
struct ata_port *ap = host_set->ports[i];
- if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
+ if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED)) {
sil24_host_intr(host_set->ports[i]);
handled++;
} else
return IRQ_RETVAL(handled);
}
-static void sil24_error_handler(struct ata_port *ap)
-{
- struct ata_eh_context *ehc = &ap->eh_context;
-
- if (sil24_init_port(ap)) {
- ata_eh_freeze_port(ap);
- ehc->i.action |= ATA_EH_HARDRESET;
- }
-
- /* perform recovery */
- ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
- ata_std_postreset);
-}
-
-static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
-
- if (qc->flags & ATA_QCFLAG_FAILED)
- qc->err_mask |= AC_ERR_OTHER;
-
- /* make DMA engine forget about the failed command */
- if (qc->err_mask)
- sil24_init_port(ap);
-}
-
static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
{
- const size_t cb_size = sizeof(*pp->cmd_block) * SIL24_MAX_CMDS;
+ const size_t cb_size = sizeof(*pp->cmd_block);
dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
}
struct device *dev = ap->host_set->dev;
struct sil24_port_priv *pp;
union sil24_cmd_block *cb;
- size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
+ size_t cb_size = sizeof(*cb);
dma_addr_t cb_dma;
int rc = -ENOMEM;
static void sil24_host_stop(struct ata_host_set *host_set)
{
struct sil24_host_priv *hpriv = host_set->private_data;
- struct pci_dev *pdev = to_pci_dev(host_set->dev);
- pci_iounmap(pdev, hpriv->host_base);
- pci_iounmap(pdev, hpriv->port_base);
+ iounmap(hpriv->host_base);
+ iounmap(hpriv->port_base);
kfree(hpriv);
}
-static void sil24_init_controller(struct pci_dev *pdev, int n_ports,
- unsigned long host_flags,
- void __iomem *host_base,
- void __iomem *port_base)
-{
- u32 tmp;
- int i;
-
- /* GPIO off */
- writel(0, host_base + HOST_FLASH_CMD);
-
- /* clear global reset & mask interrupts during initialization */
- writel(0, host_base + HOST_CTRL);
-
- /* init ports */
- for (i = 0; i < n_ports; i++) {
- void __iomem *port = port_base + i * PORT_REGS_SIZE;
-
- /* Initial PHY setting */
- writel(0x20c, port + PORT_PHY_CFG);
-
- /* Clear port RST */
- tmp = readl(port + PORT_CTRL_STAT);
- if (tmp & PORT_CS_PORT_RST) {
- writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
- tmp = ata_wait_register(port + PORT_CTRL_STAT,
- PORT_CS_PORT_RST,
- PORT_CS_PORT_RST, 10, 100);
- if (tmp & PORT_CS_PORT_RST)
- dev_printk(KERN_ERR, &pdev->dev,
- "failed to clear port RST\n");
- }
-
- /* Configure IRQ WoC */
- if (host_flags & SIL24_FLAG_PCIX_IRQ_WOC)
- writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
- else
- writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
-
- /* Zero error counters. */
- writel(0x8000, port + PORT_DECODE_ERR_THRESH);
- writel(0x8000, port + PORT_CRC_ERR_THRESH);
- writel(0x8000, port + PORT_HSHK_ERR_THRESH);
- writel(0x0000, port + PORT_DECODE_ERR_CNT);
- writel(0x0000, port + PORT_CRC_ERR_CNT);
- writel(0x0000, port + PORT_HSHK_ERR_CNT);
-
- /* Always use 64bit activation */
- writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
-
- /* Clear port multiplier enable and resume bits */
- writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
- }
-
- /* Turn on interrupts */
- writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
-}
-
static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
static int printed_version = 0;
void __iomem *host_base = NULL;
void __iomem *port_base = NULL;
int i, rc;
- u32 tmp;
if (!printed_version++)
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
goto out_disable;
rc = -ENOMEM;
- /* map mmio registers */
- host_base = pci_iomap(pdev, 0, 0);
+ /* ioremap mmio registers */
+ host_base = ioremap(pci_resource_start(pdev, 0),
+ pci_resource_len(pdev, 0));
if (!host_base)
goto out_free;
- port_base = pci_iomap(pdev, 2, 0);
+ port_base = ioremap(pci_resource_start(pdev, 2),
+ pci_resource_len(pdev, 2));
if (!port_base)
goto out_free;
/* allocate & init probe_ent and hpriv */
- probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
+ probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
if (!probe_ent)
goto out_free;
- hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
+ hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
if (!hpriv)
goto out_free;
+ memset(probe_ent, 0, sizeof(*probe_ent));
probe_ent->dev = pci_dev_to_dev(pdev);
INIT_LIST_HEAD(&probe_ent->node);
probe_ent->sht = pinfo->sht;
probe_ent->host_flags = pinfo->host_flags;
probe_ent->pio_mask = pinfo->pio_mask;
- probe_ent->mwdma_mask = pinfo->mwdma_mask;
probe_ent->udma_mask = pinfo->udma_mask;
probe_ent->port_ops = pinfo->port_ops;
probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
probe_ent->irq = pdev->irq;
- probe_ent->irq_flags = IRQF_SHARED;
+ probe_ent->irq_flags = SA_SHIRQ;
+ probe_ent->mmio_base = port_base;
probe_ent->private_data = hpriv;
+ memset(hpriv, 0, sizeof(*hpriv));
hpriv->host_base = host_base;
hpriv->port_base = port_base;
/*
* Configure the device
*/
- if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
- rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
- if (rc) {
- rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
- if (rc) {
- dev_printk(KERN_ERR, &pdev->dev,
- "64-bit DMA enable failed\n");
- goto out_free;
- }
- }
- } else {
- rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
- if (rc) {
- dev_printk(KERN_ERR, &pdev->dev,
- "32-bit DMA enable failed\n");
- goto out_free;
- }
- rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
- if (rc) {
- dev_printk(KERN_ERR, &pdev->dev,
- "32-bit consistent DMA enable failed\n");
- goto out_free;
- }
+ /*
+ * FIXME: This device is certainly 64-bit capable. We just
+ * don't know how to use it. After fixing 32bit activation in
+ * this function, enable 64bit masks here.
+ */
+ rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
+ if (rc) {
+ dev_printk(KERN_ERR, &pdev->dev,
+ "32-bit DMA enable failed\n");
+ goto out_free;
}
-
- /* Apply workaround for completion IRQ loss on PCI-X errata */
- if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
- tmp = readl(host_base + HOST_CTRL);
- if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
- dev_printk(KERN_INFO, &pdev->dev,
- "Applying completion IRQ loss on PCI-X "
- "errata fix\n");
- else
- probe_ent->host_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
+ rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
+ if (rc) {
+ dev_printk(KERN_ERR, &pdev->dev,
+ "32-bit consistent DMA enable failed\n");
+ goto out_free;
}
+ /* GPIO off */
+ writel(0, host_base + HOST_FLASH_CMD);
+
+ /* Mask interrupts during initialization */
+ writel(0, host_base + HOST_CTRL);
+
for (i = 0; i < probe_ent->n_ports; i++) {
- unsigned long portu =
- (unsigned long)port_base + i * PORT_REGS_SIZE;
+ void __iomem *port = port_base + i * PORT_REGS_SIZE;
+ unsigned long portu = (unsigned long)port;
+ u32 tmp;
+ int cnt;
- probe_ent->port[i].cmd_addr = portu;
+ probe_ent->port[i].cmd_addr = portu + PORT_PRB;
probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
ata_std_ports(&probe_ent->port[i]);
+
+ /* Initial PHY setting */
+ writel(0x20c, port + PORT_PHY_CFG);
+
+ /* Clear port RST */
+ tmp = readl(port + PORT_CTRL_STAT);
+ if (tmp & PORT_CS_PORT_RST) {
+ writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
+ readl(port + PORT_CTRL_STAT); /* sync */
+ for (cnt = 0; cnt < 10; cnt++) {
+ msleep(10);
+ tmp = readl(port + PORT_CTRL_STAT);
+ if (!(tmp & PORT_CS_PORT_RST))
+ break;
+ }
+ if (tmp & PORT_CS_PORT_RST)
+ dev_printk(KERN_ERR, &pdev->dev,
+ "failed to clear port RST\n");
+ }
+
+ /* Zero error counters. */
+ writel(0x8000, port + PORT_DECODE_ERR_THRESH);
+ writel(0x8000, port + PORT_CRC_ERR_THRESH);
+ writel(0x8000, port + PORT_HSHK_ERR_THRESH);
+ writel(0x0000, port + PORT_DECODE_ERR_CNT);
+ writel(0x0000, port + PORT_CRC_ERR_CNT);
+ writel(0x0000, port + PORT_HSHK_ERR_CNT);
+
+ /* FIXME: 32bit activation? */
+ writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
+ writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
+
+ /* Configure interrupts */
+ writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
+ writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS,
+ port + PORT_IRQ_ENABLE_SET);
+
+ /* Clear interrupts */
+ writel(0x0fff0fff, port + PORT_IRQ_STAT);
+ writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
+
+ /* Clear port multiplier enable and resume bits */
+ writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
+
+ /* Reset itself */
+ if (__sil24_reset_controller(port))
+ dev_printk(KERN_ERR, &pdev->dev,
+ "failed to reset controller\n");
}
- sil24_init_controller(pdev, probe_ent->n_ports, probe_ent->host_flags,
- host_base, port_base);
+ /* Turn on interrupts */
+ writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
pci_set_master(pdev);
out_free:
if (host_base)
- pci_iounmap(pdev, host_base);
+ iounmap(host_base);
if (port_base)
- pci_iounmap(pdev, port_base);
+ iounmap(port_base);
kfree(probe_ent);
kfree(hpriv);
pci_release_regions(pdev);
return rc;
}
-static int sil24_pci_device_resume(struct pci_dev *pdev)
-{
- struct ata_host_set *host_set = dev_get_drvdata(&pdev->dev);
- struct sil24_host_priv *hpriv = host_set->private_data;
-
- ata_pci_device_do_resume(pdev);
-
- if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
- writel(HOST_CTRL_GLOBAL_RST, hpriv->host_base + HOST_CTRL);
-
- sil24_init_controller(pdev, host_set->n_ports,
- host_set->ports[0]->flags,
- hpriv->host_base, hpriv->port_base);
-
- ata_host_set_resume(host_set);
-
- return 0;
-}
-
static int __init sil24_init(void)
{
return pci_module_init(&sil24_pci_driver);
git://git.onelab.eu / linux-2.6.git / blobdiff