#ifndef SYM53C8XX_DEFS_H
#define SYM53C8XX_DEFS_H
-/*
-** Check supported Linux versions
-*/
-
#include <linux/config.h>
-/*
- * NCR PQS/PDS special device support.
- */
-#ifdef CONFIG_SCSI_NCR53C8XX_PQS_PDS
-#define SCSI_NCR_PQS_PDS_SUPPORT
-#endif
-
-/*
- * No more an option, enabled by default.
- */
-#ifndef CONFIG_SCSI_NCR53C8XX_NO_NVRAM
-# ifndef CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
-# define CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
-# endif
-#endif
-
-/*
-** These options are not tunable from 'make config'
-*/
+/* These options are not tunable from 'make config' */
#define SCSI_NCR_PROC_INFO_SUPPORT
/*
*/
#define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
#define SCSI_NCR_DEBUG_INFO_SUPPORT
-#define SCSI_NCR_PCI_FIX_UP_SUPPORT
#ifdef SCSI_NCR_PROC_INFO_SUPPORT
# define SCSI_NCR_USER_COMMAND_SUPPORT
# define SCSI_NCR_USER_INFO_SUPPORT
# define SCSI_NCR_ENABLE_INTEGRITY_CHECK
#endif
-/*==========================================================
-**
-** nvram settings - #define SCSI_NCR_NVRAM_SUPPORT to enable
-**
-**==========================================================
-*/
-
-#ifdef CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
-#define SCSI_NCR_NVRAM_SUPPORT
-/* #define SCSI_NCR_DEBUG_NVRAM */
-#endif
-
/* ---------------------------------------------------------------------
** Take into account kernel configured parameters.
** Most of these options can be overridden at startup by a command line.
#define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
#endif
-/*
- * Use normal IO if configured. Forced for alpha.
- */
-#if defined(CONFIG_SCSI_NCR53C8XX_IOMAPPED)
-#define SCSI_NCR_IOMAPPED
-#elif defined(__alpha__)
-#define SCSI_NCR_IOMAPPED
-#endif
-
/*
* Immediate arbitration
*/
#define SCSI_NCR_MAX_LUN (1)
#endif
-#ifndef HOSTS_C
-
/*
** These simple macros limit expression involving
** kernel time values (jiffies) to some that have
#define outw_raw outw
#define outl_raw outl
-#if defined(__i386__) /* i386 implements full FLAT memory/MMIO model */
-#define readb_raw(a) (*(volatile unsigned char *) (a))
-#define readw_raw(a) (*(volatile unsigned short *) (a))
-#define readl_raw(a) (*(volatile unsigned int *) (a))
-#define writeb_raw(b,a) ((*(volatile unsigned char *) (a)) = (b))
-#define writew_raw(b,a) ((*(volatile unsigned short *) (a)) = (b))
-#define writel_raw(b,a) ((*(volatile unsigned int *) (a)) = (b))
-
-#else /* Other little-endian */
#define readb_raw readb
#define readw_raw readw
#define readl_raw readl
#define writew_raw writew
#define writel_raw writel
-#endif
#endif
#if !defined(__hppa__) && !defined(__mips__)
#endif
#endif
-
-/*
- * IA32 architecture does not reorder STORES and prevents
- * LOADS from passing STORES. It is called `program order'
- * by Intel and allows device drivers to deal with memory
- * ordering by only ensuring that the code is not reordered
- * by the compiler when ordering is required.
- * Other architectures implement a weaker ordering that
- * requires memory barriers (and also IO barriers when they
- * make sense) to be used.
- */
-
#define MEMORY_BARRIER() mb()
/*
* Access to the controller chip.
*
- * If SCSI_NCR_IOMAPPED is defined, the driver will use
- * normal IOs instead of the MEMORY MAPPED IO method
- * recommended by PCI specifications.
- * If all PCI bridges, host brigdes and architectures
- * would have been correctly designed for PCI, this
- * option would be useless.
- *
* If the CPU and the NCR use same endian-ness addressing,
* no byte reordering is needed for accessing chip io
* registers. Functions suffixed by '_raw' are assumed
* blah, ...
*/
-#if defined(SCSI_NCR_IOMAPPED)
-/*
- * IO mapped only input / ouput
- */
-
-#define INB_OFF(o) inb (np->base_io + ncr_offb(o))
-#define OUTB_OFF(o, val) outb ((val), np->base_io + ncr_offb(o))
-
-#if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
-
-#define INW_OFF(o) inw_l2b (np->base_io + ncr_offw(o))
-#define INL_OFF(o) inl_l2b (np->base_io + (o))
-
-#define OUTW_OFF(o, val) outw_b2l ((val), np->base_io + ncr_offw(o))
-#define OUTL_OFF(o, val) outl_b2l ((val), np->base_io + (o))
-
-#elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
-
-#define INW_OFF(o) inw_b2l (np->base_io + ncr_offw(o))
-#define INL_OFF(o) inl_b2l (np->base_io + (o))
-
-#define OUTW_OFF(o, val) outw_l2b ((val), np->base_io + ncr_offw(o))
-#define OUTL_OFF(o, val) outl_l2b ((val), np->base_io + (o))
-
-#else
-
-#define INW_OFF(o) inw_raw (np->base_io + ncr_offw(o))
-#define INL_OFF(o) inl_raw (np->base_io + (o))
-
-#define OUTW_OFF(o, val) outw_raw ((val), np->base_io + ncr_offw(o))
-#define OUTL_OFF(o, val) outl_raw ((val), np->base_io + (o))
-
-#endif /* ENDIANs */
-
-#else /* defined SCSI_NCR_IOMAPPED */
-
/*
* MEMORY mapped IO input / output
*/
#endif
-#endif /* defined SCSI_NCR_IOMAPPED */
-
#define INB(r) INB_OFF (offsetof(struct ncr_reg,r))
#define INW(r) INW_OFF (offsetof(struct ncr_reg,r))
#define INL(r) INL_OFF (offsetof(struct ncr_reg,r))
} while (0)
-/*
-** NCR53C8XX Device Ids
-*/
-
-#ifndef PSEUDO_720_ID
-#define PSEUDO_720_ID 0x5a00
-#endif
-
-#ifndef PCI_DEVICE_ID_NCR_53C810
-#define PCI_DEVICE_ID_NCR_53C810 1
-#endif
-
-#ifndef PCI_DEVICE_ID_NCR_53C810AP
-#define PCI_DEVICE_ID_NCR_53C810AP 5
-#endif
-
-#ifndef PCI_DEVICE_ID_NCR_53C815
-#define PCI_DEVICE_ID_NCR_53C815 4
-#endif
-
-#ifndef PCI_DEVICE_ID_NCR_53C820
-#define PCI_DEVICE_ID_NCR_53C820 2
-#endif
-
-#ifndef PCI_DEVICE_ID_NCR_53C825
-#define PCI_DEVICE_ID_NCR_53C825 3
-#endif
-
-#ifndef PCI_DEVICE_ID_NCR_53C860
-#define PCI_DEVICE_ID_NCR_53C860 6
-#endif
-
-#ifndef PCI_DEVICE_ID_NCR_53C875
-#define PCI_DEVICE_ID_NCR_53C875 0xf
-#endif
-
-#ifndef PCI_DEVICE_ID_NCR_53C875J
-#define PCI_DEVICE_ID_NCR_53C875J 0x8f
-#endif
-
-#ifndef PCI_DEVICE_ID_NCR_53C885
-#define PCI_DEVICE_ID_NCR_53C885 0xd
-#endif
-
-#ifndef PCI_DEVICE_ID_NCR_53C895
-#define PCI_DEVICE_ID_NCR_53C895 0xc
-#endif
-
-#ifndef PCI_DEVICE_ID_NCR_53C896
-#define PCI_DEVICE_ID_NCR_53C896 0xb
-#endif
-
-#ifndef PCI_DEVICE_ID_NCR_53C895A
-#define PCI_DEVICE_ID_NCR_53C895A 0x12
-#endif
-
-#ifndef PCI_DEVICE_ID_NCR_53C875A
-#define PCI_DEVICE_ID_NCR_53C875A 0x13
-#endif
-
-#ifndef PCI_DEVICE_ID_NCR_53C1510D
-#define PCI_DEVICE_ID_NCR_53C1510D 0xa
-#endif
-
-#ifndef PCI_DEVICE_ID_LSI_53C1010
-#define PCI_DEVICE_ID_LSI_53C1010 0x20
-#endif
-
-#ifndef PCI_DEVICE_ID_LSI_53C1010_66
-#define PCI_DEVICE_ID_LSI_53C1010_66 0x21
-#endif
-
-
/*
** NCR53C8XX devices features table.
*/
-typedef struct {
- unsigned short device_id;
+struct ncr_chip {
unsigned short revision_id;
- char *name;
unsigned char burst_max; /* log-base-2 of max burst */
unsigned char offset_max;
unsigned char nr_divisor;
#define FE_LED0 (1<<0)
#define FE_WIDE (1<<1) /* Wide data transfers */
#define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
-#define FE_ULTRA2 (1<<3) /* Ultra 2 - 40 Mtrans/sec */
#define FE_DBLR (1<<4) /* Clock doubler present */
#define FE_QUAD (1<<5) /* Clock quadrupler present */
#define FE_ERL (1<<6) /* Enable read line */
#define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
#define FE_LEDC (1<<20) /* Hardware control of LED */
#define FE_DIFF (1<<21) /* Support Differential SCSI */
-#define FE_ULTRA3 (1<<22) /* Ultra-3 80Mtrans/sec */
#define FE_66MHZ (1<<23) /* 66MHz PCI Support */
#define FE_DAC (1<<24) /* Support DAC cycles (64 bit addressing) */
#define FE_ISTAT1 (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */
#define FE_EA (1<<29) /* 720: Enable Ack */
#define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
-#define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_ULTRA2|FE_DBLR|FE_QUAD|F_CLK80)
+#define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_DBLR|FE_QUAD|F_CLK80)
#define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
-} ncr_chip;
-
-/*
-** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 3.
-** Memory Read transaction terminated by a retry followed by
-** Memory Read Line command.
-*/
-#define FE_CACHE0_SET (FE_CACHE_SET & ~FE_ERL)
-
-/*
-** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 5.
-** On paper, this errata is harmless. But it is a good reason for
-** using a shorter programmed burst length (64 DWORDS instead of 128).
-*/
+};
-#define SCSI_NCR_CHIP_TABLE \
-{ \
- {PSEUDO_720_ID, 0x0f, "720", 3, 8, 4, \
- FE_WIDE|FE_DIFF|FE_EHP|FE_MUX|FE_EA} \
- , \
- {PCI_DEVICE_ID_NCR_53C810, 0x0f, "810", 4, 8, 4, \
- FE_ERL} \
- , \
- {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, \
- FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF} \
- , \
- {PCI_DEVICE_ID_NCR_53C815, 0xff, "815", 4, 8, 4, \
- FE_ERL|FE_BOF} \
- , \
- {PCI_DEVICE_ID_NCR_53C820, 0xff, "820", 4, 8, 4, \
- FE_WIDE|FE_ERL} \
- , \
- {PCI_DEVICE_ID_NCR_53C825, 0x0f, "825", 4, 8, 4, \
- FE_WIDE|FE_ERL|FE_BOF|FE_DIFF} \
- , \
- {PCI_DEVICE_ID_NCR_53C825, 0xff, "825a", 6, 8, 4, \
- FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF} \
- , \
- {PCI_DEVICE_ID_NCR_53C860, 0xff, "860", 4, 8, 5, \
- FE_ULTRA|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN} \
- , \
- {PCI_DEVICE_ID_NCR_53C875, 0x01, "875", 6, 16, 5, \
- FE_WIDE|FE_ULTRA|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
- FE_RAM|FE_DIFF|FE_VARCLK} \
- , \
- {PCI_DEVICE_ID_NCR_53C875, 0xff, "875", 6, 16, 5, \
- FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
- FE_RAM|FE_DIFF|FE_VARCLK} \
- , \
- {PCI_DEVICE_ID_NCR_53C875J,0xff, "875J", 6, 16, 5, \
- FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
- FE_RAM|FE_VARCLK} \
- , \
- {PCI_DEVICE_ID_NCR_53C885, 0xff, "885", 6, 16, 5, \
- FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
- FE_RAM|FE_DIFF|FE_VARCLK} \
- , \
- {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, \
- FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
- FE_RAM} \
- , \
- {PCI_DEVICE_ID_NCR_53C896, 0xff, "896", 6, 31, 7, \
- FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
- FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_ISTAT1} \
- , \
- {PCI_DEVICE_ID_NCR_53C895A, 0xff, "895a", 6, 31, 7, \
- FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
- FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC} \
- , \
- {PCI_DEVICE_ID_NCR_53C875A, 0xff, "875a", 6, 31, 7, \
- FE_WIDE|FE_ULTRA|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
- FE_RAM|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC} \
- , \
- {PCI_DEVICE_ID_NCR_53C1510D, 0xff, "1510D", 7, 31, 7, \
- FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
- FE_RAM|FE_IO256} \
- , \
- {PCI_DEVICE_ID_LSI_53C1010, 0xff, "1010-33", 6, 62, 7, \
- FE_WIDE|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_ISTAT1| \
- FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_ULTRA3} \
- , \
- {PCI_DEVICE_ID_LSI_53C1010_66, 0xff, "1010-66", 6, 62, 7, \
- FE_WIDE|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_ISTAT1| \
- FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_ULTRA3| \
- FE_66MHZ} \
-}
-
-/*
- * List of supported NCR chip ids
- */
-#define SCSI_NCR_CHIP_IDS \
-{ \
- PSEUDO_720_ID, \
- PCI_DEVICE_ID_NCR_53C810, \
- PCI_DEVICE_ID_NCR_53C815, \
- PCI_DEVICE_ID_NCR_53C820, \
- PCI_DEVICE_ID_NCR_53C825, \
- PCI_DEVICE_ID_NCR_53C860, \
- PCI_DEVICE_ID_NCR_53C875, \
- PCI_DEVICE_ID_NCR_53C875J, \
- PCI_DEVICE_ID_NCR_53C885, \
- PCI_DEVICE_ID_NCR_53C895, \
- PCI_DEVICE_ID_NCR_53C896, \
- PCI_DEVICE_ID_NCR_53C895A, \
- PCI_DEVICE_ID_NCR_53C1510D, \
- PCI_DEVICE_ID_LSI_53C1010, \
- PCI_DEVICE_ID_LSI_53C1010_66 \
-}
/*
** Driver setup structure.
*/
#define SCSI_NCR_MAX_EXCLUDES 8
struct ncr_driver_setup {
- u_char master_parity;
- u_char scsi_parity;
- u_char disconnection;
- u_char special_features;
- u_char force_sync_nego;
- u_char reverse_probe;
- u_char pci_fix_up;
- u_char use_nvram;
- u_char verbose;
- u_char default_tags;
- u_short default_sync;
- u_short debug;
- u_char burst_max;
- u_char led_pin;
- u_char max_wide;
- u_char settle_delay;
- u_char diff_support;
- u_char irqm;
- u_char bus_check;
- u_char optimize;
- u_char recovery;
- u_char host_id;
- u_short iarb;
- u_long excludes[SCSI_NCR_MAX_EXCLUDES];
+ u8 master_parity;
+ u8 scsi_parity;
+ u8 disconnection;
+ u8 special_features;
+ u8 force_sync_nego;
+ u8 reverse_probe;
+ u8 pci_fix_up;
+ u8 use_nvram;
+ u8 verbose;
+ u8 default_tags;
+ u16 default_sync;
+ u16 debug;
+ u8 burst_max;
+ u8 led_pin;
+ u8 max_wide;
+ u8 settle_delay;
+ u8 diff_support;
+ u8 irqm;
+ u8 bus_check;
+ u8 optimize;
+ u8 recovery;
+ u8 host_id;
+ u16 iarb;
+ u32 excludes[SCSI_NCR_MAX_EXCLUDES];
char tag_ctrl[100];
};
255 \
}
-#ifdef SCSI_NCR_NVRAM_SUPPORT
-/*
-** Symbios NvRAM data format
-*/
-#define SYMBIOS_NVRAM_SIZE 368
-#define SYMBIOS_NVRAM_ADDRESS 0x100
-
-struct Symbios_nvram {
-/* Header 6 bytes */
- u_short type; /* 0x0000 */
- u_short byte_count; /* excluding header/trailer */
- u_short checksum;
-
-/* Controller set up 20 bytes */
- u_char v_major; /* 0x00 */
- u_char v_minor; /* 0x30 */
- u32 boot_crc;
- u_short flags;
-#define SYMBIOS_SCAM_ENABLE (1)
-#define SYMBIOS_PARITY_ENABLE (1<<1)
-#define SYMBIOS_VERBOSE_MSGS (1<<2)
-#define SYMBIOS_CHS_MAPPING (1<<3)
-#define SYMBIOS_NO_NVRAM (1<<3) /* ??? */
- u_short flags1;
-#define SYMBIOS_SCAN_HI_LO (1)
- u_short term_state;
-#define SYMBIOS_TERM_CANT_PROGRAM (0)
-#define SYMBIOS_TERM_ENABLED (1)
-#define SYMBIOS_TERM_DISABLED (2)
- u_short rmvbl_flags;
-#define SYMBIOS_RMVBL_NO_SUPPORT (0)
-#define SYMBIOS_RMVBL_BOOT_DEVICE (1)
-#define SYMBIOS_RMVBL_MEDIA_INSTALLED (2)
- u_char host_id;
- u_char num_hba; /* 0x04 */
- u_char num_devices; /* 0x10 */
- u_char max_scam_devices; /* 0x04 */
- u_char num_valid_scam_devives; /* 0x00 */
- u_char rsvd;
-
-/* Boot order 14 bytes * 4 */
- struct Symbios_host{
- u_short type; /* 4:8xx / 0:nok */
- u_short device_id; /* PCI device id */
- u_short vendor_id; /* PCI vendor id */
- u_char bus_nr; /* PCI bus number */
- u_char device_fn; /* PCI device/function number << 3*/
- u_short word8;
- u_short flags;
-#define SYMBIOS_INIT_SCAN_AT_BOOT (1)
- u_short io_port; /* PCI io_port address */
- } host[4];
-
-/* Targets 8 bytes * 16 */
- struct Symbios_target {
- u_char flags;
-#define SYMBIOS_DISCONNECT_ENABLE (1)
-#define SYMBIOS_SCAN_AT_BOOT_TIME (1<<1)
-#define SYMBIOS_SCAN_LUNS (1<<2)
-#define SYMBIOS_QUEUE_TAGS_ENABLED (1<<3)
- u_char rsvd;
- u_char bus_width; /* 0x08/0x10 */
- u_char sync_offset;
- u_short sync_period; /* 4*period factor */
- u_short timeout;
- } target[16];
-/* Scam table 8 bytes * 4 */
- struct Symbios_scam {
- u_short id;
- u_short method;
-#define SYMBIOS_SCAM_DEFAULT_METHOD (0)
-#define SYMBIOS_SCAM_DONT_ASSIGN (1)
-#define SYMBIOS_SCAM_SET_SPECIFIC_ID (2)
-#define SYMBIOS_SCAM_USE_ORDER_GIVEN (3)
- u_short status;
-#define SYMBIOS_SCAM_UNKNOWN (0)
-#define SYMBIOS_SCAM_DEVICE_NOT_FOUND (1)
-#define SYMBIOS_SCAM_ID_NOT_SET (2)
-#define SYMBIOS_SCAM_ID_VALID (3)
- u_char target_id;
- u_char rsvd;
- } scam[4];
-
- u_char spare_devices[15*8];
- u_char trailer[6]; /* 0xfe 0xfe 0x00 0x00 0x00 0x00 */
-};
-typedef struct Symbios_nvram Symbios_nvram;
-typedef struct Symbios_host Symbios_host;
-typedef struct Symbios_target Symbios_target;
-typedef struct Symbios_scam Symbios_scam;
-
-/*
-** Tekram NvRAM data format.
-*/
-#define TEKRAM_NVRAM_SIZE 64
-#define TEKRAM_93C46_NVRAM_ADDRESS 0
-#define TEKRAM_24C16_NVRAM_ADDRESS 0x40
-
-struct Tekram_nvram {
- struct Tekram_target {
- u_char flags;
-#define TEKRAM_PARITY_CHECK (1)
-#define TEKRAM_SYNC_NEGO (1<<1)
-#define TEKRAM_DISCONNECT_ENABLE (1<<2)
-#define TEKRAM_START_CMD (1<<3)
-#define TEKRAM_TAGGED_COMMANDS (1<<4)
-#define TEKRAM_WIDE_NEGO (1<<5)
- u_char sync_index;
- u_short word2;
- } target[16];
- u_char host_id;
- u_char flags;
-#define TEKRAM_MORE_THAN_2_DRIVES (1)
-#define TEKRAM_DRIVES_SUP_1GB (1<<1)
-#define TEKRAM_RESET_ON_POWER_ON (1<<2)
-#define TEKRAM_ACTIVE_NEGATION (1<<3)
-#define TEKRAM_IMMEDIATE_SEEK (1<<4)
-#define TEKRAM_SCAN_LUNS (1<<5)
-#define TEKRAM_REMOVABLE_FLAGS (3<<6) /* 0: disable; 1: boot device; 2:all */
- u_char boot_delay_index;
- u_char max_tags_index;
- u_short flags1;
-#define TEKRAM_F2_F6_ENABLED (1)
- u_short spare[29];
-};
-typedef struct Tekram_nvram Tekram_nvram;
-typedef struct Tekram_target Tekram_target;
-
-#endif /* SCSI_NCR_NVRAM_SUPPORT */
-
/**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
/*-----------------------------------------------------------------
*/
struct ncr_reg {
-/*00*/ u_char nc_scntl0; /* full arb., ena parity, par->ATN */
+/*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */
-/*01*/ u_char nc_scntl1; /* no reset */
+/*01*/ u8 nc_scntl1; /* no reset */
#define ISCON 0x10 /* connected to scsi */
#define CRST 0x08 /* force reset */
#define IARB 0x02 /* immediate arbitration */
-/*02*/ u_char nc_scntl2; /* no disconnect expected */
+/*02*/ u8 nc_scntl2; /* no disconnect expected */
#define SDU 0x80 /* cmd: disconnect will raise error */
#define CHM 0x40 /* sta: chained mode */
#define WSS 0x08 /* sta: wide scsi send [W]*/
#define WSR 0x01 /* sta: wide scsi received [W]*/
-/*03*/ u_char nc_scntl3; /* cnf system clock dependent */
+/*03*/ u8 nc_scntl3; /* cnf system clock dependent */
#define EWS 0x08 /* cmd: enable wide scsi [W]*/
#define ULTRA 0x80 /* cmd: ULTRA enable */
/* bits 0-2, 7 rsvd for C1010 */
-/*04*/ u_char nc_scid; /* cnf host adapter scsi address */
+/*04*/ u8 nc_scid; /* cnf host adapter scsi address */
#define RRE 0x40 /* r/w:e enable response to resel. */
#define SRE 0x20 /* r/w:e enable response to select */
-/*05*/ u_char nc_sxfer; /* ### Sync speed and count */
+/*05*/ u8 nc_sxfer; /* ### Sync speed and count */
/* bits 6-7 rsvd for C1010 */
-/*06*/ u_char nc_sdid; /* ### Destination-ID */
+/*06*/ u8 nc_sdid; /* ### Destination-ID */
-/*07*/ u_char nc_gpreg; /* ??? IO-Pins */
+/*07*/ u8 nc_gpreg; /* ??? IO-Pins */
-/*08*/ u_char nc_sfbr; /* ### First byte in phase */
+/*08*/ u8 nc_sfbr; /* ### First byte in phase */
-/*09*/ u_char nc_socl;
+/*09*/ u8 nc_socl;
#define CREQ 0x80 /* r/w: SCSI-REQ */
#define CACK 0x40 /* r/w: SCSI-ACK */
#define CBSY 0x20 /* r/w: SCSI-BSY */
#define CC_D 0x02 /* r/w: SCSI-C_D */
#define CI_O 0x01 /* r/w: SCSI-I_O */
-/*0a*/ u_char nc_ssid;
+/*0a*/ u8 nc_ssid;
-/*0b*/ u_char nc_sbcl;
+/*0b*/ u8 nc_sbcl;
-/*0c*/ u_char nc_dstat;
+/*0c*/ u8 nc_dstat;
#define DFE 0x80 /* sta: dma fifo empty */
#define MDPE 0x40 /* int: master data parity error */
#define BF 0x20 /* int: script: bus fault */
#define SIR 0x04 /* int: script: interrupt instruct. */
#define IID 0x01 /* int: script: illegal instruct. */
-/*0d*/ u_char nc_sstat0;
+/*0d*/ u8 nc_sstat0;
#define ILF 0x80 /* sta: data in SIDL register lsb */
#define ORF 0x40 /* sta: data in SODR register lsb */
#define OLF 0x20 /* sta: data in SODL register lsb */
#define IRST 0x02 /* sta: scsi reset signal */
#define SDP 0x01 /* sta: scsi parity signal */
-/*0e*/ u_char nc_sstat1;
+/*0e*/ u8 nc_sstat1;
#define FF3210 0xf0 /* sta: bytes in the scsi fifo */
-/*0f*/ u_char nc_sstat2;
+/*0f*/ u8 nc_sstat2;
#define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
#define ORF1 0x40 /* sta: data in SODR register msb[W]*/
#define OLF1 0x20 /* sta: data in SODL register msb[W]*/
#define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
#define LDSC 0x02 /* sta: disconnect & reconnect */
-/*10*/ u_char nc_dsa; /* --> Base page */
-/*11*/ u_char nc_dsa1;
-/*12*/ u_char nc_dsa2;
-/*13*/ u_char nc_dsa3;
+/*10*/ u8 nc_dsa; /* --> Base page */
+/*11*/ u8 nc_dsa1;
+/*12*/ u8 nc_dsa2;
+/*13*/ u8 nc_dsa3;
-/*14*/ u_char nc_istat; /* --> Main Command and status */
+/*14*/ u8 nc_istat; /* --> Main Command and status */
#define CABRT 0x80 /* cmd: abort current operation */
#define SRST 0x40 /* mod: reset chip */
#define SIGP 0x20 /* r/w: message from host to ncr */
#define SIP 0x02 /* sta: scsi-interrupt */
#define DIP 0x01 /* sta: host/script interrupt */
-/*15*/ u_char nc_istat1; /* 896 and later cores only */
+/*15*/ u8 nc_istat1; /* 896 and later cores only */
#define FLSH 0x04 /* sta: chip is flushing */
#define SRUN 0x02 /* sta: scripts are running */
#define SIRQD 0x01 /* r/w: disable INT pin */
-/*16*/ u_char nc_mbox0; /* 896 and later cores only */
-/*17*/ u_char nc_mbox1; /* 896 and later cores only */
+/*16*/ u8 nc_mbox0; /* 896 and later cores only */
+/*17*/ u8 nc_mbox1; /* 896 and later cores only */
-/*18*/ u_char nc_ctest0;
+/*18*/ u8 nc_ctest0;
#define EHP 0x04 /* 720 even host parity */
-/*19*/ u_char nc_ctest1;
+/*19*/ u8 nc_ctest1;
-/*1a*/ u_char nc_ctest2;
+/*1a*/ u8 nc_ctest2;
#define CSIGP 0x40
/* bits 0-2,7 rsvd for C1010 */
-/*1b*/ u_char nc_ctest3;
+/*1b*/ u8 nc_ctest3;
#define FLF 0x08 /* cmd: flush dma fifo */
#define CLF 0x04 /* cmd: clear dma fifo */
#define FM 0x02 /* mod: fetch pin mode */
/*1c*/ u32 nc_temp; /* ### Temporary stack */
-/*20*/ u_char nc_dfifo;
-/*21*/ u_char nc_ctest4;
+/*20*/ u8 nc_dfifo;
+/*21*/ u8 nc_ctest4;
#define MUX 0x80 /* 720 host bus multiplex mode */
#define BDIS 0x80 /* mod: burst disable */
#define MPEE 0x08 /* mod: master parity error enable */
-/*22*/ u_char nc_ctest5;
+/*22*/ u8 nc_ctest5;
#define DFS 0x20 /* mod: dma fifo size */
/* bits 0-1, 3-7 rsvd for C1010 */
-/*23*/ u_char nc_ctest6;
+/*23*/ u8 nc_ctest6;
/*24*/ u32 nc_dbc; /* ### Byte count and command */
/*28*/ u32 nc_dnad; /* ### Next command register */
/*2c*/ u32 nc_dsp; /* --> Script Pointer */
/*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */
-/*34*/ u_char nc_scratcha; /* Temporary register a */
-/*35*/ u_char nc_scratcha1;
-/*36*/ u_char nc_scratcha2;
-/*37*/ u_char nc_scratcha3;
+/*34*/ u8 nc_scratcha; /* Temporary register a */
+/*35*/ u8 nc_scratcha1;
+/*36*/ u8 nc_scratcha2;
+/*37*/ u8 nc_scratcha3;
-/*38*/ u_char nc_dmode;
+/*38*/ u8 nc_dmode;
#define BL_2 0x80 /* mod: burst length shift value +2 */
#define BL_1 0x40 /* mod: burst length shift value +1 */
#define ERL 0x08 /* mod: enable read line */
#define ERMP 0x04 /* mod: enable read multiple */
#define BOF 0x02 /* mod: burst op code fetch */
-/*39*/ u_char nc_dien;
-/*3a*/ u_char nc_sbr;
+/*39*/ u8 nc_dien;
+/*3a*/ u8 nc_sbr;
-/*3b*/ u_char nc_dcntl; /* --> Script execution control */
+/*3b*/ u8 nc_dcntl; /* --> Script execution control */
#define CLSE 0x80 /* mod: cache line size enable */
#define PFF 0x40 /* cmd: pre-fetch flush */
#define PFEN 0x20 /* mod: pre-fetch enable */
#define NOCOM 0x01 /* cmd: protect sfbr while reselect */
/* bits 0-1 rsvd for C1010 */
-/*3c*/ u32 nc_adder;
+/*3c*/ u32 nc_adder;
-/*40*/ u_short nc_sien; /* -->: interrupt enable */
-/*42*/ u_short nc_sist; /* <--: interrupt status */
+/*40*/ u16 nc_sien; /* -->: interrupt enable */
+/*42*/ u16 nc_sist; /* <--: interrupt status */
#define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
#define STO 0x0400/* sta: timeout (select) */
#define GEN 0x0200/* sta: timeout (general) */
#define RST 0x02 /* sta: scsi bus reset detected */
#define PAR 0x01 /* sta: scsi parity error */
-/*44*/ u_char nc_slpar;
-/*45*/ u_char nc_swide;
-/*46*/ u_char nc_macntl;
-/*47*/ u_char nc_gpcntl;
-/*48*/ u_char nc_stime0; /* cmd: timeout for select&handshake*/
-/*49*/ u_char nc_stime1; /* cmd: timeout user defined */
-/*4a*/ u_short nc_respid; /* sta: Reselect-IDs */
+/*44*/ u8 nc_slpar;
+/*45*/ u8 nc_swide;
+/*46*/ u8 nc_macntl;
+/*47*/ u8 nc_gpcntl;
+/*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/
+/*49*/ u8 nc_stime1; /* cmd: timeout user defined */
+/*4a*/ u16 nc_respid; /* sta: Reselect-IDs */
-/*4c*/ u_char nc_stest0;
+/*4c*/ u8 nc_stest0;
-/*4d*/ u_char nc_stest1;
+/*4d*/ u8 nc_stest1;
#define SCLK 0x80 /* Use the PCI clock as SCSI clock */
#define DBLEN 0x08 /* clock doubler running */
#define DBLSEL 0x04 /* clock doubler selected */
-/*4e*/ u_char nc_stest2;
+/*4e*/ u8 nc_stest2;
#define ROF 0x40 /* reset scsi offset (after gross error!) */
#define DIF 0x20 /* 720 SCSI differential mode */
#define EXT 0x02 /* extended filtering */
-/*4f*/ u_char nc_stest3;
+/*4f*/ u8 nc_stest3;
#define TE 0x80 /* c: tolerAnt enable */
#define HSC 0x20 /* c: Halt SCSI Clock */
#define CSF 0x02 /* c: clear scsi fifo */
-/*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */
-/*52*/ u_char nc_stest4;
+/*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */
+/*52*/ u8 nc_stest4;
#define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
#define SMODE_HVD 0x40 /* High Voltage Differential */
#define SMODE_SE 0x80 /* Single Ended */
#define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
/* bits 0-5 rsvd for C1010 */
-/*53*/ u_char nc_53_;
-/*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */
-/*56*/ u_char nc_ccntl0; /* Chip Control 0 (896) */
+/*53*/ u8 nc_53_;
+/*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */
+/*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
#define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
#define PMJCTL 0x40 /* Phase Mismatch Jump Control */
#define ENNDJ 0x20 /* Enable Non Data PM Jump */
#define DILS 0x02 /* Disable Internal Load/Store */
#define DPR 0x01 /* Disable Pipe Req */
-/*57*/ u_char nc_ccntl1; /* Chip Control 1 (896) */
+/*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */
#define ZMOD 0x80 /* High Impedance Mode */
#define DIC 0x10 /* Disable Internal Cycles */
#define DDAC 0x08 /* Disable Dual Address Cycle */
#define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
#define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
-/*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */
-/*5a*/ u_short nc_5a_;
-
-/*5c*/ u_char nc_scr0; /* Working register B */
-/*5d*/ u_char nc_scr1; /* */
-/*5e*/ u_char nc_scr2; /* */
-/*5f*/ u_char nc_scr3; /* */
-
-/*60*/ u_char nc_scrx[64]; /* Working register C-R */
-/*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */
-/*a4*/ u32 nc_mmws; /* Memory Move Write Selector */
-/*a8*/ u32 nc_sfs; /* Script Fetch Selector */
-/*ac*/ u32 nc_drs; /* DSA Relative Selector */
-/*b0*/ u32 nc_sbms; /* Static Block Move Selector */
-/*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
-/*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
-/*bc*/ u_short nc_scntl4; /* C1010 only */
+/*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */
+/*5a*/ u16 nc_5a_;
+
+/*5c*/ u8 nc_scr0; /* Working register B */
+/*5d*/ u8 nc_scr1; /* */
+/*5e*/ u8 nc_scr2; /* */
+/*5f*/ u8 nc_scr3; /* */
+
+/*60*/ u8 nc_scrx[64]; /* Working register C-R */
+/*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */
+/*a4*/ u32 nc_mmws; /* Memory Move Write Selector */
+/*a8*/ u32 nc_sfs; /* Script Fetch Selector */
+/*ac*/ u32 nc_drs; /* DSA Relative Selector */
+/*b0*/ u32 nc_sbms; /* Static Block Move Selector */
+/*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
+/*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
+/*bc*/ u16 nc_scntl4; /* C1010 only */
#define U3EN 0x80 /* Enable Ultra 3 */
#define AIPEN 0x40 /* Allow check upper byte lanes */
#define XCLKH_DT 0x08 /* Extra clock of data hold on DT
#define XCLKH_ST 0x04 /* Extra clock of data hold on ST
transfer edge */
-/*be*/ u_char nc_aipcntl0; /* Epat Control 1 C1010 only */
-/*bf*/ u_char nc_aipcntl1; /* AIP Control C1010_66 Only */
-
-/*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
-/*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
-/*c8*/ u_char nc_rbc; /* Remaining Byte Count */
-/*c9*/ u_char nc_rbc1; /* */
-/*ca*/ u_char nc_rbc2; /* */
-/*cb*/ u_char nc_rbc3; /* */
-
-/*cc*/ u_char nc_ua; /* Updated Address */
-/*cd*/ u_char nc_ua1; /* */
-/*ce*/ u_char nc_ua2; /* */
-/*cf*/ u_char nc_ua3; /* */
-/*d0*/ u32 nc_esa; /* Entry Storage Address */
-/*d4*/ u_char nc_ia; /* Instruction Address */
-/*d5*/ u_char nc_ia1;
-/*d6*/ u_char nc_ia2;
-/*d7*/ u_char nc_ia3;
-/*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
-/*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */
-
- /* Following for C1010 only */
-/*e0*/ u_short nc_crcpad; /* CRC Value */
-/*e2*/ u_char nc_crccntl0; /* CRC control register */
+/*be*/ u8 nc_aipcntl0; /* Epat Control 1 C1010 only */
+/*bf*/ u8 nc_aipcntl1; /* AIP Control C1010_66 Only */
+
+/*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
+/*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
+/*c8*/ u8 nc_rbc; /* Remaining Byte Count */
+/*c9*/ u8 nc_rbc1; /* */
+/*ca*/ u8 nc_rbc2; /* */
+/*cb*/ u8 nc_rbc3; /* */
+
+/*cc*/ u8 nc_ua; /* Updated Address */
+/*cd*/ u8 nc_ua1; /* */
+/*ce*/ u8 nc_ua2; /* */
+/*cf*/ u8 nc_ua3; /* */
+/*d0*/ u32 nc_esa; /* Entry Storage Address */
+/*d4*/ u8 nc_ia; /* Instruction Address */
+/*d5*/ u8 nc_ia1;
+/*d6*/ u8 nc_ia2;
+/*d7*/ u8 nc_ia3;
+/*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
+/*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */
+
+ /* Following for C1010 only */
+/*e0*/ u16 nc_crcpad; /* CRC Value */
+/*e2*/ u8 nc_crccntl0; /* CRC control register */
#define SNDCRC 0x10 /* Send CRC Request */
-/*e3*/ u_char nc_crccntl1; /* CRC control register */
-/*e4*/ u32 nc_crcdata; /* CRC data register */
-/*e8*/ u32 nc_e8_; /* rsvd */
-/*ec*/ u32 nc_ec_; /* rsvd */
-/*f0*/ u_short nc_dfbc; /* DMA FIFO byte count */
+/*e3*/ u8 nc_crccntl1; /* CRC control register */
+/*e4*/ u32 nc_crcdata; /* CRC data register */
+/*e8*/ u32 nc_e8_; /* rsvd */
+/*ec*/ u32 nc_ec_; /* rsvd */
+/*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */
};
#ifdef SCSI_NCR_BIG_ENDIAN
struct scr_tblsel {
- u_char sel_scntl3;
- u_char sel_id;
- u_char sel_sxfer;
- u_char sel_scntl4;
+ u8 sel_scntl3;
+ u8 sel_id;
+ u8 sel_sxfer;
+ u8 sel_scntl4;
};
#else
struct scr_tblsel {
- u_char sel_scntl4;
- u_char sel_sxfer;
- u_char sel_id;
- u_char sel_scntl3;
+ u8 sel_scntl4;
+ u8 sel_sxfer;
+ u8 sel_id;
+ u8 sel_scntl3;
};
#endif
* End of ncrreg from FreeBSD
*/
-#endif /* !defined HOSTS_C */
-
#endif /* defined SYM53C8XX_DEFS_H */
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