*
* SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
*
- * Copyright (C) 2002, 2003 Paul Mundt
+ * Copyright (C) 2002, 2003, 2004 Paul Mundt
*
* based off of the old drivers/char/sh-sci.c by:
*
* for more details.
*/
-#define DEBUG
-#include <linux/config.h>
+#undef DEBUG
+
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/console.h>
+#include <linux/bitops.h>
+#include <linux/generic_serial.h>
#ifdef CONFIG_CPU_FREQ
#include <linux/notifier.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
-#include <asm/bitops.h>
-#include <linux/generic_serial.h>
+#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
+#include <asm/clock.h>
+#endif
#ifdef CONFIG_SH_STANDARD_BIOS
#include <asm/sh_bios.h>
#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
/* Function prototypes */
-static void sci_stop_tx(struct uart_port *port, unsigned int tty_stop);
-static void sci_start_tx(struct uart_port *port, unsigned int tty_start);
+static void sci_stop_tx(struct uart_port *port);
+static void sci_start_tx(struct uart_port *port);
static void sci_start_rx(struct uart_port *port, unsigned int tty_start);
static void sci_stop_rx(struct uart_port *port);
static int sci_request_irq(struct sci_port *port);
static void sci_free_irq(struct sci_port *port);
-static struct sci_port sci_ports[SCI_NPORTS];
+static struct sci_port sci_ports[];
static struct uart_driver sci_uart_driver;
+#define SCI_NPORTS sci_uart_driver.nr
+
#if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
-static void handle_error(struct sci_port *port)
+static void handle_error(struct uart_port *port)
{ /* Clear error flags */
sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
}
-static int get_char(struct sci_port *port)
+static int get_char(struct uart_port *port)
{
unsigned long flags;
unsigned short status;
int usegdb=0;
#ifdef CONFIG_SH_STANDARD_BIOS
- /* This call only does a trap the first time it is
+ /* This call only does a trap the first time it is
* called, and so is safe to do here unconditionally
*/
usegdb |= sh_bios_in_gdb_mode();
/* tx mark output*/
H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
}
-#else
-static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag)
-{
-}
#endif
#endif
#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
-#if defined(CONFIG_CPU_SH3)
-/* For SH7707, SH7709, SH7709A, SH7729 */
+#if defined(CONFIG_CPU_SUBTYPE_SH7300)
+/* SH7300 doesn't use RTS/CTS */
+static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
+{
+ sci_out(port, SCFCR, 0);
+}
+#elif defined(CONFIG_CPU_SH3)
+/* For SH7705, SH7707, SH7709, SH7709A, SH7729 */
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
{
unsigned int fcr_val = 0;
+ unsigned short data;
- {
- unsigned short data;
+ /* We need to set SCPCR to enable RTS/CTS */
+ data = ctrl_inw(SCPCR);
+ /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
+ ctrl_outw(data & 0x0fcf, SCPCR);
- /* We need to set SCPCR to enable RTS/CTS */
- data = ctrl_inw(SCPCR);
- /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
- ctrl_outw(data&0x0fcf, SCPCR);
- }
if (cflag & CRTSCTS)
fcr_val |= SCFCR_MCE;
else {
- unsigned short data;
-
/* We need to set SCPCR to enable RTS/CTS */
data = ctrl_inw(SCPCR);
/* Clear out SCP7MD1,0, SCP4MD1,0,
Set SCP6MD1,0 = {01} (output) */
- ctrl_outw((data&0x0fcf)|0x1000, SCPCR);
+ ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
data = ctrl_inb(SCPDR);
/* Set /RTS2 (bit6) = 0 */
- ctrl_outb(data&0xbf, SCPDR);
+ ctrl_outb(data & 0xbf, SCPDR);
}
+
sci_out(port, SCFCR, fcr_val);
}
+#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
{
unsigned int fcr_val = 0;
sci_out(port, SCFCR, fcr_val);
}
-
+#endif
#else
/* For SH7750 */
if (cflag & CRTSCTS) {
fcr_val |= SCFCR_MCE;
} else {
+#ifdef CONFIG_CPU_SUBTYPE_SH7780
+ ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
+#else
ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
+#endif
}
sci_out(port, SCFCR, fcr_val);
}
#if !defined(SCI_ONLY)
if (port->type == PORT_SCIF) {
- txroom = 16 - (sci_in(port, SCFDR)>>8);
+#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
+ txroom = SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
+#else
+ txroom = SCIF_TXROOM_MAX - (sci_in(port, SCFDR)>>8);
+#endif
} else {
txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
if (uart_circ_empty(xmit)) {
- sci_stop_tx(port, 0);
+ sci_stop_tx(port);
} else {
local_irq_save(flags);
ctrl = sci_in(port, SCSCR);
struct tty_struct *tty = port->info->tty;
int i, count, copied = 0;
unsigned short status;
+ unsigned char flag;
status = sci_in(port, SCxSR);
if (!(status & SCxSR_RDxF(port)))
while (1) {
#if !defined(SCI_ONLY)
if (port->type == PORT_SCIF) {
- count = sci_in(port, SCFDR)&0x001f;
+#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
+ count = sci_in(port, SCRFDR) & 0x7f;
+#else
+ count = sci_in(port, SCFDR)&SCIF_RFDC_MASK ;
+#endif
} else {
count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
}
#endif
/* Don't copy more bytes than there is room for in the buffer */
- if (tty->flip.count + count > TTY_FLIPBUF_SIZE)
- count = TTY_FLIPBUF_SIZE - tty->flip.count;
+ count = tty_buffer_request_room(tty, count);
/* If for any reason we can't copy more data, we're done! */
if (count == 0)
|| uart_handle_sysrq_char(port, c, regs)) {
count = 0;
} else {
- tty->flip.char_buf_ptr[0] = c;
- tty->flip.flag_buf_ptr[0] = TTY_NORMAL;
+ tty_insert_flip_char(tty, c, TTY_NORMAL);
}
} else {
for (i=0; i<count; i++) {
}
/* Store data and status */
- tty->flip.char_buf_ptr[i] = c;
if (status&SCxSR_FER(port)) {
- tty->flip.flag_buf_ptr[i] = TTY_FRAME;
+ flag = TTY_FRAME;
pr_debug("sci: frame error\n");
} else if (status&SCxSR_PER(port)) {
- tty->flip.flag_buf_ptr[i] = TTY_PARITY;
+ flag = TTY_PARITY;
pr_debug("sci: parity error\n");
- } else {
- tty->flip.flag_buf_ptr[i] = TTY_NORMAL;
- }
+ } else
+ flag = TTY_NORMAL;
+ tty_insert_flip_char(tty, c, flag);
}
}
sci_in(port, SCxSR); /* dummy read */
sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
- /* Update the kernel buffer end */
- tty->flip.count += count;
- tty->flip.char_buf_ptr += count;
- tty->flip.flag_buf_ptr += count;
copied += count;
port->icount.rx += count;
}
unsigned short status = sci_in(port, SCxSR);
struct tty_struct *tty = port->info->tty;
- if (status&SCxSR_ORER(port) && tty->flip.count<TTY_FLIPBUF_SIZE) {
+ if (status&SCxSR_ORER(port)) {
/* overrun error */
- copied++;
- *tty->flip.flag_buf_ptr++ = TTY_OVERRUN;
+ if(tty_insert_flip_char(tty, 0, TTY_OVERRUN))
+ copied++;
pr_debug("sci: overrun error\n");
}
- if (status&SCxSR_FER(port) && tty->flip.count<TTY_FLIPBUF_SIZE) {
+ if (status&SCxSR_FER(port)) {
if (sci_rxd_in(port) == 0) {
/* Notify of BREAK */
struct sci_port * sci_port = (struct sci_port *)port;
- if(!sci_port->break_flag) {
- sci_port->break_flag = 1;
- sci_schedule_break_timer((struct sci_port *)port);
+ if(!sci_port->break_flag) {
+ sci_port->break_flag = 1;
+ sci_schedule_break_timer((struct sci_port *)port);
/* Do sysrq handling. */
- if(uart_handle_break(port)) {
+ if(uart_handle_break(port))
return 0;
- }
pr_debug("sci: BREAK detected\n");
- copied++;
- *tty->flip.flag_buf_ptr++ = TTY_BREAK;
+ if(tty_insert_flip_char(tty, 0, TTY_BREAK))
+ copied++;
}
}
else {
/* frame error */
- copied++;
- *tty->flip.flag_buf_ptr++ = TTY_FRAME;
+ if(tty_insert_flip_char(tty, 0, TTY_FRAME))
+ copied++;
pr_debug("sci: frame error\n");
}
}
- if (status&SCxSR_PER(port) && tty->flip.count<TTY_FLIPBUF_SIZE) {
+ if (status&SCxSR_PER(port)) {
+ if(tty_insert_flip_char(tty, 0, TTY_PARITY))
+ copied++;
/* parity error */
- copied++;
- *tty->flip.flag_buf_ptr++ = TTY_PARITY;
pr_debug("sci: parity error\n");
}
- if (copied) {
- tty->flip.count += copied;
+ if (copied)
tty_flip_buffer_push(tty);
- }
return copied;
}
struct tty_struct *tty = port->info->tty;
struct sci_port *s = &sci_ports[port->line];
- if (!s->break_flag && status & SCxSR_BRK(port) &&
- tty->flip.count < TTY_FLIPBUF_SIZE) {
+ if (!s->break_flag && status & SCxSR_BRK(port)) {
#if defined(CONFIG_CPU_SH3)
/* Debounce break */
s->break_flag = 1;
#endif
/* Notify of BREAK */
- copied++;
- *tty->flip.flag_buf_ptr++ = TTY_BREAK;
+ if(tty_insert_flip_char(tty, 0, TTY_BREAK))
+ copied++;
pr_debug("sci: BREAK detected\n");
}
-#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_ST40STB1) || \
- defined(CONFIG_CPU_SUBTYPE_SH7760)
+#if defined(SCIF_ORER)
/* XXX: Handle SCIF overrun error */
if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
sci_out(port, SCLSR, 0);
- if(tty->flip.count<TTY_FLIPBUF_SIZE) {
+ if(tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
copied++;
- *tty->flip.flag_buf_ptr++ = TTY_OVERRUN;
pr_debug("sci: overrun error\n");
}
}
#endif
- if (copied) {
- tty->flip.count += copied;
+ if (copied)
tty_flip_buffer_push(tty);
- }
-
return copied;
}
sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
}
} else {
+#if defined(SCIF_ORER)
+ if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
+ struct tty_struct *tty = port->info->tty;
+
+ sci_out(port, SCLSR, 0);
+ tty_insert_flip_char(tty, 0, TTY_OVERRUN);
+ tty_flip_buffer_push(tty);
+ pr_debug("scif: overrun error\n");
+ }
+#endif
sci_rx_interrupt(irq, ptr, regs);
}
return IRQ_HANDLED;
}
+static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr, struct pt_regs *regs)
+{
+ unsigned short ssr_status, scr_status;
+ struct uart_port *port = ptr;
+
+ ssr_status = sci_in(port,SCxSR);
+ scr_status = sci_in(port,SCSCR);
+
+ /* Tx Interrupt */
+ if ((ssr_status&0x0020) && (scr_status&0x0080))
+ sci_tx_interrupt(irq, ptr, regs);
+ /* Rx Interrupt */
+ if ((ssr_status&0x0002) && (scr_status&0x0040))
+ sci_rx_interrupt(irq, ptr, regs);
+ /* Error Interrupt */
+ if ((ssr_status&0x0080) && (scr_status&0x0400))
+ sci_er_interrupt(irq, ptr, regs);
+ /* Break Interrupt */
+ if ((ssr_status&0x0010) && (scr_status&0x0200))
+ sci_br_interrupt(irq, ptr, regs);
+
+ return IRQ_HANDLED;
+}
+
#ifdef CONFIG_CPU_FREQ
/*
* Here we define a transistion notifier so that we can update all of our
if ((phase == CPUFREQ_POSTCHANGE) ||
(phase == CPUFREQ_RESUMECHANGE)){
for (i = 0; i < SCI_NPORTS; i++) {
- struct uart_port *port = &sci_ports[i];
+ struct uart_port *port = &sci_ports[i].port;
+ struct clk *clk;
/*
* Update the uartclk per-port if frequency has
*
* Clean this up later..
*/
- port->uartclk = current_cpu_data.module_clock * 16;
+ clk = clk_get("module_clk");
+ port->uartclk = clk_get_rate(clk) * 16;
+ clk_put(clk);
}
printk("%s: got a postchange notification for cpu %d (old %d, new %d)\n",
const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
"SCI Transmit Data Empty", "SCI Break" };
- for (i = 0; i < ARRAY_SIZE(handlers); i++) {
- if (!port->irqs[i])
- continue;
- if (request_irq(port->irqs[i], handlers[i], SA_INTERRUPT,
- desc[i], port)) {
+ if (port->irqs[0] == port->irqs[1]) {
+ if (!port->irqs[0]) {
+ printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
+ return -ENODEV;
+ }
+ if (request_irq(port->irqs[0], sci_mpxed_interrupt, IRQF_DISABLED,
+ "sci", port)) {
printk(KERN_ERR "sci: Cannot allocate irq.\n");
return -ENODEV;
}
+ } else {
+ for (i = 0; i < ARRAY_SIZE(handlers); i++) {
+ if (!port->irqs[i])
+ continue;
+ if (request_irq(port->irqs[i], handlers[i], IRQF_DISABLED,
+ desc[i], port)) {
+ printk(KERN_ERR "sci: Cannot allocate irq.\n");
+ return -ENODEV;
+ }
+ }
}
return 0;
{
int i;
- for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
- if (!port->irqs[i])
- continue;
-
- free_irq(port->irqs[i], port);
+ if (port->irqs[0] == port->irqs[1]) {
+ if (!port->irqs[0])
+ printk("sci: sci_free_irq error\n");
+ else
+ free_irq(port->irqs[0], port);
+ } else {
+ for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
+ if (!port->irqs[i])
+ continue;
+
+ free_irq(port->irqs[i], port);
+ }
}
}
return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
}
-static void sci_start_tx(struct uart_port *port, unsigned int tty_start)
+static void sci_start_tx(struct uart_port *port)
{
struct sci_port *s = &sci_ports[port->line];
enable_irq(s->irqs[SCIx_TXI_IRQ]);
}
-static void sci_stop_tx(struct uart_port *port, unsigned int tty_stop)
+static void sci_stop_tx(struct uart_port *port)
{
unsigned long flags;
unsigned short ctrl;
/* Set RIE (Receive Interrupt Enable) bit in SCSCR */
local_irq_save(flags);
ctrl = sci_in(port, SCSCR);
- ctrl |= SCI_CTRL_FLAGS_RIE;
+ ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
sci_out(port, SCSCR, ctrl);
local_irq_restore(flags);
}
/* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
local_irq_save(flags);
ctrl = sci_in(port, SCSCR);
- ctrl &= ~SCI_CTRL_FLAGS_RIE;
+ ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
sci_out(port, SCSCR, ctrl);
local_irq_restore(flags);
}
#endif
sci_request_irq(s);
- sci_start_tx(port, 1);
+ sci_start_tx(port);
sci_start_rx(port, 1);
return 0;
struct sci_port *s = &sci_ports[port->line];
sci_stop_rx(port);
- sci_stop_tx(port, 1);
+ sci_stop_tx(port);
sci_free_irq(s);
#if defined(__H8300S__)
sci_out(port, SCSMR, smr_val);
switch (baud) {
- case 0: t = -1; break;
- case 2400: t = BPS_2400; break;
- case 4800: t = BPS_4800; break;
- case 9600: t = BPS_9600; break;
- case 19200: t = BPS_19200; break;
- case 38400: t = BPS_38400; break;
- case 57600: t = BPS_57600; break;
- case 115200: t = BPS_115200; break;
- default: t = BPS_115200; break;
+ case 0:
+ t = -1;
+ break;
+ default:
+ {
+#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
+ struct clk *clk = clk_get("module_clk");
+ t = SCBRR_VALUE(baud, clk_get_rate(clk));
+ clk_put(clk);
+#else
+ t = SCBRR_VALUE(baud);
+#endif
+ }
+ break;
}
if (t > 0) {
udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
}
- s->init_pins(port, termios->c_cflag);
+ if (likely(s->init_pins))
+ s->init_pins(port, termios->c_cflag);
+
sci_out(port, SCSCR, SCSCR_INIT(port));
if ((termios->c_cflag & CREAD) != 0)
struct sci_port *s = &sci_ports[port->line];
port->type = s->type;
+
+#if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
+ if (port->mapbase == 0)
+ port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
+
+ port->membase = (void *)port->mapbase;
+#endif
}
static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
.verify_port = sci_verify_port,
};
-static struct sci_port sci_ports[SCI_NPORTS] = {
+static struct sci_port sci_ports[] = {
#if defined(CONFIG_CPU_SUBTYPE_SH7708)
{
.port = {
.membase = (void *)0xfffffe80,
.mapbase = 0xfffffe80,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 25,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 0,
},
.type = PORT_SCI,
.irqs = SCI_IRQS,
- .init_pins = sci_init_pins_sci,
},
+#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
+ {
+ .port = {
+ .membase = (void *)SCIF0,
+ .mapbase = SCIF0,
+ .iotype = UPIO_MEM,
+ .irq = 55,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 0,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH3_IRDA_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
+ {
+ .port = {
+ .membase = (void *)SCIF2,
+ .mapbase = SCIF2,
+ .iotype = UPIO_MEM,
+ .irq = 59,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 1,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH3_SCIF_IRQS,
+ .init_pins = sci_init_pins_scif,
+ }
#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
{
.port = {
.membase = (void *)0xfffffe80,
.mapbase = 0xfffffe80,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 25,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 0,
},
.type = PORT_SCI,
.irqs = SCI_IRQS,
- .init_pins = sci_init_pins_sci,
},
{
.port = {
.membase = (void *)0xa4000150,
.mapbase = 0xa4000150,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 59,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 1,
},
.type = PORT_SCIF,
.port = {
.membase = (void *)0xa4000140,
.mapbase = 0xa4000140,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 55,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 2,
},
.type = PORT_IRDA,
.irqs = SH3_IRDA_IRQS,
.init_pins = sci_init_pins_irda,
}
+#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
+ {
+ .port = {
+ .membase = (void *)0xA4430000,
+ .mapbase = 0xA4430000,
+ .iotype = UPIO_MEM,
+ .irq = 25,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 0,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH7300_SCIF0_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
+#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
+ {
+ .port = {
+ .membase = (void *)0xffe00000,
+ .mapbase = 0xffe00000,
+ .iotype = UPIO_MEM,
+ .irq = 25,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 0,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH73180_SCIF_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
+#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
+ {
+ .port = {
+ .membase = (void *)0xffe80000,
+ .mapbase = 0xffe80000,
+ .iotype = UPIO_MEM,
+ .irq = 43,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 0,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH4_SCIF_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
{
.port = {
.membase = (void *)0xffe00000,
.mapbase = 0xffe00000,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 25,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 0,
},
.type = PORT_SCI,
.irqs = SCI_IRQS,
- .init_pins = sci_init_pins_sci,
},
{
.port = {
.membase = (void *)0xffe80000,
.mapbase = 0xffe80000,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 43,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 1,
},
.type = PORT_SCIF,
.port = {
.membase = (void *)0xfe600000,
.mapbase = 0xfe600000,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 55,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 0,
},
.type = PORT_SCIF,
.port = {
.membase = (void *)0xfe610000,
.mapbase = 0xfe610000,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 75,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 1,
},
.type = PORT_SCIF,
.port = {
.membase = (void *)0xfe620000,
.mapbase = 0xfe620000,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 79,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 2,
},
.type = PORT_SCIF,
.port = {
.membase = (void *)0xffe00000,
.mapbase = 0xffe00000,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 26,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 0,
},
.type = PORT_SCIF,
.port = {
.membase = (void *)0xffe80000,
.mapbase = 0xffe80000,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 43,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 1,
},
.type = PORT_SCIF,
.irqs = SH4_SCIF_IRQS,
.init_pins = sci_init_pins_scif,
},
+#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
+ {
+ .port = {
+ .iotype = UPIO_MEM,
+ .irq = 42,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 0,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH5_SCIF_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
{
.port = {
.membase = (void *)0x00ffffb0,
.mapbase = 0x00ffffb0,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 54,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 0,
},
.type = PORT_SCI,
.port = {
.membase = (void *)0x00ffffb8,
.mapbase = 0x00ffffb8,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 58,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 1,
},
.type = PORT_SCI,
.port = {
.membase = (void *)0x00ffffc0,
.mapbase = 0x00ffffc0,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 62,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 2,
},
.type = PORT_SCI,
.port = {
.membase = (void *)0x00ffff78,
.mapbase = 0x00ffff78,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 90,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 0,
},
.type = PORT_SCI,
.port = {
.membase = (void *)0x00ffff80,
.mapbase = 0x00ffff80,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 94,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 1,
},
.type = PORT_SCI,
.port = {
.membase = (void *)0x00ffff88,
.mapbase = 0x00ffff88,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 98,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 2,
},
.type = PORT_SCI,
.irqs = H8S_SCI_IRQS2,
.init_pins = sci_init_pins_sci,
},
+#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
+ {
+ .port = {
+ .membase = (void *)0xff923000,
+ .mapbase = 0xff923000,
+ .iotype = UPIO_MEM,
+ .irq = 61,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 0,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH7770_SCIF0_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
+ {
+ .port = {
+ .membase = (void *)0xff924000,
+ .mapbase = 0xff924000,
+ .iotype = UPIO_MEM,
+ .irq = 62,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 1,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH7770_SCIF1_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
+ {
+ .port = {
+ .membase = (void *)0xff925000,
+ .mapbase = 0xff925000,
+ .iotype = UPIO_MEM,
+ .irq = 63,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 2,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH7770_SCIF2_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
+#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
+ {
+ .port = {
+ .membase = (void *)0xffe00000,
+ .mapbase = 0xffe00000,
+ .iotype = UPIO_MEM,
+ .irq = 43,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 0,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH7780_SCIF0_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
+ {
+ .port = {
+ .membase = (void *)0xffe10000,
+ .mapbase = 0xffe10000,
+ .iotype = UPIO_MEM,
+ .irq = 79,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 1,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH7780_SCIF1_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
#else
#error "CPU subtype not defined"
#endif
int flow = 'n';
int ret;
- if (co->index >= SCI_NPORTS)
- co->index = 0;
-
serial_console_port = &sci_ports[co->index];
port = &serial_console_port->port;
port->type = serial_console_port->type;
+#ifdef CONFIG_SUPERH64
+ /* This is especially needed on sh64 to remap the SCIF */
+ sci_config_port(port, 0);
+#endif
+
/*
* We need to set the initial uartclk here, since otherwise it will
* only ever be setup at sci_init() time.
*/
-#if !defined(__H8300H__) && !defined(__H8300S__)
- port->uartclk = current_cpu_data.module_clock * 16;
-#else
+#if defined(__H8300H__) || defined(__H8300S__)
port->uartclk = CONFIG_CPU_CLOCK;
-#endif
+
#if defined(__H8300S__)
h8300_sci_enable(port, sci_enable);
+#endif
+#elif defined(CONFIG_SUPERH64)
+ port->uartclk = current_cpu_data.module_clock * 16;
+#else
+ {
+ struct clk *clk = clk_get("module_clk");
+ port->uartclk = clk_get_rate(clk) * 16;
+ clk_put(clk);
+ }
#endif
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
static int __init sci_console_init(void)
{
-#ifdef CONFIG_SH_EARLY_PRINTK
- extern void sh_console_unregister(void);
-
- /*
- * Now that the real console is available, unregister the one we
- * used while first booting.
- */
- sh_console_unregister();
-#endif
-
register_console(&serial_console);
-
return 0;
}
int parity = 'n';
int flow = 'n';
- if (co->index >= SCI_NPORTS || co->index != kgdb_portnum)
+ if (co->index != kgdb_portnum)
co->index = kgdb_portnum;
if (options)
/* Register the KGDB console so we get messages (d'oh!) */
static int __init kgdb_console_init(void)
{
- register_console(&kgdb_console);
-
+ register_console(&kgdb_console);
return 0;
}
#elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
#define SCI_CONSOLE &serial_console
#else
-#define SCI_CONSOLE 0
+#define SCI_CONSOLE 0
#endif
static char banner[] __initdata =
static struct uart_driver sci_uart_driver = {
.owner = THIS_MODULE,
.driver_name = "sci",
-#ifdef CONFIG_DEVFS_FS
- .devfs_name = "ttsc/",
-#endif
.dev_name = "ttySC",
.major = SCI_MAJOR,
.minor = SCI_MINOR_START,
- .nr = SCI_NPORTS,
.cons = SCI_CONSOLE,
};
printk("%s", banner);
+ sci_uart_driver.nr = ARRAY_SIZE(sci_ports);
+
ret = uart_register_driver(&sci_uart_driver);
if (ret == 0) {
for (chan = 0; chan < SCI_NPORTS; chan++) {
struct sci_port *sciport = &sci_ports[chan];
-#if !defined(__H8300H__) && !defined(__H8300S__)
- sciport->port.uartclk = (current_cpu_data.module_clock * 16);
-#else
+#if defined(__H8300H__) || defined(__H8300S__)
sciport->port.uartclk = CONFIG_CPU_CLOCK;
+#elif defined(CONFIG_SUPERH64)
+ sciport->port.uartclk = current_cpu_data.module_clock * 16;
+#else
+ struct clk *clk = clk_get("module_clk");
+ sciport->port.uartclk = clk_get_rate(clk) * 16;
+ clk_put(clk);
#endif
uart_add_one_port(&sci_uart_driver, &sciport->port);
sciport->break_timer.data = (unsigned long)sciport;
git://git.onelab.eu / linux-2.6.git / blobdiff