}
static int aty_var_to_pll_514(const struct fb_info *info, u32 vclk_per,
- u8 bpp, union aty_pll *pll)
+ u32 bpp, union aty_pll *pll)
{
/*
* FIXME: use real calculations instead of using fixed values from the old
temp = aty_ld_8(DAC_CNTL, par);
aty_st_8(DAC_CNTL, temp | DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3, par);
- if (info->fix.smem_len < MEM_SIZE_1M)
+ if (info->fix.smem_len < ONE_MB)
mask = 0x04;
- else if (info->fix.smem_len == MEM_SIZE_1M)
+ else if (info->fix.smem_len == ONE_MB)
mask = 0x08;
else
mask = 0x0C;
* ATI 18818 / ICS 2595 Clock Chip
*/
-static int aty_var_to_pll_18818(const struct fb_info *info,
- u32 vclk_per, u8 bpp, union aty_pll *pll)
+static int aty_var_to_pll_18818(const struct fb_info *info, u32 vclk_per,
+ u32 bpp, union aty_pll *pll)
{
u32 MHz100; /* in 0.01 MHz */
u32 program_bits;
* STG 1703 Clock Chip
*/
-static int aty_var_to_pll_1703(const struct fb_info *info,
- u32 vclk_per, u8 bpp, union aty_pll *pll)
+static int aty_var_to_pll_1703(const struct fb_info *info, u32 vclk_per,
+ u32 bpp, union aty_pll *pll)
{
u32 mhz100; /* in 0.01 MHz */
u32 program_bits;
* Chrontel 8398 Clock Chip
*/
-static int aty_var_to_pll_8398(const struct fb_info *info,
- u32 vclk_per, u8 bpp, union aty_pll *pll)
+static int aty_var_to_pll_8398(const struct fb_info *info, u32 vclk_per,
+ u32 bpp, union aty_pll *pll)
{
u32 tempA, tempB, fOut, longMHz100, diff, preDiff;
*/
static int aty_var_to_pll_408(const struct fb_info *info, u32 vclk_per,
- u8 bpp, union aty_pll *pll)
+ u32 bpp, union aty_pll *pll)
{
u32 mhz100; /* in 0.01 MHz */
u32 program_bits;