#undef SST_DEBUG
-#define SST_DEBUG_REG 0
-#define SST_DEBUG_FUNC 0
-#define SST_DEBUG_VAR 0
-
/* enable 24/32 bpp functions ? (completely untested!) */
#undef EN_24_32_BPP
#define dac_i_read(reg) __dac_i_read(par->mmio_vbase, reg)
#define dac_i_write(reg,val) __dac_i_write(par->mmio_vbase, reg, val)
-static inline u32 __sst_read(u_long vbase, u32 reg)
+static inline u32 __sst_read(u8 __iomem *vbase, u32 reg)
{
u32 ret = readl(vbase + reg);
sst_dbg_print_read_reg(reg, ret);
return ret;
}
-static inline void __sst_write(u_long vbase, u32 reg, u32 val)
+static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val)
{
sst_dbg_print_write_reg(reg, val);
writel(val, vbase + reg);
}
-static inline void __sst_set_bits(u_long vbase, u32 reg, u32 val)
+static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val)
{
r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val);
__sst_write(vbase, reg, __sst_read(vbase, reg) | val);
}
-static inline void __sst_unset_bits(u_long vbase, u32 reg, u32 val)
+static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val)
{
r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val);
__sst_write(vbase, reg, __sst_read(vbase, reg) & ~val);
#define sst_wait_idle() __sst_wait_idle(par->mmio_vbase)
-static int __sst_wait_idle(u_long vbase)
+static int __sst_wait_idle(u8 __iomem *vbase)
{
int count = 0;
/* dac access */
/* dac_read should be remaped to FbiInit2 (via the pci reg init_enable) */
-static u8 __sst_dac_read(u_long vbase, u8 reg)
+static u8 __sst_dac_read(u8 __iomem *vbase, u8 reg)
{
u8 ret;
return ret;
}
-static void __sst_dac_write(u_long vbase, u8 reg, u8 val)
+static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val)
{
r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val);
reg &= 0x07;
}
/* indexed access to ti/att dacs */
-static u32 __dac_i_read(u_long vbase, u8 reg)
+static u32 __dac_i_read(u8 __iomem *vbase, u8 reg)
{
u32 ret;
r_dprintk("sst_dac_read_i(%#x): %#x\n", reg, ret);
return ret;
}
-static void __dac_i_write(u_long vbase, u8 reg,u8 val)
+static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val)
{
r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val);
__sst_dac_write(vbase, DACREG_ADDR_I, reg);
*/
static int __devinit sst_get_memsize(struct fb_info *info, __u32 *memsize)
{
- u_long fbbase_virt = (u_long) info->screen_base;
+ u8 __iomem *fbbase_virt = info->screen_base;
/* force memsize */
if ((mem >= 1 ) && (mem <= 4)) {
goto fail_fb_mem;
}
- par->mmio_vbase = (u_long) ioremap_nocache(fix->mmio_start,
+ par->mmio_vbase = ioremap_nocache(fix->mmio_start,
fix->mmio_len);
if (!par->mmio_vbase) {
eprintk("cannot remap register area %#lx\n",
info->flags = FBINFO_DEFAULT;
info->fbops = &sstfb_ops;
- info->currcon = -1;
info->pseudo_palette = &all->pseudo_palette;
fix->type = FB_TYPE_PACKED_PIXELS;
fb_alloc_cmap(&info->cmap, 256, 0);
/* register fb */
+ info->device = &pdev->dev;
if (register_framebuffer(info) < 0) {
eprintk("can't register framebuffer.\n");
goto fail;
fail:
iounmap(info->screen_base);
fail_fb_remap:
- iounmap((void *)par->mmio_vbase);
+ iounmap(par->mmio_vbase);
fail_mmio_remap:
release_mem_region(fix->smem_start, 0x400000);
fail_fb_mem:
sst_shutdown(info);
unregister_framebuffer(info);
iounmap(info->screen_base);
- iounmap((void*)par->mmio_vbase);
+ iounmap(par->mmio_vbase);
release_mem_region(info->fix.smem_start, 0x400000);
release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
kfree(info);
static void sstfb_fillrect_softw( struct fb_info *info, const struct fb_fillrect *rect)
{
- unsigned long fbbase_virt = (unsigned long) info->screen_base;
+ u8 __iomem *fbbase_virt = info->screen_base;
int x, y, w = info->var.bits_per_pixel == 16 ? 2 : 4;
u32 color = rect->color, height = rect->height;
- unsigned long p;
+ u8 __iomem *p;
if (w==2) color |= color<<16;
for (y=rect->dy; height; y++, height--) {
MODULE_DESCRIPTION("FBDev driver for 3dfx Voodoo Graphics and Voodoo2 based video boards");
MODULE_LICENSE("GPL");
-MODULE_PARM(mem, "i");
+module_param(mem, int, 0);
MODULE_PARM_DESC(mem, "Size of frame buffer memory in MB (1, 2, 4 MB, default=autodetect)");
-MODULE_PARM(vgapass, "i");
+module_param(vgapass, bool, 0);
MODULE_PARM_DESC(vgapass, "Enable VGA PassThrough mode (0 or 1) (default=0)");
-MODULE_PARM(clipping , "i");
+module_param(clipping, bool, 0);
MODULE_PARM_DESC(clipping, "Enable clipping (slower, safer) (0 or 1) (default=1)");
-MODULE_PARM(gfxclk , "i");
+module_param(gfxclk, int, 0);
MODULE_PARM_DESC(gfxclk, "Force graphic chip frequency in MHz. DANGEROUS. (default=auto)");
-MODULE_PARM(slowpci, "i");
+module_param(slowpci, bool, 0);
MODULE_PARM_DESC(slowpci, "Uses slow PCI settings (0 or 1) (default=0)");