fedora core 6 1.2949 + vserver 2.2.0

[linux-2.6.git] / include / asm-arm / arch-at91rm9200 / hardware.h

diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
index 2646c01..9ea5bfe 100644 (file)
--- a/include/asm-arm/arch-at91rm9200/hardware.h
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -16,8 +16,16 @@
 
 #include <asm/sizes.h>
 
+#if defined(CONFIG_ARCH_AT91RM9200)
 #include <asm/arch/at91rm9200.h>
-#include <asm/arch/at91rm9200_sys.h>
+#elif defined(CONFIG_ARCH_AT91SAM9260)
+#include <asm/arch/at91sam9260.h>
+#elif defined(CONFIG_ARCH_AT91SAM9261)
+#include <asm/arch/at91sam9261.h>
+#else
+#error "Unsupported AT91 processor"
+#endif
+
 
 /*
  * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF
@@ -34,39 +42,27 @@
  * Virtual to Physical Address mapping for IO devices.
  */
 #define AT91_VA_BASE_SYS       AT91_IO_P2V(AT91_BASE_SYS)
-#define AT91_VA_BASE_SPI       AT91_IO_P2V(AT91_BASE_SPI)
-#define AT91_VA_BASE_SSC2      AT91_IO_P2V(AT91_BASE_SSC2)
-#define AT91_VA_BASE_SSC1      AT91_IO_P2V(AT91_BASE_SSC1)
-#define AT91_VA_BASE_SSC0      AT91_IO_P2V(AT91_BASE_SSC0)
-#define AT91_VA_BASE_US3       AT91_IO_P2V(AT91_BASE_US3)
-#define AT91_VA_BASE_US2       AT91_IO_P2V(AT91_BASE_US2)
-#define AT91_VA_BASE_US1       AT91_IO_P2V(AT91_BASE_US1)
-#define AT91_VA_BASE_US0       AT91_IO_P2V(AT91_BASE_US0)
-#define AT91_VA_BASE_EMAC      AT91_IO_P2V(AT91_BASE_EMAC)
-#define AT91_VA_BASE_TWI       AT91_IO_P2V(AT91_BASE_TWI)
-#define AT91_VA_BASE_MCI       AT91_IO_P2V(AT91_BASE_MCI)
-#define AT91_VA_BASE_UDP       AT91_IO_P2V(AT91_BASE_UDP)
-#define AT91_VA_BASE_TCB1      AT91_IO_P2V(AT91_BASE_TCB1)
-#define AT91_VA_BASE_TCB0      AT91_IO_P2V(AT91_BASE_TCB0)
-
-/* Internal SRAM */
-#define AT91_BASE_SRAM         0x00200000      /* Internal SRAM base address */
-#define AT91_SRAM_SIZE         0x00004000      /* Internal SRAM SIZE (16Kb) */
+#define AT91_VA_BASE_EMAC      AT91_IO_P2V(AT91RM9200_BASE_EMAC)
 
-/* Serial ports */
-#define AT91_NR_UART           5               /* 4 USART3's and one DBGU port */
+ /* Internal SRAM is mapped below the IO devices */
+#define AT91_SRAM_MAX          SZ_1M
+#define AT91_VIRT_BASE         (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
 
-/* FLASH */
-#define AT91_FLASH_BASE                0x10000000      /* NCS0: Flash physical base address */
+/* Serial ports */
+#define ATMEL_MAX_UART         7               /* 6 USART3's and one DBGU port (SAM9260) */
+
+/* External Memory Map */
+#define AT91_CHIPSELECT_0      0x10000000
+#define AT91_CHIPSELECT_1      0x20000000
+#define AT91_CHIPSELECT_2      0x30000000
+#define AT91_CHIPSELECT_3      0x40000000
+#define AT91_CHIPSELECT_4      0x50000000
+#define AT91_CHIPSELECT_5      0x60000000
+#define AT91_CHIPSELECT_6      0x70000000
+#define AT91_CHIPSELECT_7      0x80000000
 
 /* SDRAM */
-#define AT91_SDRAM_BASE                0x20000000      /* NCS1: SDRAM physical base address */
-
-/* SmartMedia */
-#define AT91_SMARTMEDIA_BASE   0x40000000      /* NCS3: Smartmedia physical base address */
-
-/* Multi-Master Memory controller */
-#define AT91_UHP_BASE          0x00300000      /* USB Host controller */
+#define AT91_SDRAM_BASE                AT91_CHIPSELECT_1
 
 /* Clocks */
 #define AT91_SLOW_CLOCK                32768           /* slow clock */
@@ -78,14 +74,14 @@ static inline unsigned int at91_sys_read(unsigned int reg_offset)
 {
        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
 
-       return readl(addr + reg_offset);
+       return __raw_readl(addr + reg_offset);
 }
 
 static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
 {
        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
 
-       writel(value, addr + reg_offset);
+       __raw_writel(value, addr + reg_offset);
 }
 #endif