*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
- * Copyright (C) 2002-2004 MontaVista Software, Inc.
+ * Copyright (C) 2002-2005 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* fallback to the default.
*/
static inline void __iomem *
-__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags, unsigned long align)
+__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags)
{
- extern void __iomem * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
if((addr < 0x48000000) || (addr > 0x4fffffff))
- return __ioremap(addr, size, flags, align);
+ return __ioremap(addr, size, flags);
return (void *)addr;
}
static inline void
__ixp4xx_iounmap(void __iomem *addr)
{
- extern void __iounmap(void __iomem *addr);
-
if ((u32)addr >= VMALLOC_START)
__iounmap(addr);
}
-#define __arch_ioremap(a, s, f, x) __ixp4xx_ioremap(a, s, f, x)
+#define __arch_ioremap(a, s, f) __ixp4xx_ioremap(a, s, f)
#define __arch_iounmap(a) __ixp4xx_iounmap(a)
-#define writeb(p, v) __ixp4xx_writeb(p, v)
-#define writew(p, v) __ixp4xx_writew(p, v)
-#define writel(p, v) __ixp4xx_writel(p, v)
+#define writeb(v, p) __ixp4xx_writeb(v, p)
+#define writew(v, p) __ixp4xx_writew(v, p)
+#define writel(v, p) __ixp4xx_writel(v, p)
#define writesb(p, v, l) __ixp4xx_writesb(p, v, l)
#define writesw(p, v, l) __ixp4xx_writesw(p, v, l)
#define readsl(p, v, l) __ixp4xx_readsl(p, v, l)
static inline void
-__ixp4xx_writeb(u8 value, u32 addr)
+__ixp4xx_writeb(u8 value, volatile void __iomem *p)
{
+ u32 addr = (u32)p;
u32 n, byte_enables, data;
if (addr >= VMALLOC_START) {
}
static inline void
-__ixp4xx_writesb(u32 bus_addr, u8 *vaddr, int count)
+__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count)
{
while (count--)
writeb(*vaddr++, bus_addr);
}
static inline void
-__ixp4xx_writew(u16 value, u32 addr)
+__ixp4xx_writew(u16 value, volatile void __iomem *p)
{
+ u32 addr = (u32)p;
u32 n, byte_enables, data;
if (addr >= VMALLOC_START) {
}
static inline void
-__ixp4xx_writesw(u32 bus_addr, u16 *vaddr, int count)
+__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
{
while (count--)
writew(*vaddr++, bus_addr);
}
static inline void
-__ixp4xx_writel(u32 value, u32 addr)
+__ixp4xx_writel(u32 value, volatile void __iomem *p)
{
+ u32 addr = (u32)p;
if (addr >= VMALLOC_START) {
__raw_writel(value, addr);
return;
}
static inline void
-__ixp4xx_writesl(u32 bus_addr, u32 *vaddr, int count)
+__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count)
{
while (count--)
writel(*vaddr++, bus_addr);
}
static inline unsigned char
-__ixp4xx_readb(u32 addr)
+__ixp4xx_readb(const volatile void __iomem *p)
{
+ u32 addr = (u32)p;
u32 n, byte_enables, data;
if (addr >= VMALLOC_START)
}
static inline void
-__ixp4xx_readsb(u32 bus_addr, u8 *vaddr, u32 count)
+__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count)
{
while (count--)
*vaddr++ = readb(bus_addr);
}
static inline unsigned short
-__ixp4xx_readw(u32 addr)
+__ixp4xx_readw(const volatile void __iomem *p)
{
+ u32 addr = (u32)p;
u32 n, byte_enables, data;
if (addr >= VMALLOC_START)
}
static inline void
-__ixp4xx_readsw(u32 bus_addr, u16 *vaddr, u32 count)
+__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
{
while (count--)
*vaddr++ = readw(bus_addr);
}
static inline unsigned long
-__ixp4xx_readl(u32 addr)
+__ixp4xx_readl(const volatile void __iomem *p)
{
+ u32 addr = (u32)p;
u32 data;
if (addr >= VMALLOC_START)
}
static inline void
-__ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count)
+__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
{
while (count--)
*vaddr++ = readl(bus_addr);
eth_copy_and_sum((s),__mem_pci(c),(l),(b))
static inline int
-check_signature(unsigned long bus_addr, const unsigned char *signature,
+check_signature(const unsigned char __iomem *bus_addr, const unsigned char *signature,
int length)
{
int retval = 0;
#endif
+#ifndef CONFIG_PCI
+
+#define __io(v) v
+
+#else
+
/*
* IXP4xx does not have a transparent cpu -> PCI I/O translation
* window. Instead, it has a set of registers that must be tweaked
*vaddr++ = inl(io_addr);
}
+#define PIO_OFFSET 0x10000UL
+#define PIO_MASK 0x0ffffUL
+
+#define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \
+ ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
+static inline unsigned int
+__ixp4xx_ioread8(const void __iomem *addr)
+{
+ unsigned long port = (unsigned long __force)addr;
+ if (__is_io_address(port))
+ return (unsigned int)__ixp4xx_inb(port & PIO_MASK);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ return (unsigned int)__raw_readb(port);
+#else
+ return (unsigned int)__ixp4xx_readb(addr);
+#endif
+}
+
+static inline void
+__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
+{
+ unsigned long port = (unsigned long __force)addr;
+ if (__is_io_address(port))
+ __ixp4xx_insb(port & PIO_MASK, vaddr, count);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_readsb(addr, vaddr, count);
+#else
+ __ixp4xx_readsb(addr, vaddr, count);
+#endif
+}
+
+static inline unsigned int
+__ixp4xx_ioread16(const void __iomem *addr)
+{
+ unsigned long port = (unsigned long __force)addr;
+ if (__is_io_address(port))
+ return (unsigned int)__ixp4xx_inw(port & PIO_MASK);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ return le16_to_cpu(__raw_readw((u32)port));
+#else
+ return (unsigned int)__ixp4xx_readw(addr);
+#endif
+}
+
+static inline void
+__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count)
+{
+ unsigned long port = (unsigned long __force)addr;
+ if (__is_io_address(port))
+ __ixp4xx_insw(port & PIO_MASK, vaddr, count);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_readsw(addr, vaddr, count);
+#else
+ __ixp4xx_readsw(addr, vaddr, count);
+#endif
+}
+
+static inline unsigned int
+__ixp4xx_ioread32(const void __iomem *addr)
+{
+ unsigned long port = (unsigned long __force)addr;
+ if (__is_io_address(port))
+ return (unsigned int)__ixp4xx_inl(port & PIO_MASK);
+ else {
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ return le32_to_cpu(__raw_readl((u32)port));
+#else
+ return (unsigned int)__ixp4xx_readl(addr);
+#endif
+ }
+}
+
+static inline void
+__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count)
+{
+ unsigned long port = (unsigned long __force)addr;
+ if (__is_io_address(port))
+ __ixp4xx_insl(port & PIO_MASK, vaddr, count);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_readsl(addr, vaddr, count);
+#else
+ __ixp4xx_readsl(addr, vaddr, count);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite8(u8 value, void __iomem *addr)
+{
+ unsigned long port = (unsigned long __force)addr;
+ if (__is_io_address(port))
+ __ixp4xx_outb(value, port & PIO_MASK);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_writeb(value, port);
+#else
+ __ixp4xx_writeb(value, addr);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
+{
+ unsigned long port = (unsigned long __force)addr;
+ if (__is_io_address(port))
+ __ixp4xx_outsb(port & PIO_MASK, vaddr, count);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_writesb(addr, vaddr, count);
+#else
+ __ixp4xx_writesb(addr, vaddr, count);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite16(u16 value, void __iomem *addr)
+{
+ unsigned long port = (unsigned long __force)addr;
+ if (__is_io_address(port))
+ __ixp4xx_outw(value, port & PIO_MASK);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_writew(cpu_to_le16(value), addr);
+#else
+ __ixp4xx_writew(value, addr);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
+{
+ unsigned long port = (unsigned long __force)addr;
+ if (__is_io_address(port))
+ __ixp4xx_outsw(port & PIO_MASK, vaddr, count);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_writesw(addr, vaddr, count);
+#else
+ __ixp4xx_writesw(addr, vaddr, count);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite32(u32 value, void __iomem *addr)
+{
+ unsigned long port = (unsigned long __force)addr;
+ if (__is_io_address(port))
+ __ixp4xx_outl(value, port & PIO_MASK);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_writel(cpu_to_le32(value), port);
+#else
+ __ixp4xx_writel(value, addr);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
+{
+ unsigned long port = (unsigned long __force)addr;
+ if (__is_io_address(port))
+ __ixp4xx_outsl(port & PIO_MASK, vaddr, count);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_writesl(addr, vaddr, count);
+#else
+ __ixp4xx_writesl(addr, vaddr, count);
+#endif
+}
+
+#define ioread8(p) __ixp4xx_ioread8(p)
+#define ioread16(p) __ixp4xx_ioread16(p)
+#define ioread32(p) __ixp4xx_ioread32(p)
+
+#define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c)
+#define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c)
+#define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c)
+
+#define iowrite8(v,p) __ixp4xx_iowrite8(v,p)
+#define iowrite16(v,p) __ixp4xx_iowrite16(v,p)
+#define iowrite32(v,p) __ixp4xx_iowrite32(v,p)
+
+#define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c)
+#define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c)
+#define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c)
+
+#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
+#define ioport_unmap(addr)
+#endif // !CONFIG_PCI
#endif // __ASM_ARM_ARCH_IO_H
git://git.onelab.eu / linux-2.6.git / blobdiff