-/* linux/include/asm-arm/arch-s3c2410/dma.h
+/* linux/include/asm-arm/arch-bast/dma.h
*
- * Copyright (C) 2003,2004,2006 Simtec Electronics
+ * Copyright (C) 2003,2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
- * Samsung S3C241XX DMA support
+ * Samsung S3C2410X DMA support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
+ *
+ * Changelog:
+ * ??-May-2003 BJD Created file
+ * ??-Jun-2003 BJD Added more dma functionality to go with arch
+ * 10-Nov-2004 BJD Added sys_device support
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H __FILE__
+#include <linux/config.h>
#include <linux/sysdev.h>
#include "hardware.h"
+
/*
* This is the maximum DMA address(physical address) that can be DMAd to.
*
*/
-#define MAX_DMA_ADDRESS 0x40000000
+#define MAX_DMA_ADDRESS 0x20000000
#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
+
/* we have 4 dma channels */
#define S3C2410_DMA_CHANNELS (4)
/* types */
-enum s3c2410_dma_state {
+typedef enum {
S3C2410_DMA_IDLE,
S3C2410_DMA_RUNNING,
S3C2410_DMA_PAUSED
-};
+} s3c2410_dma_state_t;
-/* enum s3c2410_dma_loadst
+/* s3c2410_dma_loadst_t
*
* This represents the state of the DMA engine, wrt to the loaded / running
* transfers. Since we don't have any way of knowing exactly the state of
* currently running.
*/
-enum s3c2410_dma_loadst {
+typedef enum {
S3C2410_DMALOAD_NONE,
S3C2410_DMALOAD_1LOADED,
S3C2410_DMALOAD_1RUNNING,
S3C2410_DMALOAD_1LOADED_1RUNNING,
-};
+} s3c2410_dma_loadst_t;
-enum s3c2410_dma_buffresult {
+typedef enum {
S3C2410_RES_OK,
S3C2410_RES_ERR,
S3C2410_RES_ABORT
-};
+} s3c2410_dma_buffresult_t;
-enum s3c2410_dmasrc {
- S3C2410_DMASRC_HW, /* source is memory */
- S3C2410_DMASRC_MEM /* source is hardware */
+
+typedef enum s3c2410_dmasrc_e s3c2410_dmasrc_t;
+
+enum s3c2410_dmasrc_e {
+ S3C2410_DMASRC_HW, /* source is memory */
+ S3C2410_DMASRC_MEM /* source is hardware */
};
-/* enum s3c2410_chan_op
+/* enum s3c2410_chan_op_e
*
* operation codes passed to the DMA code by the user, and also used
* to inform the current channel owner of any changes to the system state
*/
-enum s3c2410_chan_op {
+enum s3c2410_chan_op_e {
S3C2410_DMAOP_START,
S3C2410_DMAOP_STOP,
S3C2410_DMAOP_PAUSE,
S3C2410_DMAOP_RESUME,
S3C2410_DMAOP_FLUSH,
- S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
- S3C2410_DMAOP_STARTED, /* indicate channel started */
+ S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
};
+typedef enum s3c2410_chan_op_e s3c2410_chan_op_t;
+
/* flags */
#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
/* dma buffer */
+typedef struct s3c2410_dma_buf_s s3c2410_dma_buf_t;
+
struct s3c2410_dma_client {
char *name;
};
+typedef struct s3c2410_dma_client s3c2410_dma_client_t;
+
/* s3c2410_dma_buf_s
*
* internally used buffer structure to describe a queued or running
* buffer.
*/
-struct s3c2410_dma_buf;
-struct s3c2410_dma_buf {
- struct s3c2410_dma_buf *next;
- int magic; /* magic */
- int size; /* buffer size in bytes */
- dma_addr_t data; /* start of DMA data */
- dma_addr_t ptr; /* where the DMA got to [1] */
- void *id; /* client's id */
+struct s3c2410_dma_buf_s {
+ s3c2410_dma_buf_t *next;
+ int magic; /* magic */
+ int size; /* buffer size in bytes */
+ dma_addr_t data; /* start of DMA data */
+ dma_addr_t ptr; /* where the DMA got to [1] */
+ void *id; /* client's id */
};
/* [1] is this updated for both recv/send modes? */
-struct s3c2410_dma_chan;
+typedef struct s3c2410_dma_chan_s s3c2410_dma_chan_t;
/* s3c2410_dma_cbfn_t
*
* buffer callback routine type
*/
-typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
- void *buf, int size,
- enum s3c2410_dma_buffresult result);
+typedef void (*s3c2410_dma_cbfn_t)(s3c2410_dma_chan_t *, void *buf, int size,
+ s3c2410_dma_buffresult_t result);
-typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
- enum s3c2410_chan_op );
+typedef int (*s3c2410_dma_opfn_t)(s3c2410_dma_chan_t *,
+ s3c2410_chan_op_t );
-struct s3c2410_dma_stats {
- unsigned long loads;
- unsigned long timeout_longest;
- unsigned long timeout_shortest;
- unsigned long timeout_avg;
- unsigned long timeout_failed;
+struct s3c2410_dma_stats_s {
+ unsigned long loads;
+ unsigned long timeout_longest;
+ unsigned long timeout_shortest;
+ unsigned long timeout_avg;
+ unsigned long timeout_failed;
};
-/* struct s3c2410_dma_chan
+typedef struct s3c2410_dma_stats_s s3c2410_dma_stats_t;
+
+/* struct s3c2410_dma_chan_s
*
* full state information for each DMA channel
*/
-struct s3c2410_dma_chan {
+struct s3c2410_dma_chan_s {
/* channel state flags and information */
- unsigned char number; /* number of this dma channel */
- unsigned char in_use; /* channel allocated */
- unsigned char irq_claimed; /* irq claimed for channel */
- unsigned char irq_enabled; /* irq enabled for channel */
- unsigned char xfer_unit; /* size of an transfer */
+ unsigned char number; /* number of this dma channel */
+ unsigned char in_use; /* channel allocated */
+ unsigned char irq_claimed; /* irq claimed for channel */
+ unsigned char irq_enabled; /* irq enabled for channel */
+ unsigned char xfer_unit; /* size of an transfer */
/* channel state */
- enum s3c2410_dma_state state;
- enum s3c2410_dma_loadst load_state;
- struct s3c2410_dma_client *client;
+ s3c2410_dma_state_t state;
+ s3c2410_dma_loadst_t load_state;
+ s3c2410_dma_client_t *client;
/* channel configuration */
- enum s3c2410_dmasrc source;
- unsigned long dev_addr;
- unsigned long load_timeout;
- unsigned int flags; /* channel flags */
+ s3c2410_dmasrc_t source;
+ unsigned long dev_addr;
+ unsigned long load_timeout;
+ unsigned int flags; /* channel flags */
/* channel's hardware position and configuration */
- void __iomem *regs; /* channels registers */
- void __iomem *addr_reg; /* data address register */
- unsigned int irq; /* channel irq */
- unsigned long dcon; /* default value of DCON */
+ void __iomem *regs; /* channels registers */
+ void __iomem *addr_reg; /* data address register */
+ unsigned int irq; /* channel irq */
+ unsigned long dcon; /* default value of DCON */
/* driver handles */
- s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
- s3c2410_dma_opfn_t op_fn; /* channel op callback */
+ s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
+ s3c2410_dma_opfn_t op_fn; /* channel operation callback */
/* stats gathering */
- struct s3c2410_dma_stats *stats;
- struct s3c2410_dma_stats stats_store;
+ s3c2410_dma_stats_t *stats;
+ s3c2410_dma_stats_t stats_store;
/* buffer list and information */
- struct s3c2410_dma_buf *curr; /* current dma buffer */
- struct s3c2410_dma_buf *next; /* next buffer to load */
- struct s3c2410_dma_buf *end; /* end of queue */
+ s3c2410_dma_buf_t *curr; /* current dma buffer */
+ s3c2410_dma_buf_t *next; /* next buffer to load */
+ s3c2410_dma_buf_t *end; /* end of queue */
/* system device */
struct sys_device dev;
};
/* the currently allocated channel information */
-extern struct s3c2410_dma_chan s3c2410_chans[];
+extern s3c2410_dma_chan_t s3c2410_chans[];
/* note, we don't really use dma_device_t at the moment */
typedef unsigned long dma_device_t;
*/
extern int s3c2410_dma_request(dmach_t channel,
- struct s3c2410_dma_client *, void *dev);
+ s3c2410_dma_client_t *, void *dev);
/* s3c2410_dma_ctrl
* change the state of the dma channel
*/
-extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op);
+extern int s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op);
/* s3c2410_dma_setflags
*
* free the dma channel (will also abort any outstanding operations)
*/
-extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *);
+extern int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *);
/* s3c2410_dma_enqueue
*
* configure the device we're talking to
*/
-extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
+extern int s3c2410_dma_devconfig(int channel, s3c2410_dmasrc_t source,
int hwcfg, unsigned long devaddr);
/* s3c2410_dma_getposition
git://git.onelab.eu / linux-2.6.git / blobdiff