vserver 2.0 rc7

[linux-2.6.git] / include / asm-arm / arch-s3c2410 / regs-mem.h

diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h
index 400fbd7..a2d7d0c 100644 (file)
--- a/include/asm-arm/arch-s3c2410/regs-mem.h
+++ b/include/asm-arm/arch-s3c2410/regs-mem.h
@@ -11,6 +11,8 @@
  *
  *  Changelog:
  *     29-Sep-2004  BJD  Initial include for Linux
+ *      10-Mar-2005  LCVR Changed S3C2410_VA to S3C24XX_VA
+ *      04-Apr-2005  LCVR Added S3C2400 DRAM/BANKSIZE_MASK definitions
  *
 */
 
@@ -18,7 +20,7 @@
 #define __ASM_ARM_MEMREGS_H "$Id: regs.h,v 1.8 2003/05/01 15:55:41 ben Exp $"
 
 #ifndef S3C2410_MEMREG
-#define S3C2410_MEMREG(x) (S3C2410_VA_MEMCTRL + (x))
+#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
 #endif
 
 /* bus width, and wait state control */
@@ -133,8 +135,29 @@
 #define S3C2410_BANKCON_Tacs4          (0x3 << 13)
 
 #define S3C2410_BANKCON_SRAM           (0x0 << 15)
+#define S3C2400_BANKCON_EDODRAM                (0x2 << 15)
 #define S3C2410_BANKCON_SDRAM          (0x3 << 15)
 
+/* next bits only for EDO DRAM in 6,7 */
+#define S3C2400_BANKCON_EDO_Trdc1      (0x00 << 4)
+#define S3C2400_BANKCON_EDO_Trdc2      (0x01 << 4)
+#define S3C2400_BANKCON_EDO_Trdc3      (0x02 << 4)
+#define S3C2400_BANKCON_EDO_Trdc4      (0x03 << 4)
+
+/* CAS pulse width */
+#define S3C2400_BANKCON_EDO_PULSE1     (0x00 << 3)
+#define S3C2400_BANKCON_EDO_PULSE2     (0x01 << 3)
+
+/* CAS pre-charge */
+#define S3C2400_BANKCON_EDO_TCP1       (0x00 << 2)
+#define S3C2400_BANKCON_EDO_TCP2       (0x01 << 2)
+
+/* control column address select */
+#define S3C2400_BANKCON_EDO_SCANb8     (0x00 << 0)
+#define S3C2400_BANKCON_EDO_SCANb9     (0x01 << 0)
+#define S3C2400_BANKCON_EDO_SCANb10    (0x02 << 0)
+#define S3C2400_BANKCON_EDO_SCANb11    (0x03 << 0)
+
 /* next bits only for SDRAM in 6,7 */
 #define S3C2410_BANKCON_Trdc2          (0x00 << 2)
 #define S3C2410_BANKCON_Trdc3          (0x01 << 2)
@@ -161,6 +184,12 @@
 #define S3C2410_REFRESH_TRP_3clk       (1<<20)
 #define S3C2410_REFRESH_TRP_4clk       (2<<20)
 
+#define S3C2400_REFRESH_DRAM_TRP_MASK   (3<<20)
+#define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20)
+#define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20)
+#define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20)
+#define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20)
+
 #define S3C2410_REFRESH_TSRC_MASK      (3<<18)
 #define S3C2410_REFRESH_TSRC_4clk      (0<<18)
 #define S3C2410_REFRESH_TSRC_5clk      (1<<18)
@@ -183,6 +212,7 @@
 #define S3C2410_BANKSIZE_4M            (0x5 << 0)
 #define S3C2410_BANKSIZE_2M            (0x4 << 0)
 #define S3C2410_BANKSIZE_MASK          (0x7 << 0)
+#define S3C2400_BANKSIZE_MASK           (0x4 << 0)
 #define S3C2410_BANKSIZE_SCLK_EN       (1<<4)
 #define S3C2410_BANKSIZE_SCKE_EN       (1<<5)
 #define S3C2410_BANKSIZE_BURST         (1<<7)