linux 2.6.16.38 w/ vs2.0.3-rc1

[linux-2.6.git] / include / asm-arm / system.h

diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index 0947cbf..ec91d1f 100644 (file)
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -3,6 +3,7 @@
 
 #ifdef __KERNEL__
 
+#include <linux/config.h>
 
 #define CPU_ARCH_UNKNOWN       0
 #define CPU_ARCH_ARMv3         1
@@ -107,34 +108,6 @@ extern void __show_regs(struct pt_regs *);
 extern int cpu_architecture(void);
 extern void cpu_init(void);
 
-void arm_machine_restart(char mode);
-extern void (*arm_pm_restart)(char str);
-
-/*
- * Intel's XScale3 core supports some v6 features (supersections, L2)
- * but advertises itself as v5 as it does not support the v6 ISA.  For
- * this reason, we need a way to explicitly test for this type of CPU.
- */
-#ifndef CONFIG_CPU_XSC3
-#define cpu_is_xsc3()  0
-#else
-static inline int cpu_is_xsc3(void)
-{
-       extern unsigned int processor_id;
-
-       if ((processor_id & 0xffffe000) == 0x69056000)
-               return 1;
-
-       return 0;
-}
-#endif
-
-#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
-#define        cpu_is_xscale() 0
-#else
-#define        cpu_is_xscale() 1
-#endif
-
 #define set_cr(x)                                      \
        __asm__ __volatile__(                           \
        "mcr    p15, 0, %0, c1, c0, 0   @ set CR"       \
@@ -176,6 +149,7 @@ extern unsigned int user_debug;
 #define wmb() mb()
 #define read_barrier_depends() do { } while(0)
 #define set_mb(var, value)  do { var = value; mb(); } while (0)
+#define set_wmb(var, value) do { var = value; wmb(); } while (0)
 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 
 /*