__asm__ __volatile__(
"stc ccr,r3l\n\t"
"orc #0x80,ccr\n\t"
- "mov.l %0, er1\n\t"
+ "mov.l %2, er1\n\t"
"dec.l #1,er1\n\t"
"mov.l er1,%0\n\t"
"bpl 1f\n\t"
"1:\n\t"
"ldc r3l,ccr\n"
"2:"
- : "+m"(*count)
- : "g"(sem)
+ : "=m"(*count)
+ : "g"(sem),"m"(*count)
: "cc", "er1", "er2", "er3");
}
__asm__ __volatile__(
"stc ccr,r1l\n\t"
"orc #0x80,ccr\n\t"
- "mov.l %1, er2\n\t"
+ "mov.l %3, er2\n\t"
"dec.l #1,er2\n\t"
"mov.l er2,%1\n\t"
"bpl 1f\n\t"
"ldc r1l,ccr\n\t"
"sub.l %0,%0\n\t"
"2:\n\t"
- : "=r" (count),"+m" (*count)
- : "g"(sem)
+ : "=r" (count),"=m" (*count)
+ : "g"(sem),"m"(*count)
: "cc", "er1", "er2", "er3");
return (int)count;
}
__asm__ __volatile__(
"stc ccr,r3l\n\t"
"orc #0x80,ccr\n\t"
- "mov.l %0,er2\n\t"
+ "mov.l %3,er2\n\t"
"dec.l #1,er2\n\t"
"mov.l er2,%0\n\t"
"bpl 1f\n\t"
"ldc r3l,ccr\n\t"
"sub.l %1,%1\n"
"2:"
- : "+m" (*count),"=r"(count)
- : "g"(sem)
+ : "=m" (*count),"=r"(count)
+ : "g"(sem),"m"(*count)
: "cc", "er1","er2", "er3");
return (int)count;
}
__asm__ __volatile__(
"stc ccr,r3l\n\t"
"orc #0x80,ccr\n\t"
- "mov.l %0,er1\n\t"
+ "mov.l %2,er1\n\t"
"inc.l #1,er1\n\t"
"mov.l er1,%0\n\t"
"ldc r3l,ccr\n\t"
"mov.l %1,er0\n\t"
"jsr @___up\n"
"1:"
- : "+m"(*count)
- : "g"(sem)
+ : "=m"(*count)
+ : "g"(sem),"m"(*count)
: "cc", "er1", "er2", "er3");
}