linux 2.6.16.38 w/ vs2.0.3-rc1

[linux-2.6.git] / include / asm-mips / cpu.h

diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index d38fdbf..818b9a9 100644 (file)
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -51,7 +51,6 @@
 #define PRID_IMP_R4300         0x0b00
 #define PRID_IMP_VR41XX                0x0c00
 #define PRID_IMP_R12000                0x0e00
-#define PRID_IMP_R14000                0x0f00
 #define PRID_IMP_R8000         0x1000
 #define PRID_IMP_PR4450                0x1200
 #define PRID_IMP_R4600         0x2000
@@ -88,7 +87,6 @@
 #define PRID_IMP_24K           0x9300
 #define PRID_IMP_34K           0x9500
 #define PRID_IMP_24KE          0x9600
-#define PRID_IMP_74K           0x9700
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -198,9 +196,7 @@
 #define CPU_34K                        60
 #define CPU_PR4450             61
 #define CPU_SB1A               62
-#define CPU_74K                        63
-#define CPU_R14000             64
-#define CPU_LAST               64
+#define CPU_LAST               62
 
 /*
  * ISA Level encodings
@@ -242,7 +238,7 @@
 #define MIPS_CPU_EJTAG         0x00008000 /* EJTAG exception */
 #define MIPS_CPU_NOFPUEX       0x00010000 /* no FPU exception */
 #define MIPS_CPU_LLSC          0x00020000 /* CPU has ll/sc instructions */
-#define MIPS_CPU_INCLUSIVE_CACHES      0x00040000 /* P-cache subset enforced */
+#define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */
 #define MIPS_CPU_PREFETCH      0x00080000 /* CPU has usable prefetch */
 #define MIPS_CPU_VINT          0x00100000 /* CPU supports MIPSR2 vectored interrupts */
 #define MIPS_CPU_VEIC          0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */