#ifndef _AU1000_H_
#define _AU1000_H_
+#include <linux/config.h>
+
#ifndef _LANGUAGE_ASSEMBLY
#include <linux/delay.h>
#endif
/* SDRAM Controller */
+#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
#define MEM_SDMODE0 0xB4000000
#define MEM_SDMODE1 0xB4000004
#define MEM_SDMODE2 0xB4000008
#define MEM_SDSLEEP 0xB4000030
#define MEM_SDSMCKE 0xB4000034
+#endif
/* Static Bus Controller */
#define MEM_STCFG0 0xB4001000
#define MEM_STTIME3 0xB4001034
#define MEM_STADDR3 0xB4001038
-#ifdef CONFIG_SOC_AU1550
+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
#define MEM_STNDCTL 0xB4001100
#define MEM_STSTAT 0xB4001104
#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
/* Interrupt Numbers */
+/* Au1000 */
+#ifdef CONFIG_SOC_AU1000
#define AU1000_UART0_INT 0
#define AU1000_UART1_INT 1 /* au1000 */
#define AU1000_UART2_INT 2 /* au1000 */
-
-#define AU1000_PCI_INTA 1 /* au1500 */
-#define AU1000_PCI_INTB 2 /* au1500 */
-
#define AU1000_UART3_INT 3
-
#define AU1000_SSI0_INT 4 /* au1000 */
#define AU1000_SSI1_INT 5 /* au1000 */
-
-#define AU1000_PCI_INTC 4 /* au1500 */
-#define AU1000_PCI_INTD 5 /* au1500 */
-
#define AU1000_DMA_INT_BASE 6
#define AU1000_TOY_INT 14
#define AU1000_TOY_MATCH0_INT 15
#define AU1000_ACSYNC_INT 27
#define AU1000_MAC0_DMA_INT 28
#define AU1000_MAC1_DMA_INT 29
-#define AU1000_ETH0_IRQ AU1000_MAC0_DMA_INT
-#define AU1000_ETH1_IRQ AU1000_MAC1_DMA_INT
#define AU1000_I2S_UO_INT 30 /* au1000 */
#define AU1000_AC97C_INT 31
-#define AU1000_LAST_INTC0_INT AU1000_AC97C_INT
#define AU1000_GPIO_0 32
#define AU1000_GPIO_1 33
#define AU1000_GPIO_2 34
#define AU1000_GPIO_13 45
#define AU1000_GPIO_14 46
#define AU1000_GPIO_15 47
-
-/* Au1000 only */
#define AU1000_GPIO_16 48
#define AU1000_GPIO_17 49
#define AU1000_GPIO_18 50
#define AU1000_GPIO_30 62
#define AU1000_GPIO_31 63
-/* Au1500 only */
+#define UART0_ADDR 0xB1100000
+#define UART1_ADDR 0xB1200000
+#define UART2_ADDR 0xB1300000
+#define UART3_ADDR 0xB1400000
+
+#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
+#define USB_HOST_CONFIG 0xB017fffc
+
+#define AU1000_ETH0_BASE 0xB0500000
+#define AU1000_ETH1_BASE 0xB0510000
+#define AU1000_MAC0_ENABLE 0xB0520000
+#define AU1000_MAC1_ENABLE 0xB0520004
+#define NUM_ETH_INTERFACES 2
+#endif // CONFIG_SOC_AU1000
+
+/* Au1500 */
+#ifdef CONFIG_SOC_AU1500
+#define AU1500_UART0_INT 0
+#define AU1000_PCI_INTA 1 /* au1500 */
+#define AU1000_PCI_INTB 2 /* au1500 */
+#define AU1500_UART3_INT 3
+#define AU1000_PCI_INTC 4 /* au1500 */
+#define AU1000_PCI_INTD 5 /* au1500 */
+#define AU1000_DMA_INT_BASE 6
+#define AU1000_TOY_INT 14
+#define AU1000_TOY_MATCH0_INT 15
+#define AU1000_TOY_MATCH1_INT 16
+#define AU1000_TOY_MATCH2_INT 17
+#define AU1000_RTC_INT 18
+#define AU1000_RTC_MATCH0_INT 19
+#define AU1000_RTC_MATCH1_INT 20
+#define AU1000_RTC_MATCH2_INT 21
+#define AU1500_PCI_ERR_INT 22
+#define AU1000_USB_DEV_REQ_INT 24
+#define AU1000_USB_DEV_SUS_INT 25
+#define AU1000_USB_HOST_INT 26
+#define AU1000_ACSYNC_INT 27
+#define AU1500_MAC0_DMA_INT 28
+#define AU1500_MAC1_DMA_INT 29
+#define AU1000_AC97C_INT 31
+#define AU1000_GPIO_0 32
+#define AU1000_GPIO_1 33
+#define AU1000_GPIO_2 34
+#define AU1000_GPIO_3 35
+#define AU1000_GPIO_4 36
+#define AU1000_GPIO_5 37
+#define AU1000_GPIO_6 38
+#define AU1000_GPIO_7 39
+#define AU1000_GPIO_8 40
+#define AU1000_GPIO_9 41
+#define AU1000_GPIO_10 42
+#define AU1000_GPIO_11 43
+#define AU1000_GPIO_12 44
+#define AU1000_GPIO_13 45
+#define AU1000_GPIO_14 46
+#define AU1000_GPIO_15 47
#define AU1500_GPIO_200 48
#define AU1500_GPIO_201 49
#define AU1500_GPIO_202 50
#define AU1500_GPIO_207 62
#define AU1500_GPIO_208_215 63
-#define AU1000_MAX_INTR 63
+#define UART0_ADDR 0xB1100000
+#define UART3_ADDR 0xB1400000
-#define AU1100_SD 2
+#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
+#define USB_HOST_CONFIG 0xB017fffc
+
+#define AU1500_ETH0_BASE 0xB1500000
+#define AU1500_ETH1_BASE 0xB1510000
+#define AU1500_MAC0_ENABLE 0xB1520000
+#define AU1500_MAC1_ENABLE 0xB1520004
+#define NUM_ETH_INTERFACES 2
+#endif // CONFIG_SOC_AU1500
+
+/* Au1100 */
+#ifdef CONFIG_SOC_AU1100
+#define AU1100_UART0_INT 0
+#define AU1100_UART1_INT 1
+#define AU1100_SD_INT 2
+#define AU1100_UART3_INT 3
+#define AU1000_SSI0_INT 4
+#define AU1000_SSI1_INT 5
+#define AU1000_DMA_INT_BASE 6
+#define AU1000_TOY_INT 14
+#define AU1000_TOY_MATCH0_INT 15
+#define AU1000_TOY_MATCH1_INT 16
+#define AU1000_TOY_MATCH2_INT 17
+#define AU1000_RTC_INT 18
+#define AU1000_RTC_MATCH0_INT 19
+#define AU1000_RTC_MATCH1_INT 20
+#define AU1000_RTC_MATCH2_INT 21
+#define AU1000_IRDA_TX_INT 22
+#define AU1000_IRDA_RX_INT 23
+#define AU1000_USB_DEV_REQ_INT 24
+#define AU1000_USB_DEV_SUS_INT 25
+#define AU1000_USB_HOST_INT 26
+#define AU1000_ACSYNC_INT 27
+#define AU1100_MAC0_DMA_INT 28
#define AU1100_GPIO_208_215 29
-// Seperate defines for AU1550 SOC
-#define AU1550_UART0_INT AU1000_UART0_INT
-#define AU1550_PCI_INTA AU1000_PCI_INTA
-#define AU1550_PCI_INTB AU1000_PCI_INTB
+#define AU1100_LCD_INT 30
+#define AU1000_AC97C_INT 31
+#define AU1000_GPIO_0 32
+#define AU1000_GPIO_1 33
+#define AU1000_GPIO_2 34
+#define AU1000_GPIO_3 35
+#define AU1000_GPIO_4 36
+#define AU1000_GPIO_5 37
+#define AU1000_GPIO_6 38
+#define AU1000_GPIO_7 39
+#define AU1000_GPIO_8 40
+#define AU1000_GPIO_9 41
+#define AU1000_GPIO_10 42
+#define AU1000_GPIO_11 43
+#define AU1000_GPIO_12 44
+#define AU1000_GPIO_13 45
+#define AU1000_GPIO_14 46
+#define AU1000_GPIO_15 47
+
+#define UART0_ADDR 0xB1100000
+#define UART1_ADDR 0xB1200000
+#define UART3_ADDR 0xB1400000
+
+#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
+#define USB_HOST_CONFIG 0xB017fffc
+
+#define AU1100_ETH0_BASE 0xB0500000
+#define AU1100_MAC0_ENABLE 0xB0520000
+#define NUM_ETH_INTERFACES 1
+#endif // CONFIG_SOC_AU1100
+
+#ifdef CONFIG_SOC_AU1550
+#define AU1550_UART0_INT 0
+#define AU1550_PCI_INTA 1
+#define AU1550_PCI_INTB 2
#define AU1550_DDMA_INT 3
#define AU1550_CRYPTO_INT 4
#define AU1550_PCI_INTC 5
#define AU1550_USB_DEV_REQ_INT 24
#define AU1550_USB_DEV_SUS_INT 25
#define AU1550_USB_HOST_INT 26
+#define AU1000_USB_DEV_REQ_INT AU1550_USB_DEV_REQ_INT
+#define AU1000_USB_DEV_SUS_INT AU1550_USB_DEV_SUS_INT
+#define AU1000_USB_HOST_INT AU1550_USB_HOST_INT
#define AU1550_MAC0_DMA_INT 27
#define AU1550_MAC1_DMA_INT 28
-#define AU1550_ETH0_IRQ AU1550_MAC0_DMA_INT
-#define AU1550_ETH1_IRQ AU1550_MAC1_DMA_INT
-
+#define AU1000_GPIO_0 32
+#define AU1000_GPIO_1 33
+#define AU1000_GPIO_2 34
+#define AU1000_GPIO_3 35
+#define AU1000_GPIO_4 36
+#define AU1000_GPIO_5 37
+#define AU1000_GPIO_6 38
+#define AU1000_GPIO_7 39
+#define AU1000_GPIO_8 40
+#define AU1000_GPIO_9 41
+#define AU1000_GPIO_10 42
+#define AU1000_GPIO_11 43
+#define AU1000_GPIO_12 44
+#define AU1000_GPIO_13 45
+#define AU1000_GPIO_14 46
+#define AU1000_GPIO_15 47
#define AU1550_GPIO_200 48
#define AU1500_GPIO_201_205 49 // Logical or of GPIO201:205
#define AU1500_GPIO_16 50
#define AU1500_GPIO_207 62
#define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218
-// REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE
+#define UART0_ADDR 0xB1100000
+#define UART1_ADDR 0xB1200000
+#define UART3_ADDR 0xB1400000
+
+#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap
+#define USB_HOST_CONFIG 0xB4027ffc
+
+#define AU1550_ETH0_BASE 0xB0500000
+#define AU1550_ETH1_BASE 0xB0510000
+#define AU1550_MAC0_ENABLE 0xB0520000
+#define AU1550_MAC1_ENABLE 0xB0520004
+#define NUM_ETH_INTERFACES 2
+#endif // CONFIG_SOC_AU1550
+
+#ifdef CONFIG_SOC_AU1200
+#define AU1200_UART0_INT 0
+#define AU1200_SWT_INT 1
+#define AU1200_SD_INT 2
+#define AU1200_DDMA_INT 3
+#define AU1200_MAE_BE_INT 4
+#define AU1200_GPIO_200 5
+#define AU1200_GPIO_201 6
+#define AU1200_GPIO_202 7
+#define AU1200_UART1_INT 8
+#define AU1200_MAE_FE_INT 9
+#define AU1200_PSC0_INT 10
+#define AU1200_PSC1_INT 11
+#define AU1200_AES_INT 12
+#define AU1200_CAMERA_INT 13
+#define AU1200_TOY_INT 14
+#define AU1200_TOY_MATCH0_INT 15
+#define AU1200_TOY_MATCH1_INT 16
+#define AU1200_TOY_MATCH2_INT 17
+#define AU1200_RTC_INT 18
+#define AU1200_RTC_MATCH0_INT 19
+#define AU1200_RTC_MATCH1_INT 20
+#define AU1200_RTC_MATCH2_INT 21
+#define AU1200_NAND_INT 23
+#define AU1200_GPIO_204 24
+#define AU1200_GPIO_205 25
+#define AU1200_GPIO_206 26
+#define AU1200_GPIO_207 27
+#define AU1200_GPIO_208_215 28 // Logical OR of 208:215
+#define AU1200_USB_INT 29
+#define AU1200_LCD_INT 30
+#define AU1200_MAE_BOTH_INT 31
+#define AU1000_GPIO_0 32
+#define AU1000_GPIO_1 33
+#define AU1000_GPIO_2 34
+#define AU1000_GPIO_3 35
+#define AU1000_GPIO_4 36
+#define AU1000_GPIO_5 37
+#define AU1000_GPIO_6 38
+#define AU1000_GPIO_7 39
+#define AU1000_GPIO_8 40
+#define AU1000_GPIO_9 41
+#define AU1000_GPIO_10 42
+#define AU1000_GPIO_11 43
+#define AU1000_GPIO_12 44
+#define AU1000_GPIO_13 45
+#define AU1000_GPIO_14 46
+#define AU1000_GPIO_15 47
+#define AU1000_GPIO_16 48
+#define AU1000_GPIO_17 49
+#define AU1000_GPIO_18 50
+#define AU1000_GPIO_19 51
+#define AU1000_GPIO_20 52
+#define AU1000_GPIO_21 53
+#define AU1000_GPIO_22 54
+#define AU1000_GPIO_23 55
+#define AU1000_GPIO_24 56
+#define AU1000_GPIO_25 57
+#define AU1000_GPIO_26 58
+#define AU1000_GPIO_27 59
+#define AU1000_GPIO_28 60
+#define AU1000_GPIO_29 61
+#define AU1000_GPIO_30 62
+#define AU1000_GPIO_31 63
+
+#define UART0_ADDR 0xB1100000
+#define UART1_ADDR 0xB1200000
+
+#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap
+#define USB_HOST_CONFIG 0xB4027ffc
+
+// these are here for prototyping on au1550 (do not exist on au1200)
+#define AU1200_ETH0_BASE 0xB0500000
+#define AU1200_ETH1_BASE 0xB0510000
+#define AU1200_MAC0_ENABLE 0xB0520000
+#define AU1200_MAC1_ENABLE 0xB0520004
+#define NUM_ETH_INTERFACES 2
+#endif // CONFIG_SOC_AU1200
+
+#define AU1000_LAST_INTC0_INT 31
+#define AU1000_MAX_INTR 63
/* Programmable Counters 0 and 1 */
#define I2S_CONTROL_CE (1<<0)
/* USB Host Controller */
-// We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address
-#if defined( CONFIG_SOC_AU1550 )
-#define USB_OHCI_BASE 0x14020000
-#define USB_OHCI_LEN 0x00100000
-#define USB_HOST_CONFIG 0xB4027ffc
-#else
-#define USB_OHCI_BASE 0x10100000
#define USB_OHCI_LEN 0x00100000
-#define USB_HOST_CONFIG 0xB017fffc
-#endif
/* USB Device Controller */
#define USBD_EP0RD 0xB0200000
#define USBDEV_CE (1<<0)
/* Ethernet Controllers */
-#define AU1000_ETH0_BASE 0xB0500000
-#define AU1000_ETH1_BASE 0xB0510000
-#define AU1500_ETH0_BASE 0xB1500000
-#define AU1500_ETH1_BASE 0xB1510000
-#define AU1100_ETH0_BASE 0xB0500000
-#define AU1550_ETH0_BASE 0xB0500000
-#define AU1550_ETH1_BASE 0xB0510000
/* 4 byte offsets from AU1000_ETH_BASE */
#define MAC_CONTROL 0x0
#define MAC_VLAN2_TAG 0x24
/* Ethernet Controller Enable */
-#define AU1000_MAC0_ENABLE 0xB0520000
-#define AU1000_MAC1_ENABLE 0xB0520004
-#define AU1500_MAC0_ENABLE 0xB1520000
-#define AU1500_MAC1_ENABLE 0xB1520004
-#define AU1100_MAC0_ENABLE 0xB0520000
#define MAC_EN_CLOCK_ENABLE (1<<0)
#define MAC_EN_RESET0 (1<<1)
/* UARTS 0-3 */
-#define UART0_ADDR 0xB1100000
-#define UART1_ADDR 0xB1200000
-#define UART2_ADDR 0xB1300000
-#define UART3_ADDR 0xB1400000
#define UART_BASE UART0_ADDR
#define UART_DEBUG_BASE UART3_ADDR
#define SYS_PF_PSC1_S1 (1 << 1)
#define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
-
#define SYS_TRIOUTRD 0xB1900100
#define SYS_TRIOUTCLR 0xB1900100
#define SYS_OUTPUTRD 0xB1900108
* addresses. For PCI IO, it's simpler because we get to do the ioremap
* ourselves and then adjust the device's resources.
*/
-#define Au1500_EXT_CFG 0x600000000
-#define Au1500_EXT_CFG_TYPE1 0x680000000
-#define Au1500_PCI_IO_START 0x500000000
-#define Au1500_PCI_IO_END 0x5000FFFFF
-#define Au1500_PCI_MEM_START 0x440000000
-#define Au1500_PCI_MEM_END 0x44FFFFFFF
+#define Au1500_EXT_CFG 0x600000000ULL
+#define Au1500_EXT_CFG_TYPE1 0x680000000ULL
+#define Au1500_PCI_IO_START 0x500000000ULL
+#define Au1500_PCI_IO_END 0x5000FFFFFULL
+#define Au1500_PCI_MEM_START 0x440000000ULL
+#define Au1500_PCI_MEM_END 0x44FFFFFFFULL
#define PCI_IO_START (Au1500_PCI_IO_START + 0x1000)
#define PCI_IO_END (Au1500_PCI_IO_END)
#define PCI_FIRST_DEVFN (0<<3)
#define PCI_LAST_DEVFN (19<<3)
-#define IOPORT_RESOURCE_START 0x00001000 /* skip the legacy ide probing */
+#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
#define IOPORT_RESOURCE_END 0xffffffff
#define IOMEM_RESOURCE_START 0x10000000
#define IOMEM_RESOURCE_END 0xffffffff
#endif
-#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
-#define NUM_ETH_INTERFACES 2
-#elif defined(CONFIG_SOC_AU1100)
-#define NUM_ETH_INTERFACES 1
-#endif
/* Processor information base on prid.
* Copied from PowerPC.
*/
unsigned int prid_value;
char *cpu_name;
- unsigned int cpu_od; /* Set Config[OD] */
- unsigned int cpu_bclk; /* Enable BCLK switching */
+ unsigned char cpu_od; /* Set Config[OD] */
+ unsigned char cpu_bclk; /* Enable BCLK switching */
};
extern struct cpu_spec cpu_specs[];
extern struct cpu_spec *cur_cpu_spec[];
-
#endif
git://git.onelab.eu / linux-2.6.git / blobdiff