fedora core 6 1.2949 + vserver 2.2.0

[linux-2.6.git] / include / asm-mips / mach-generic / ide.h

diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h
index 550979a..6eba2e5 100644 (file)
--- a/include/asm-mips/mach-generic/ide.h
+++ b/include/asm-mips/mach-generic/ide.h
@@ -15,7 +15,6 @@
 
 #ifdef __KERNEL__
 
-#include <linux/config.h>
 #include <linux/pci.h>
 #include <linux/stddef.h>
 #include <asm/processor.h>
@@ -104,65 +103,107 @@ static __inline__ unsigned long ide_default_io_base(int index)
 #endif
 
 /* MIPS port and memory-mapped I/O string operations.  */
+static inline void __ide_flush_prologue(void)
+{
+#ifdef CONFIG_SMP
+       if (cpu_has_dc_aliases)
+               preempt_disable();
+#endif
+}
+
+static inline void __ide_flush_epilogue(void)
+{
+#ifdef CONFIG_SMP
+       if (cpu_has_dc_aliases)
+               preempt_enable();
+#endif
+}
 
 static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
 {
        if (cpu_has_dc_aliases) {
                unsigned long end = addr + size;
-               for (; addr < end; addr += PAGE_SIZE)
-                       flush_dcache_page(virt_to_page(addr));
+
+               while (addr < end) {
+                       local_flush_data_cache_page((void *)addr);
+                       addr += PAGE_SIZE;
+               }
        }
 }
 
+/*
+ * insw() and gang might be called with interrupts disabled, so we can't
+ * send IPIs for flushing due to the potencial of deadlocks, see the comment
+ * above smp_call_function() in arch/mips/kernel/smp.c.  We work around the
+ * problem by disabling preemption so we know we actually perform the flush
+ * on the processor that actually has the lines to be flushed which hopefully
+ * is even better for performance anyway.
+ */
 static inline void __ide_insw(unsigned long port, void *addr,
        unsigned int count)
 {
+       __ide_flush_prologue();
        insw(port, addr, count);
        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+       __ide_flush_epilogue();
 }
 
 static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
 {
+       __ide_flush_prologue();
        insl(port, addr, count);
        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+       __ide_flush_epilogue();
 }
 
 static inline void __ide_outsw(unsigned long port, const void *addr,
        unsigned long count)
 {
+       __ide_flush_prologue();
        outsw(port, addr, count);
        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+       __ide_flush_epilogue();
 }
 
 static inline void __ide_outsl(unsigned long port, const void *addr,
        unsigned long count)
 {
+       __ide_flush_prologue();
        outsl(port, addr, count);
        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+       __ide_flush_epilogue();
 }
 
 static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
 {
+       __ide_flush_prologue();
        readsw(port, addr, count);
        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+       __ide_flush_epilogue();
 }
 
 static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
 {
+       __ide_flush_prologue();
        readsl(port, addr, count);
        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+       __ide_flush_epilogue();
 }
 
 static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
 {
+       __ide_flush_prologue();
        writesw(port, addr, count);
        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+       __ide_flush_epilogue();
 }
 
 static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
 {
+       __ide_flush_prologue();
        writesl(port, addr, count);
        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+       __ide_flush_epilogue();
 }
 
 /* ide_insw calls insw, not __ide_insw.  Why? */