linux 2.6.16.38 w/ vs2.0.3-rc1

[linux-2.6.git] / include / asm-powerpc / cputable.h

diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 1ba3c99..5638518 100644 (file)
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -22,10 +22,6 @@
 #define PPC_FEATURE_BOOKE              0x00008000
 #define PPC_FEATURE_SMT                        0x00004000
 #define PPC_FEATURE_ICACHE_SNOOP       0x00002000
-#define PPC_FEATURE_ARCH_2_05          0x00001000
-
-#define PPC_FEATURE_TRUE_LE            0x00000002
-#define PPC_FEATURE_PPC_LE             0x00000001
 
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
@@ -72,13 +68,6 @@ struct cpu_spec {
        /* Processor specific oprofile operations */
        enum powerpc_oprofile_type oprofile_type;
 
-       /* Bit locations inside the mmcra change */
-       unsigned long   oprofile_mmcra_sihv;
-       unsigned long   oprofile_mmcra_sipr;
-
-       /* Bits to clear during an oprofile exception */
-       unsigned long   oprofile_mmcra_clear;
-
        /* Name of processor class, for the ELF AT_PLATFORM entry */
        char            *platform;
 };
@@ -113,34 +102,40 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
 #define CPU_FTR_NEED_COHERENT          ASM_CONST(0x0000000000020000)
 #define CPU_FTR_NO_BTIC                        ASM_CONST(0x0000000000040000)
 #define CPU_FTR_BIG_PHYS               ASM_CONST(0x0000000000080000)
-#define CPU_FTR_NODSISRALIGN           ASM_CONST(0x0000000000100000)
-#define CPU_FTR_PPC_LE                 ASM_CONST(0x0000000000200000)
-#define CPU_FTR_REAL_LE                        ASM_CONST(0x0000000000400000)
+#define CPU_FTR_NODSISRALIGN           ASM_CONST(0x0000000000100000)
 
-/*
- * Add the 64-bit processor unique features in the top half of the word;
- * on 32-bit, make the names available but defined to be 0.
- */
 #ifdef __powerpc64__
-#define LONG_ASM_CONST(x)              ASM_CONST(x)
+/* Add the 64b processor unique features in the top half of the word */
+#define CPU_FTR_SLB                    ASM_CONST(0x0000000100000000)
+#define CPU_FTR_16M_PAGE               ASM_CONST(0x0000000200000000)
+#define CPU_FTR_TLBIEL                         ASM_CONST(0x0000000400000000)
+#define CPU_FTR_NOEXECUTE              ASM_CONST(0x0000000800000000)
+#define CPU_FTR_IABR                   ASM_CONST(0x0000002000000000)
+#define CPU_FTR_MMCRA                          ASM_CONST(0x0000004000000000)
+#define CPU_FTR_CTRL                   ASM_CONST(0x0000008000000000)
+#define CPU_FTR_SMT                    ASM_CONST(0x0000010000000000)
+#define CPU_FTR_COHERENT_ICACHE        ASM_CONST(0x0000020000000000)
+#define CPU_FTR_LOCKLESS_TLBIE         ASM_CONST(0x0000040000000000)
+#define CPU_FTR_MMCRA_SIHV             ASM_CONST(0x0000080000000000)
+#define CPU_FTR_CI_LARGE_PAGE          ASM_CONST(0x0000100000000000)
+#define CPU_FTR_PAUSE_ZERO             ASM_CONST(0x0000200000000000)
 #else
-#define LONG_ASM_CONST(x)              0
+/* ensure on 32b processors the flags are available for compiling but
+ * don't do anything */
+#define CPU_FTR_SLB                    ASM_CONST(0x0)
+#define CPU_FTR_16M_PAGE               ASM_CONST(0x0)
+#define CPU_FTR_TLBIEL                         ASM_CONST(0x0)
+#define CPU_FTR_NOEXECUTE              ASM_CONST(0x0)
+#define CPU_FTR_IABR                   ASM_CONST(0x0)
+#define CPU_FTR_MMCRA                          ASM_CONST(0x0)
+#define CPU_FTR_CTRL                   ASM_CONST(0x0)
+#define CPU_FTR_SMT                    ASM_CONST(0x0)
+#define CPU_FTR_COHERENT_ICACHE        ASM_CONST(0x0)
+#define CPU_FTR_LOCKLESS_TLBIE         ASM_CONST(0x0)
+#define CPU_FTR_MMCRA_SIHV             ASM_CONST(0x0)
+#define CPU_FTR_CI_LARGE_PAGE          ASM_CONST(0x0)
 #endif
 
-#define CPU_FTR_SLB                    LONG_ASM_CONST(0x0000000100000000)
-#define CPU_FTR_16M_PAGE               LONG_ASM_CONST(0x0000000200000000)
-#define CPU_FTR_TLBIEL                 LONG_ASM_CONST(0x0000000400000000)
-#define CPU_FTR_NOEXECUTE              LONG_ASM_CONST(0x0000000800000000)
-#define CPU_FTR_IABR                   LONG_ASM_CONST(0x0000002000000000)
-#define CPU_FTR_MMCRA                  LONG_ASM_CONST(0x0000004000000000)
-#define CPU_FTR_CTRL                   LONG_ASM_CONST(0x0000008000000000)
-#define CPU_FTR_SMT                    LONG_ASM_CONST(0x0000010000000000)
-#define CPU_FTR_COHERENT_ICACHE                LONG_ASM_CONST(0x0000020000000000)
-#define CPU_FTR_LOCKLESS_TLBIE         LONG_ASM_CONST(0x0000040000000000)
-#define CPU_FTR_CI_LARGE_PAGE          LONG_ASM_CONST(0x0000100000000000)
-#define CPU_FTR_PAUSE_ZERO             LONG_ASM_CONST(0x0000200000000000)
-#define CPU_FTR_PURR                   LONG_ASM_CONST(0x0000400000000000)
-
 #ifndef __ASSEMBLY__
 
 #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
@@ -191,155 +186,153 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
                     !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
                     !defined(CONFIG_BOOKE))
 
-#define CPU_FTRS_PPC601        (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
-#define CPU_FTRS_603   (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
-           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_604   (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
-           CPU_FTR_PPC_LE)
-#define CPU_FTRS_740_NOTAU     (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-           CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_740   (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-           CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
-           CPU_FTR_PPC_LE)
-#define CPU_FTRS_750   (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-           CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
-           CPU_FTR_PPC_LE)
-#define CPU_FTRS_750FX1        (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-           CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
-           CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
-#define CPU_FTRS_750FX2        (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-           CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
-           CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
-#define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-           CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
-           CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
-#define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
-           CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
-           CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
-           CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7400_NOTAU    (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-           CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
-           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7400  (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-           CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
-           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7450_20       (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-           CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
-           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7450_21       (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_USE_TB | \
-           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-           CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
-           CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
-           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7450_23       (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_USE_TB | \
-           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-           CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
-           CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7455_1        (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_USE_TB | \
-           CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
-           CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
-           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7455_20       (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_USE_TB | \
-           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-           CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
-           CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
-           CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7455  (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_USE_TB | \
-           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-           CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
-           CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
-           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7447_10       (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_USE_TB | \
-           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-           CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
-           CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
-           CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7447  (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_USE_TB | \
-           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-           CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
-           CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
-           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_USE_TB | \
-           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-           CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
-           CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
-           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_82XX  (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
-#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
-           CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
-#define CPU_FTRS_E300  (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
-           CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
-           CPU_FTR_COMMON)
-#define CPU_FTRS_CLASSIC32     (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-           CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
-#define CPU_FTRS_8XX   (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
-#define CPU_FTRS_40X   (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-           CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_44X   (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-           CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_E200  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_E500  (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-           CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_E500_2        (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-           CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_GENERIC_32    (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
+enum {
+       CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
+       CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+           CPU_FTR_MAYBE_CAN_NAP,
+       CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
+       CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+           CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+       CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+           CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+       CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+           CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+       CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+           CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+           CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
+       CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+           CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+           CPU_FTR_NO_DPM,
+       CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+           CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+           CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+           CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
+           CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+           CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+           CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
+           CPU_FTR_MAYBE_CAN_NAP,
+       CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+           CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
+           CPU_FTR_MAYBE_CAN_NAP,
+       CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+           CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+           CPU_FTR_NEED_COHERENT,
+       CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_USE_TB |
+           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+           CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+           CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
+           CPU_FTR_NEED_COHERENT,
+       CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_USE_TB |
+           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+           CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+           CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
+       CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_USE_TB |
+           CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+           CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
+           CPU_FTR_NEED_COHERENT,
+       CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_USE_TB |
+           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+           CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+           CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
+           CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_USE_TB |
+           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+           CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+           CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+           CPU_FTR_NEED_COHERENT,
+       CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_USE_TB |
+           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+           CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+           CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+           CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
+       CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_USE_TB |
+           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+           CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+           CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+           CPU_FTR_NEED_COHERENT,
+       CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_USE_TB |
+           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+           CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+           CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+           CPU_FTR_NEED_COHERENT,
+       CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
+       CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+           CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+           CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS |
+           CPU_FTR_COMMON,
+       CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+       CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+       CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN,
+       CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+           CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
+           CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN,
+       CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+       CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+           CPU_FTR_NODSISRALIGN,
+       CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+           CPU_FTR_NODSISRALIGN,
+       CPU_FTRS_E200 = CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN,
+       CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+           CPU_FTR_NODSISRALIGN,
+       CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+           CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN,
+       CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN,
 #ifdef __powerpc64__
-#define CPU_FTRS_POWER3        (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-           CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
-#define CPU_FTRS_RS64  (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-           CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
-           CPU_FTR_MMCRA | CPU_FTR_CTRL)
-#define CPU_FTRS_POWER4        (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-           CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA)
-#define CPU_FTRS_PPC970        (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-           CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
-           CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
-#define CPU_FTRS_POWER5        (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-           CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
-           CPU_FTR_MMCRA | CPU_FTR_SMT | \
-           CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
-           CPU_FTR_PURR)
-#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-           CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
-           CPU_FTR_MMCRA | CPU_FTR_SMT | \
-           CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
-           CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE)
-#define CPU_FTRS_CELL  (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-           CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
-           CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
-           CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE)
-#define CPU_FTRS_COMPATIBLE    (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-           CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
+       CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+           CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
+       CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+           CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
+           CPU_FTR_MMCRA | CPU_FTR_CTRL,
+       CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+           CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
+       CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+           CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
+           CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
+       CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+           CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
+           CPU_FTR_MMCRA | CPU_FTR_SMT |
+           CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
+           CPU_FTR_MMCRA_SIHV,
+       CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+           CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
+           CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT |
+           CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO,
+       CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+           CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
 #endif
 
+       CPU_FTRS_POSSIBLE =
 #ifdef __powerpc64__
-#define CPU_FTRS_POSSIBLE      \
-           (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
-           CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
-           CPU_FTRS_CELL | CPU_FTR_CI_LARGE_PAGE)
+           CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
+           CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
+            CPU_FTR_CI_LARGE_PAGE |
 #else
-enum {
-       CPU_FTRS_POSSIBLE =
 #if CLASSIC_PPC
            CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
            CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
@@ -352,6 +345,12 @@ enum {
 #else
            CPU_FTRS_GENERIC_32 |
 #endif
+#ifdef CONFIG_PPC64BRIDGE
+           CPU_FTRS_POWER3_32 |
+#endif
+#ifdef CONFIG_POWER4
+           CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
+#endif
 #ifdef CONFIG_8xx
            CPU_FTRS_8XX |
 #endif
@@ -367,18 +366,14 @@ enum {
 #ifdef CONFIG_E500
            CPU_FTRS_E500 | CPU_FTRS_E500_2 |
 #endif
-           0,
-};
 #endif /* __powerpc64__ */
+           0,
 
+       CPU_FTRS_ALWAYS =
 #ifdef __powerpc64__
-#define CPU_FTRS_ALWAYS                \
-           (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
-           CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &       \
-           CPU_FTRS_CELL & CPU_FTRS_POSSIBLE)
+           CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
+           CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
 #else
-enum {
-       CPU_FTRS_ALWAYS =
 #if CLASSIC_PPC
            CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
            CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
@@ -391,6 +386,12 @@ enum {
 #else
            CPU_FTRS_GENERIC_32 &
 #endif
+#ifdef CONFIG_PPC64BRIDGE
+           CPU_FTRS_POWER3_32 &
+#endif
+#ifdef CONFIG_POWER4
+           CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
+#endif
 #ifdef CONFIG_8xx
            CPU_FTRS_8XX &
 #endif
@@ -406,9 +407,9 @@ enum {
 #ifdef CONFIG_E500
            CPU_FTRS_E500 & CPU_FTRS_E500_2 &
 #endif
+#endif /* __powerpc64__ */
            CPU_FTRS_POSSIBLE,
 };
-#endif /* __powerpc64__ */
 
 static inline int cpu_has_feature(unsigned long feature)
 {