#include <linux/config.h>
-#ifndef __ASSEMBLY__
-/*
- * Data structure defining board information maintained by the boot
- * ROM on IBM's "Ebony" evaluation board. An effort has been made to
- * keep the field names consistent with the 8xx 'bd_t' board info
- * structures.
- *
- * Ebony firmware stores MAC addresses in the F/W VPD area. The
- * firmware must store the other dynamic values in NVRAM like on
- * the previous 40x systems so they should be accessible if we
- * really want them.
- */
-typedef struct board_info {
- unsigned char bi_enetaddr[2][6]; /* EMAC addresses */
- unsigned int bi_opb_busfreq; /* OPB clock in Hz */
- int bi_iic_fast[2]; /* Use fast i2c mode */
-} bd_t;
-#endif /* __ASSEMBLY__ */
-
#ifndef NR_BOARD_IRQS
#define NR_BOARD_IRQS 0
#endif
*/
#ifdef CONFIG_440GX
+/* CPRs */
+#define DCRN_CPR_CONFIG_ADDR 0xc
+#define DCRN_CPR_CONFIG_DATA 0xd
+
+#define DCRN_CPR_CLKUPD 0x0020
+#define DCRN_CPR_PLLC 0x0040
+#define DCRN_CPR_PLLD 0x0060
+#define DCRN_CPR_PRIMAD 0x0080
+#define DCRN_CPR_PRIMBD 0x00a0
+#define DCRN_CPR_OPBD 0x00c0
+#define DCRN_CPR_PERD 0x00e0
+#define DCRN_CPR_MALD 0x0100
+
+/* CPRs read/write helper macros */
+#define CPR_READ(offset) ({\
+ mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
+ mfdcr(DCRN_CPR_CONFIG_DATA);})
+#define CPR_WRITE(offset, data) ({\
+ mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
+ mtdcr(DCRN_CPR_CONFIG_DATA, data);})
+
/* SDRs */
#define DCRN_SDR_CONFIG_ADDR 0xe
#define DCRN_SDR_CONFIG_DATA 0xf
#define DCRN_SDR_PFC0 0x4100
#define DCRN_SDR_PFC1 0x4101
+#define DCRN_SDR_PFC1_EPS 0x1c000000
+#define DCRN_SDR_PFC1_EPS_SHIFT 26
+#define DCRN_SDR_PFC1_RMII 0x02000000
#define DCRN_SDR_MFR 0x4300
#define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
#define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */
#define DCRN_SDR_MFR_E3TXFH 0x00000004
#define DCRN_SDR_MFR_E3RXFL 0x00000002
#define DCRN_SDR_MFR_E3RXFH 0x00000001
+#define DCRN_SDR_UART0 0x0120
+#define DCRN_SDR_UART1 0x0121
/* SDR read/write helper macros */
#define SDR_READ(offset) ({\
/* UIC */
#define DCRN_UIC0_BASE 0xc0
#define DCRN_UIC1_BASE 0xd0
+#define DCRN_UIC2_BASE 0x210
+#define DCRN_UICB_BASE 0x200
#define UIC0 DCRN_UIC0_BASE
#define UIC1 DCRN_UIC1_BASE
+#define UIC2 DCRN_UIC2_BASE
+#define UICB DCRN_UICB_BASE
#define DCRN_UIC_SR(base) (base + 0x0)
#define DCRN_UIC_ER(base) (base + 0x2)
#define DCRN_UIC_VR(base) (base + 0x7)
#define DCRN_UIC_VCR(base) (base + 0x8)
-#define UIC0_UIC1NC 30 /* UIC1 non-critical interrupt */
-#define UIC0_UIC1CR 31 /* UIC1 critical interrupt */
+#define UIC0_UIC1NC 30 /* UIC1 non-critical interrupt */
+#define UIC0_UIC1CR 31 /* UIC1 critical interrupt */
+
+#define UICB_UIC0NC 0x40000000
+#define UICB_UIC1NC 0x10000000
+#define UICB_UIC2NC 0x04000000
/* 440GP MAL DCRs */
#define DCRN_MALCR(base) (base + 0x0) /* Configuration */
#define PPC44x_MEM_SIZE_256M 0x10000000
#define PPC44x_MEM_SIZE_512M 0x20000000
+#ifdef CONFIG_440GX
+/* Internal SRAM Controller */
+#define DCRN_SRAM0_SB0CR 0x020
+#define DCRN_SRAM0_SB1CR 0x021
+#define DCRN_SRAM0_SB2CR 0x022
+#define DCRN_SRAM0_SB3CR 0x023
+#define SRAM_SBCR_BAS0 0x80000000
+#define SRAM_SBCR_BAS1 0x80010000
+#define SRAM_SBCR_BAS2 0x80020000
+#define SRAM_SBCR_BAS3 0x80030000
+#define SRAM_SBCR_BU_MASK 0x00000180
+#define SRAM_SBCR_BS_64KB 0x00000800
+#define SRAM_SBCR_BU_RO 0x00000080
+#define SRAM_SBCR_BU_RW 0x00000180
+#define DCRN_SRAM0_BEAR 0x024
+#define DCRN_SRAM0_BESR0 0x025
+#define DCRN_SRAM0_BESR1 0x026
+#define DCRN_SRAM0_PMEG 0x027
+#define DCRN_SRAM0_CID 0x028
+#define DCRN_SRAM0_REVID 0x029
+#define DCRN_SRAM0_DPC 0x02a
+#define SRAM_DPC_ENABLE 0x80000000
+
+/* L2 Cache Controller */
+#define DCRN_L2C0_CFG 0x030
+#define L2C_CFG_L2M 0x80000000
+#define L2C_CFG_ICU 0x40000000
+#define L2C_CFG_DCU 0x20000000
+#define L2C_CFG_DCW_MASK 0x1e000000
+#define L2C_CFG_TPC 0x01000000
+#define L2C_CFG_CPC 0x00800000
+#define L2C_CFG_FRAN 0x00200000
+#define L2C_CFG_SS_MASK 0x00180000
+#define L2C_CFG_SS_256 0x00000000
+#define L2C_CFG_CPIM 0x00040000
+#define L2C_CFG_TPIM 0x00020000
+#define L2C_CFG_LIM 0x00010000
+#define L2C_CFG_PMUX_MASK 0x00007000
+#define L2C_CFG_PMUX_SNP 0x00000000
+#define L2C_CFG_PMUX_IF 0x00001000
+#define L2C_CFG_PMUX_DF 0x00002000
+#define L2C_CFG_PMUX_DS 0x00003000
+#define L2C_CFG_PMIM 0x00000800
+#define L2C_CFG_TPEI 0x00000400
+#define L2C_CFG_CPEI 0x00000200
+#define L2C_CFG_NAM 0x00000100
+#define L2C_CFG_SMCM 0x00000080
+#define L2C_CFG_NBRM 0x00000040
+#define DCRN_L2C0_CMD 0x031
+#define L2C_CMD_CLR 0x80000000
+#define L2C_CMD_DIAG 0x40000000
+#define L2C_CMD_INV 0x20000000
+#define L2C_CMD_CCP 0x10000000
+#define L2C_CMD_CTE 0x08000000
+#define L2C_CMD_STRC 0x04000000
+#define L2C_CMD_STPC 0x02000000
+#define L2C_CMD_RPMC 0x01000000
+#define L2C_CMD_HCC 0x00800000
+#define DCRN_L2C0_ADDR 0x032
+#define DCRN_L2C0_DATA 0x033
+#define DCRN_L2C0_SR 0x034
+#define L2C_SR_CC 0x80000000
+#define L2C_SR_CPE 0x40000000
+#define L2C_SR_TPE 0x20000000
+#define L2C_SR_LRU 0x10000000
+#define L2C_SR_PCS 0x08000000
+#define DCRN_L2C0_REVID 0x035
+#define DCRN_L2C0_SNP0 0x036
+#define DCRN_L2C0_SNP1 0x037
+#define L2C_SNP_BA_MASK 0xffff0000
+#define L2C_SNP_SSR_MASK 0x0000f000
+#define L2C_SNP_SSR_32G 0x0000f000
+#define L2C_SNP_ESR 0x00000800
+#endif /* CONFIG_440GX */
+
/*
* PCI-X definitions
*/
#define IIC_CLOCK 50
#undef NR_UICS
+#ifdef CONFIG_440GX
+#define NR_UICS 3
+#else
#define NR_UICS 2
+#endif
#define UIC_CASCADE_MASK 0x0003 /* bits 30 & 31 */
#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
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