VServer 1.9.2 (patch-2.6.8.1-vs1.9.2.diff)

[linux-2.6.git] / include / asm-ppc / reg.h

diff --git a/include/asm-ppc/reg.h b/include/asm-ppc/reg.h
index e1defae..73eab45 100644 (file)
--- a/include/asm-ppc/reg.h
+++ b/include/asm-ppc/reg.h
@@ -174,6 +174,7 @@
 
 #define SPRN_HID1      0x3F1           /* Hardware Implementation Register 1 */
 #define HID1_EMCP      (1<<31)         /* 7450 Machine Check Pin Enable */
+#define HID1_DFS       (1<<22)         /* 7447A Dynamic Frequency Scaling */
 #define HID1_PC0       (1<<16)         /* 7450 PLL_CFG[0] */
 #define HID1_PC1       (1<<15)         /* 7450 PLL_CFG[1] */
 #define HID1_PC2       (1<<14)         /* 7450 PLL_CFG[2] */
@@ -294,6 +295,9 @@
 #define SPRN_SPRG7     0x117   /* Special Purpose Register General 7 */
 #define SPRN_SRR0      0x01A   /* Save/Restore Register 0 */
 #define SPRN_SRR1      0x01B   /* Save/Restore Register 1 */
+#ifndef SPRN_SVR
+#define SPRN_SVR       0x11E   /* System Version Register */
+#endif
 #define SPRN_THRM1     0x3FC           /* Thermal Management Register 1 */
 /* these bits were defined in inverted endian sense originally, ugh, confusing */
 #define THRM1_TIN      (1 << 31)
@@ -346,7 +350,7 @@
 #define DBAT6U SPRN_DBAT6U     /* Data BAT 6 Upper Register */
 #define DBAT7L SPRN_DBAT7L     /* Data BAT 7 Lower Register */
 #define DBAT7U SPRN_DBAT7U     /* Data BAT 7 Upper Register */
-#define DEC    SPRN_DEC        /* Decrement Register */
+//#define DEC  SPRN_DEC        /* Decrement Register */
 #define DMISS  SPRN_DMISS      /* Data TLB Miss Register */
 #define DSISR  SPRN_DSISR      /* Data Storage Interrupt Status Register */
 #define EAR    SPRN_EAR        /* External Address Register */
@@ -376,9 +380,9 @@
 #define IMMR   SPRN_IMMR       /* PPC 860/821 Internal Memory Map Register */
 #define L2CR   SPRN_L2CR       /* Classic PPC L2 cache control register */
 #define L3CR   SPRN_L3CR       /* PPC 745x L3 cache control register */
-#define LR     SPRN_LR
+//#define LR   SPRN_LR
 #define PVR    SPRN_PVR        /* Processor Version */
-#define RPA    SPRN_RPA        /* Required Physical Address Register */
+//#define RPA  SPRN_RPA        /* Required Physical Address Register */
 #define SDR1   SPRN_SDR1       /* MMU hash base register */
 #define SPR0   SPRN_SPRG0      /* Supervisor Private Registers */
 #define SPR1   SPRN_SPRG1
@@ -400,6 +404,7 @@
 #define SRR1   SPRN_SRR1       /* Save and Restore Register 1 */
 #define SRR2   SPRN_SRR2       /* Save and Restore Register 2 */
 #define SRR3   SPRN_SRR3       /* Save and Restore Register 3 */
+#define SVR    SPRN_SVR        /* System Version Register */
 #define ICTC   SPRN_ICTC       /* Instruction Cache Throttling Control Reg */
 #define THRM1  SPRN_THRM1      /* Thermal Management Register 1 */
 #define THRM2  SPRN_THRM2      /* Thermal Management Register 2 */
@@ -462,6 +467,8 @@
 #define PVR_7400       0x000C0000
 #define PVR_7410       0x800C0000
 #define PVR_7450       0x80000000
+#define PVR_8540       0x80200000
+#define PVR_8560       0x80200000
 /*
  * For the 8xx processors, all of them report the same PVR family for
  * the PowerPC core. The various versions of these processors must be
@@ -476,6 +483,13 @@
 #define PVR_8245       0x80811014
 #define PVR_8260       PVR_8240
 
+/* System Version Numbers */
+#define SVR_8540       0x80300000
+#define SVR_8541E      0x807A0000
+#define SVR_8555E      0x80790000
+#define SVR_8560       0x80700000
+
+#if 0
 /* Segment Registers */
 #define SR0    0
 #define SR1    1
@@ -493,6 +507,7 @@
 #define SR13   13
 #define SR14   14
 #define SR15   15
+#endif
 
 /* Macros for setting and retrieving special purpose registers */
 #ifndef __ASSEMBLY__