patch-2_6_7-vs1_9_1_12

[linux-2.6.git] / include / asm-sparc / pgtsrmmu.h

diff --git a/include/asm-sparc/pgtsrmmu.h b/include/asm-sparc/pgtsrmmu.h
index e0cc31a..3107339 100644 (file)
--- a/include/asm-sparc/pgtsrmmu.h
+++ b/include/asm-sparc/pgtsrmmu.h
@@ -17,10 +17,10 @@
 #define SRMMU_MAX_CONTEXTS     65536
 
 /* PMD_SHIFT determines the size of the area a second-level page table entry can map */
-#define SRMMU_PMD_SHIFT         18
-#define SRMMU_PMD_SIZE          (1UL << SRMMU_PMD_SHIFT)
-#define SRMMU_PMD_MASK          (~(SRMMU_PMD_SIZE-1))
-/* #define SRMMU_PMD_ALIGN(addr)   (((addr)+SRMMU_PMD_SIZE-1)&SRMMU_PMD_MASK) */
+#define SRMMU_REAL_PMD_SHIFT           18
+#define SRMMU_REAL_PMD_SIZE            (1UL << SRMMU_REAL_PMD_SHIFT)
+#define SRMMU_REAL_PMD_MASK            (~(SRMMU_REAL_PMD_SIZE-1))
+#define SRMMU_REAL_PMD_ALIGN(__addr)   (((__addr)+SRMMU_REAL_PMD_SIZE-1)&SRMMU_REAL_PMD_MASK)
 
 /* PGDIR_SHIFT determines what a third-level page table entry can map */
 #define SRMMU_PGDIR_SHIFT       24
@@ -28,13 +28,13 @@
 #define SRMMU_PGDIR_MASK        (~(SRMMU_PGDIR_SIZE-1))
 #define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
 
-#define SRMMU_PTRS_PER_PTE      64
-#define SRMMU_PTRS_PER_PMD      64
-#define SRMMU_PTRS_PER_PGD      256
+#define SRMMU_REAL_PTRS_PER_PTE        64
+#define SRMMU_REAL_PTRS_PER_PMD        64
+#define SRMMU_PTRS_PER_PGD     256
 
-#define SRMMU_PTE_TABLE_SIZE    0x100 /* 64 entries, 4 bytes a piece */
-#define SRMMU_PMD_TABLE_SIZE    0x100 /* 64 entries, 4 bytes a piece */
-#define SRMMU_PGD_TABLE_SIZE    0x400 /* 256 entries, 4 bytes a piece */
+#define SRMMU_REAL_PTE_TABLE_SIZE      (SRMMU_REAL_PTRS_PER_PTE*4)
+#define SRMMU_PMD_TABLE_SIZE           (SRMMU_REAL_PTRS_PER_PMD*4)
+#define SRMMU_PGD_TABLE_SIZE           (SRMMU_PTRS_PER_PGD*4)
 
 /*
  * To support pagetables in highmem, Linux introduces APIs which
@@ -44,16 +44,11 @@
  * software tables.
  *
  * PMD_SHIFT determines the size of the area a second-level page table entry
- * can map, and our pmd_t is 16 times larger than normal.
+ * can map, and our pmd_t is 16 times larger than normal.  The values which
+ * were once defined here are now generic for 4c and srmmu, so they're
+ * found in pgtable.h.
  */
-#define SRMMU_PTRS_PER_PTE_SOFT        (PAGE_SIZE/4)   /* 16 hard tables per 4K page */
-#define SRMMU_PTRS_PER_PMD_SOFT        4       /* Each pmd_t contains 16 hard PTPs */
-#define SRMMU_PTE_SZ_SOFT       PAGE_SIZE      /* same as above, in bytes */
-
-#define SRMMU_PMD_SHIFT_SOFT   22
-#define SRMMU_PMD_SIZE_SOFT    (1UL << SRMMU_PMD_SHIFT_SOFT)
-#define SRMMU_PMD_MASK_SOFT    (~(SRMMU_PMD_SIZE_SOFT-1))
-#define SRMMU_PMD_ALIGN_SOFT(addr)  (((addr)+SRMMU_PMD_SIZE_SOFT-1)&SRMMU_PMD_MASK_SOFT)
+#define SRMMU_PTRS_PER_PMD     4
 
 /* Definition of the values in the ET field of PTD's and PTE's */
 #define SRMMU_ET_MASK         0x3
@@ -255,7 +250,7 @@ extern __inline__ void srmmu_flush_tlb_region(unsigned long addr)
 
 extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr)
 {
-       addr &= SRMMU_PMD_MASK;
+       addr &= SRMMU_REAL_PMD_MASK;
        __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
                             "r" (addr | 0x100), /* Flush TLB segment.. */
                             "i" (ASI_M_FLUSH_PROBE) : "memory");