--- /dev/null
+commit cf2eac8c7bef33a306a4437d7e385d22beb71c86
+Author: S.Çağlar Onur <caglar@cs.princeton.edu>
+Date: Tue Mar 16 21:52:02 2010 -0400
+
+ linux-2.6-810-ich10.patch
+
+diff --git a/arch/i386/pci/irq.c b/arch/i386/pci/irq.c
+index f2cb942..8e92187 100644
+--- a/arch/i386/pci/irq.c
++++ b/arch/i386/pci/irq.c
+@@ -549,11 +549,24 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route
+ case PCI_DEVICE_ID_INTEL_ICH9_3:
+ case PCI_DEVICE_ID_INTEL_ICH9_4:
+ case PCI_DEVICE_ID_INTEL_ICH9_5:
++ case PCI_DEVICE_ID_INTEL_ICH10_0:
++ case PCI_DEVICE_ID_INTEL_ICH10_1:
++ case PCI_DEVICE_ID_INTEL_ICH10_2:
++ case PCI_DEVICE_ID_INTEL_ICH10_3:
+ r->name = "PIIX/ICH";
+ r->get = pirq_piix_get;
+ r->set = pirq_piix_set;
+ return 1;
+ }
++
++ if ((device >= PCI_DEVICE_ID_INTEL_PCH_LPC_MIN) &&
++ (device <= PCI_DEVICE_ID_INTEL_PCH_LPC_MAX)) {
++ r->name = "PIIX/ICH";
++ r->get = pirq_piix_get;
++ r->set = pirq_piix_set;
++ return 1;
++ }
++
+ return 0;
+ }
+
+diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
+index e722f83..260f54c 100644
+--- a/drivers/ata/ahci.c
++++ b/drivers/ata/ahci.c
+@@ -392,6 +392,10 @@ static const struct pci_device_id ahci_pci_tbl[] = {
+ { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
+ { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
+ { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
++ { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
++ { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
++ { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
++ { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
+
+ /* JMicron 360/1/3/5/6, match class to avoid IDE function */
+ { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
+index 5a148bd..e305aac 100644
+--- a/drivers/ata/ata_piix.c
++++ b/drivers/ata/ata_piix.c
+@@ -104,6 +104,7 @@ enum {
+ PIIX_FLAG_SCR = (1 << 26), /* SCR available */
+ PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
+ PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
++ PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
+
+ PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
+ PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
+@@ -129,6 +130,7 @@ enum {
+ ich6m_sata_ahci = 8,
+ ich8_sata_ahci = 9,
+ piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
++ ich8_2port_sata = 11,
+
+ /* constants for mapping table */
+ P0 = 0, /* port 0 */
+@@ -245,6 +247,18 @@ static const struct pci_device_id piix_pci_tbl[] = {
+ { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
+ /* SATA Controller IDE (ICH9M) */
+ { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
++ /* SATA Controller IDE (ICH10) */
++ { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
++ /* SATA Controller IDE (ICH10) */
++ { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
++ /* SATA Controller IDE (ICH10) */
++ { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
++ /* SATA Controller IDE (ICH10) */
++ { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
++ /* SATA Controller IDE (PCH) */
++ { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
++ /* SATA Controller IDE (PCH) */
++ { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
+
+ { } /* terminate list */
+ };
+@@ -433,11 +447,24 @@ static const struct piix_map_db ich8_map_db = {
+ },
+ };
+
++static const struct piix_map_db ich8_2port_map_db = {
++ .mask = 0x3,
++ .port_enable = 0x3,
++ .map = {
++ /* PM PS SM SS MAP */
++ { P0, NA, P1, NA }, /* 00b */
++ { RV, RV, RV, RV }, /* 01b */
++ { RV, RV, RV, RV }, /* 10b */
++ { RV, RV, RV, RV },
++ },
++};
++
+ static const struct piix_map_db *piix_map_db_table[] = {
+ [ich5_sata] = &ich5_map_db,
+ [ich6_sata] = &ich6_map_db,
+ [ich6_sata_ahci] = &ich6_map_db,
+ [ich6m_sata_ahci] = &ich6m_map_db,
++ [ich8_2port_sata] = &ich8_2port_map_db,
+ [ich8_sata_ahci] = &ich8_map_db,
+ };
+
+@@ -552,6 +579,16 @@ static struct ata_port_info piix_port_info[] = {
+ .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
+ .port_ops = &piix_pata_ops,
+ },
++
++ [ich8_2port_sata] =
++ {
++ .sht = &piix_sht,
++ .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
++ .pio_mask = ATA_PIO4,
++ .mwdma_mask = ATA_MWDMA2,
++ .udma_mask = ATA_UDMA6,
++ .port_ops = &piix_sata_ops,
++ },
+ };
+
+ static struct pci_bits piix_enable_bits[] = {
+diff --git a/include/linux/ata.h b/include/linux/ata.h
+index 703febb..a420021 100644
+--- a/include/linux/ata.h
++++ b/include/linux/ata.h
+@@ -64,6 +64,28 @@ enum {
+ ATA_ID_PROD_LEN = 40,
+
+ ATA_PCI_CTL_OFS = 2,
++
++ ATA_PIO0 = (1 << 0),
++ ATA_PIO1 = ATA_PIO0 | (1 << 1),
++ ATA_PIO2 = ATA_PIO1 | (1 << 2),
++ ATA_PIO3 = ATA_PIO2 | (1 << 3),
++ ATA_PIO4 = ATA_PIO3 | (1 << 4),
++ ATA_PIO5 = ATA_PIO4 | (1 << 5),
++ ATA_PIO6 = ATA_PIO5 | (1 << 6),
++
++ ATA_SWDMA0 = (1 << 0),
++ ATA_SWDMA1 = ATA_SWDMA0 | (1 << 1),
++ ATA_SWDMA2 = ATA_SWDMA1 | (1 << 2),
++
++ ATA_SWDMA2_ONLY = (1 << 2),
++
++ ATA_MWDMA0 = (1 << 0),
++ ATA_MWDMA1 = ATA_MWDMA0 | (1 << 1),
++ ATA_MWDMA2 = ATA_MWDMA1 | (1 << 2),
++
++ ATA_MWDMA12_ONLY = (1 << 1) | (1 << 2),
++ ATA_MWDMA2_ONLY = (1 << 2),
++
+ ATA_UDMA0 = (1 << 0),
+ ATA_UDMA1 = ATA_UDMA0 | (1 << 1),
+ ATA_UDMA2 = ATA_UDMA1 | (1 << 2),
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index c6c9d48..5505b33 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2301,6 +2301,15 @@
+ #define PCI_DEVICE_ID_INTEL_MCH_PC 0x3599
+ #define PCI_DEVICE_ID_INTEL_MCH_PC1 0x359a
+ #define PCI_DEVICE_ID_INTEL_E7525_MCH 0x359e
++#define PCI_DEVICE_ID_INTEL_ICH10_0 0x3a14
++#define PCI_DEVICE_ID_INTEL_ICH10_1 0x3a16
++#define PCI_DEVICE_ID_INTEL_ICH10_2 0x3a18
++#define PCI_DEVICE_ID_INTEL_ICH10_3 0x3a1a
++#define PCI_DEVICE_ID_INTEL_ICH10_4 0x3a30
++#define PCI_DEVICE_ID_INTEL_ICH10_5 0x3a60
++#define PCI_DEVICE_ID_INTEL_PCH_LPC_MIN 0x3b00
++#define PCI_DEVICE_ID_INTEL_PCH_LPC_MAX 0x3b1f
++#define PCI_DEVICE_ID_INTEL_PCH_SMBUS 0x3b30
+ #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
+ #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
+ #define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020