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13 <h1>CodeMirror: Verilog mode</h1>
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16 /* Verilog demo code */
26 // m_in contains data that passes through this block with no change.
27 input wire [MWIDTH-1:0] m_in,
28 // The twiddle factor.
29 input wire signed [WIDTH-1:0] w,
31 input wire signed [WIDTH-1:0] xa,
33 input wire signed [WIDTH-1:0] xb,
34 // Set to 1 when new data is present on inputs.
36 // delayed version of m_in.
37 output reg [MWIDTH-1:0] m_out,
40 output wire signed [WIDTH-1:0] ya,
41 output wire signed [WIDTH-1:0] yb,
46 // Set wire to the real and imag parts for convenience.
47 wire signed [WIDTH/2-1:0] xa_re;
48 wire signed [WIDTH/2-1:0] xa_im;
49 assign xa_re = xa[WIDTH-1:WIDTH/2];
50 assign xa_im = xa[WIDTH/2-1:0];
51 wire signed [WIDTH/2-1: 0] ya_re;
52 wire signed [WIDTH/2-1: 0] ya_im;
53 assign ya = {ya_re, ya_im};
54 wire signed [WIDTH/2-1: 0] yb_re;
55 wire signed [WIDTH/2-1: 0] yb_im;
56 assign yb = {yb_re, yb_im};
59 reg signed [WIDTH/2-1:0] xa_re_z;
60 reg signed [WIDTH/2-1:0] xa_im_z;
61 // Output of multiplier
62 wire signed [WIDTH-1:0] xbw;
63 wire signed [WIDTH/2-1:0] xbw_re;
64 wire signed [WIDTH/2-1:0] xbw_im;
65 assign xbw_re = xbw[WIDTH-1:WIDTH/2];
66 assign xbw_im = xbw[WIDTH/2-1:0];
68 // I don't think we should get overflow here because of the
69 // size of the twiddle factors.
70 // If we do testing should catch it.
71 assign ya_re = xa_re_z + xbw_re;
72 assign ya_im = xa_im_z + xbw_im;
73 assign yb_re = xa_re_z - xbw_re;
74 assign yb_im = xa_im_z - xbw_im;
76 // Create the multiply module.
77 multiply_complex #(WIDTH) multiply_complex_0
85 always @ (posedge clk)
94 // Set delay for x_nd_old and m.
109 var editor = CodeMirror.fromTextArea(document.getElementById("code"), {
111 mode: "text/x-verilog"
115 <p>Simple mode that tries to handle Verilog-like languages as well as it
116 can. Takes one configuration parameters: <code>keywords</code>, an
117 object whose property names are the keywords in the language.</p>
119 <p><strong>MIME types defined:</strong> <code>text/x-verilog</code> (Verilog code).</p>