added refresh right to slice

diff --git a/plc/registry.py b/plc/registry.py
index b722c35..53581d4 100644 (file)
--- a/plc/registry.py
+++ b/plc/registry.py
@@ -677,6 +677,7 @@ class Registry(GeniServer):
         elif type == "ma":
             rl.add("authority")
         elif type == "slice":
+            rl.add("refresh")
             rl.add("embed")
             rl.add("bind")
             rl.add("control")