1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 #include <linux/kernel.h>
7 #include <linux/sched.h>
9 #include <linux/pagemap.h>
10 #include <linux/threads.h>
11 #include <linux/smp.h>
12 #include <linux/smp_lock.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
19 #include <linux/seq_file.h>
20 #include <linux/cache.h>
21 #include <linux/jiffies.h>
22 #include <linux/profile.h>
25 #include <asm/ptrace.h>
26 #include <asm/atomic.h>
27 #include <asm/tlbflush.h>
28 #include <asm/mmu_context.h>
29 #include <asm/cpudata.h>
33 #include <asm/pgtable.h>
34 #include <asm/oplib.h>
35 #include <asm/uaccess.h>
36 #include <asm/timer.h>
37 #include <asm/starfire.h>
40 extern int linux_num_cpus;
41 extern void calibrate_delay(void);
43 /* Please don't make this stuff initdata!!! --DaveM */
44 static unsigned char boot_cpu_id;
46 cpumask_t cpu_online_map = CPU_MASK_NONE;
47 cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
48 static cpumask_t smp_commenced_mask;
49 static cpumask_t cpu_callout_map;
51 void smp_info(struct seq_file *m)
55 seq_printf(m, "State:\n");
56 for (i = 0; i < NR_CPUS; i++) {
59 "CPU%d:\t\tonline\n", i);
63 void smp_bogo(struct seq_file *m)
67 for (i = 0; i < NR_CPUS; i++)
70 "Cpu%dBogo\t: %lu.%02lu\n"
71 "Cpu%dClkTck\t: %016lx\n",
72 i, cpu_data(i).udelay_val / (500000/HZ),
73 (cpu_data(i).udelay_val / (5000/HZ)) % 100,
74 i, cpu_data(i).clock_tick);
77 void __init smp_store_cpu_info(int id)
81 /* multiplier and counter set by
82 smp_setup_percpu_timer() */
83 cpu_data(id).udelay_val = loops_per_jiffy;
85 cpu_find_by_mid(id, &cpu_node);
86 cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
87 "clock-frequency", 0);
89 cpu_data(id).pgcache_size = 0;
90 cpu_data(id).pte_cache[0] = NULL;
91 cpu_data(id).pte_cache[1] = NULL;
92 cpu_data(id).pgdcache_size = 0;
93 cpu_data(id).pgd_cache = NULL;
94 cpu_data(id).idle_volume = 1;
97 static void smp_setup_percpu_timer(void);
99 static volatile unsigned long callin_flag = 0;
101 extern void inherit_locked_prom_mappings(int save_p);
103 void __init smp_callin(void)
105 int cpuid = hard_smp_processor_id();
106 extern int bigkernel;
107 extern unsigned long kern_locked_tte_data;
110 prom_dtlb_load(sparc64_highest_locked_tlbent()-1,
111 kern_locked_tte_data + 0x400000, KERNBASE + 0x400000);
112 prom_itlb_load(sparc64_highest_locked_tlbent()-1,
113 kern_locked_tte_data + 0x400000, KERNBASE + 0x400000);
116 inherit_locked_prom_mappings(0);
120 smp_setup_percpu_timer();
125 smp_store_cpu_info(cpuid);
127 __asm__ __volatile__("membar #Sync\n\t"
128 "flush %%g6" : : : "memory");
130 /* Clear this or we will die instantly when we
131 * schedule back to this idler...
133 clear_thread_flag(TIF_NEWCHILD);
135 /* Attach to the address space of init_task. */
136 atomic_inc(&init_mm.mm_count);
137 current->active_mm = &init_mm;
139 while (!cpu_isset(cpuid, smp_commenced_mask))
142 cpu_set(cpuid, cpu_online_map);
147 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
148 panic("SMP bolixed\n");
151 static unsigned long current_tick_offset;
153 /* This tick register synchronization scheme is taken entirely from
154 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
156 * The only change I've made is to rework it so that the master
157 * initiates the synchonization instead of the slave. -DaveM
161 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
163 #define NUM_ROUNDS 64 /* magic value */
164 #define NUM_ITERS 5 /* likewise */
166 static spinlock_t itc_sync_lock = SPIN_LOCK_UNLOCKED;
167 static unsigned long go[SLAVE + 1];
169 #define DEBUG_TICK_SYNC 0
171 static inline long get_delta (long *rt, long *master)
173 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
174 unsigned long tcenter, t0, t1, tm;
177 for (i = 0; i < NUM_ITERS; i++) {
178 t0 = tick_ops->get_tick();
180 membar("#StoreLoad");
181 while (!(tm = go[SLAVE]))
184 membar("#StoreStore");
185 t1 = tick_ops->get_tick();
187 if (t1 - t0 < best_t1 - best_t0)
188 best_t0 = t0, best_t1 = t1, best_tm = tm;
191 *rt = best_t1 - best_t0;
192 *master = best_tm - best_t0;
194 /* average best_t0 and best_t1 without overflow: */
195 tcenter = (best_t0/2 + best_t1/2);
196 if (best_t0 % 2 + best_t1 % 2 == 2)
198 return tcenter - best_tm;
201 void smp_synchronize_tick_client(void)
203 long i, delta, adj, adjust_latency = 0, done = 0;
204 unsigned long flags, rt, master_time_stamp, bound;
207 long rt; /* roundtrip time */
208 long master; /* master's timestamp */
209 long diff; /* difference between midpoint and master's timestamp */
210 long lat; /* estimate of itc adjustment latency */
219 local_irq_save(flags);
221 for (i = 0; i < NUM_ROUNDS; i++) {
222 delta = get_delta(&rt, &master_time_stamp);
224 done = 1; /* let's lock on to this... */
230 adjust_latency += -delta;
231 adj = -delta + adjust_latency/4;
235 tick_ops->add_tick(adj, current_tick_offset);
239 t[i].master = master_time_stamp;
241 t[i].lat = adjust_latency/4;
245 local_irq_restore(flags);
248 for (i = 0; i < NUM_ROUNDS; i++)
249 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
250 t[i].rt, t[i].master, t[i].diff, t[i].lat);
253 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
254 "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
257 static void smp_start_sync_tick_client(int cpu);
259 static void smp_synchronize_one_tick(int cpu)
261 unsigned long flags, i;
265 smp_start_sync_tick_client(cpu);
267 /* wait for client to be ready */
271 /* now let the client proceed into his loop */
273 membar("#StoreLoad");
275 spin_lock_irqsave(&itc_sync_lock, flags);
277 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
281 membar("#StoreStore");
282 go[SLAVE] = tick_ops->get_tick();
283 membar("#StoreLoad");
286 spin_unlock_irqrestore(&itc_sync_lock, flags);
289 extern unsigned long sparc64_cpu_startup;
291 /* The OBP cpu startup callback truncates the 3rd arg cookie to
292 * 32-bits (I think) so to be safe we have it read the pointer
293 * contained here so we work on >4GB machines. -DaveM
295 static struct thread_info *cpu_new_thread = NULL;
297 static int __devinit smp_boot_one_cpu(unsigned int cpu)
299 unsigned long entry =
300 (unsigned long)(&sparc64_cpu_startup);
301 unsigned long cookie =
302 (unsigned long)(&cpu_new_thread);
303 struct task_struct *p;
304 int timeout, ret, cpu_node;
308 cpu_new_thread = p->thread_info;
309 cpu_set(cpu, cpu_callout_map);
311 cpu_find_by_mid(cpu, &cpu_node);
312 prom_startcpu(cpu_node, entry, cookie);
314 for (timeout = 0; timeout < 5000000; timeout++) {
322 printk("Processor %d is stuck.\n", cpu);
323 cpu_clear(cpu, cpu_callout_map);
326 cpu_new_thread = NULL;
331 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
336 if (this_is_starfire) {
337 /* map to real upaid */
338 cpu = (((cpu & 0x3c) << 1) |
339 ((cpu & 0x40) >> 4) |
343 target = (cpu << 14) | 0x70;
345 /* Ok, this is the real Spitfire Errata #54.
346 * One must read back from a UDB internal register
347 * after writes to the UDB interrupt dispatch, but
348 * before the membar Sync for that write.
349 * So we use the high UDB control register (ASI 0x7f,
350 * ADDR 0x20) for the dummy read. -DaveM
353 __asm__ __volatile__(
354 "wrpr %1, %2, %%pstate\n\t"
355 "stxa %4, [%0] %3\n\t"
356 "stxa %5, [%0+%8] %3\n\t"
358 "stxa %6, [%0+%8] %3\n\t"
360 "stxa %%g0, [%7] %3\n\t"
363 "ldxa [%%g1] 0x7f, %%g0\n\t"
366 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
367 "r" (data0), "r" (data1), "r" (data2), "r" (target),
368 "r" (0x10), "0" (tmp)
371 /* NOTE: PSTATE_IE is still clear. */
374 __asm__ __volatile__("ldxa [%%g0] %1, %0"
376 : "i" (ASI_INTR_DISPATCH_STAT));
378 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
385 } while (result & 0x1);
386 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
389 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
390 smp_processor_id(), result);
397 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
402 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
403 for_each_cpu_mask(i, mask)
404 spitfire_xcall_helper(data0, data1, data2, pstate, i);
407 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
408 * packet, but we have no use for that. However we do take advantage of
409 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
411 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
414 int nack_busy_id, is_jalapeno;
416 if (cpus_empty(mask))
419 /* Unfortunately, someone at Sun had the brilliant idea to make the
420 * busy/nack fields hard-coded by ITID number for this Ultra-III
421 * derivative processor.
423 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
424 is_jalapeno = ((ver >> 32) == 0x003e0016);
426 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
429 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
430 : : "r" (pstate), "i" (PSTATE_IE));
432 /* Setup the dispatch data registers. */
433 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
434 "stxa %1, [%4] %6\n\t"
435 "stxa %2, [%5] %6\n\t"
438 : "r" (data0), "r" (data1), "r" (data2),
439 "r" (0x40), "r" (0x50), "r" (0x60),
446 for_each_cpu_mask(i, mask) {
447 u64 target = (i << 14) | 0x70;
450 target |= (nack_busy_id << 24);
451 __asm__ __volatile__(
452 "stxa %%g0, [%0] %1\n\t"
455 : "r" (target), "i" (ASI_INTR_W));
460 /* Now, poll for completion. */
465 stuck = 100000 * nack_busy_id;
467 __asm__ __volatile__("ldxa [%%g0] %1, %0"
468 : "=r" (dispatch_stat)
469 : "i" (ASI_INTR_DISPATCH_STAT));
470 if (dispatch_stat == 0UL) {
471 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
477 } while (dispatch_stat & 0x5555555555555555UL);
479 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
482 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
483 /* Busy bits will not clear, continue instead
484 * of freezing up on this cpu.
486 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
487 smp_processor_id(), dispatch_stat);
489 int i, this_busy_nack = 0;
491 /* Delay some random time with interrupts enabled
492 * to prevent deadlock.
494 udelay(2 * nack_busy_id);
496 /* Clear out the mask bits for cpus which did not
499 for_each_cpu_mask(i, mask) {
503 check_mask = (0x2UL << (2*i));
505 check_mask = (0x2UL <<
507 if ((dispatch_stat & check_mask) == 0)
517 /* Send cross call to all processors mentioned in MASK
520 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
522 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
523 int this_cpu = get_cpu();
525 cpus_and(mask, mask, cpu_online_map);
526 cpu_clear(this_cpu, mask);
528 if (tlb_type == spitfire)
529 spitfire_xcall_deliver(data0, data1, data2, mask);
531 cheetah_xcall_deliver(data0, data1, data2, mask);
532 /* NOTE: Caller runs local copy on master. */
537 extern unsigned long xcall_sync_tick;
539 static void smp_start_sync_tick_client(int cpu)
541 cpumask_t mask = cpumask_of_cpu(cpu);
543 smp_cross_call_masked(&xcall_sync_tick,
547 /* Send cross call to all processors except self. */
548 #define smp_cross_call(func, ctx, data1, data2) \
549 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
551 struct call_data_struct {
552 void (*func) (void *info);
558 static spinlock_t call_lock = SPIN_LOCK_UNLOCKED;
559 static struct call_data_struct *call_data;
561 extern unsigned long xcall_call_function;
564 * You must not call this function with disabled interrupts or from a
565 * hardware interrupt handler or from a bottom half handler.
567 int smp_call_function(void (*func)(void *info), void *info,
568 int nonatomic, int wait)
570 struct call_data_struct data;
571 int cpus = num_online_cpus() - 1;
577 /* Can deadlock when called with interrupts disabled */
578 WARN_ON(irqs_disabled());
582 atomic_set(&data.finished, 0);
585 spin_lock(&call_lock);
589 smp_cross_call(&xcall_call_function, 0, 0, 0);
592 * Wait for other cpus to complete function or at
593 * least snap the call data.
596 while (atomic_read(&data.finished) != cpus) {
603 spin_unlock(&call_lock);
608 spin_unlock(&call_lock);
609 printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n",
610 (long) num_online_cpus() - 1L,
611 (long) atomic_read(&data.finished));
615 void smp_call_function_client(int irq, struct pt_regs *regs)
617 void (*func) (void *info) = call_data->func;
618 void *info = call_data->info;
620 clear_softint(1 << irq);
621 if (call_data->wait) {
622 /* let initiator proceed only after completion */
624 atomic_inc(&call_data->finished);
626 /* let initiator proceed after getting data */
627 atomic_inc(&call_data->finished);
632 extern unsigned long xcall_flush_tlb_mm;
633 extern unsigned long xcall_flush_tlb_pending;
634 extern unsigned long xcall_flush_tlb_kernel_range;
635 extern unsigned long xcall_flush_tlb_all_spitfire;
636 extern unsigned long xcall_flush_tlb_all_cheetah;
637 extern unsigned long xcall_report_regs;
638 extern unsigned long xcall_receive_signal;
639 extern unsigned long xcall_flush_dcache_page_cheetah;
640 extern unsigned long xcall_flush_dcache_page_spitfire;
642 #ifdef CONFIG_DEBUG_DCFLUSH
643 extern atomic_t dcpage_flushes;
644 extern atomic_t dcpage_flushes_xcall;
647 static __inline__ void __local_flush_dcache_page(struct page *page)
649 #if (L1DCACHE_SIZE > PAGE_SIZE)
650 __flush_dcache_page(page_address(page),
651 ((tlb_type == spitfire) &&
652 page_mapping(page) != NULL));
654 if (page_mapping(page) != NULL &&
655 tlb_type == spitfire)
656 __flush_icache_page(__pa(page_address(page)));
660 void smp_flush_dcache_page_impl(struct page *page, int cpu)
662 cpumask_t mask = cpumask_of_cpu(cpu);
663 int this_cpu = get_cpu();
665 #ifdef CONFIG_DEBUG_DCFLUSH
666 atomic_inc(&dcpage_flushes);
668 if (cpu == this_cpu) {
669 __local_flush_dcache_page(page);
670 } else if (cpu_online(cpu)) {
671 void *pg_addr = page_address(page);
674 if (tlb_type == spitfire) {
676 ((u64)&xcall_flush_dcache_page_spitfire);
677 if (page_mapping(page) != NULL)
678 data0 |= ((u64)1 << 32);
679 spitfire_xcall_deliver(data0,
685 ((u64)&xcall_flush_dcache_page_cheetah);
686 cheetah_xcall_deliver(data0,
690 #ifdef CONFIG_DEBUG_DCFLUSH
691 atomic_inc(&dcpage_flushes_xcall);
698 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
700 void *pg_addr = page_address(page);
701 cpumask_t mask = cpu_online_map;
703 int this_cpu = get_cpu();
705 cpu_clear(this_cpu, mask);
707 #ifdef CONFIG_DEBUG_DCFLUSH
708 atomic_inc(&dcpage_flushes);
710 if (cpus_empty(mask))
712 if (tlb_type == spitfire) {
713 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
714 if (page_mapping(page) != NULL)
715 data0 |= ((u64)1 << 32);
716 spitfire_xcall_deliver(data0,
721 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
722 cheetah_xcall_deliver(data0,
726 #ifdef CONFIG_DEBUG_DCFLUSH
727 atomic_inc(&dcpage_flushes_xcall);
730 __local_flush_dcache_page(page);
735 void smp_receive_signal(int cpu)
737 cpumask_t mask = cpumask_of_cpu(cpu);
739 if (cpu_online(cpu)) {
740 u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff);
742 if (tlb_type == spitfire)
743 spitfire_xcall_deliver(data0, 0, 0, mask);
745 cheetah_xcall_deliver(data0, 0, 0, mask);
749 void smp_receive_signal_client(int irq, struct pt_regs *regs)
751 /* Just return, rtrap takes care of the rest. */
752 clear_softint(1 << irq);
755 void smp_report_regs(void)
757 smp_cross_call(&xcall_report_regs, 0, 0, 0);
760 void smp_flush_tlb_all(void)
762 if (tlb_type == spitfire)
763 smp_cross_call(&xcall_flush_tlb_all_spitfire, 0, 0, 0);
765 smp_cross_call(&xcall_flush_tlb_all_cheetah, 0, 0, 0);
769 /* We know that the window frames of the user have been flushed
770 * to the stack before we get here because all callers of us
771 * are flush_tlb_*() routines, and these run after flush_cache_*()
772 * which performs the flushw.
774 * The SMP TLB coherency scheme we use works as follows:
776 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
777 * space has (potentially) executed on, this is the heuristic
778 * we use to avoid doing cross calls.
780 * Also, for flushing from kswapd and also for clones, we
781 * use cpu_vm_mask as the list of cpus to make run the TLB.
783 * 2) TLB context numbers are shared globally across all processors
784 * in the system, this allows us to play several games to avoid
787 * One invariant is that when a cpu switches to a process, and
788 * that processes tsk->active_mm->cpu_vm_mask does not have the
789 * current cpu's bit set, that tlb context is flushed locally.
791 * If the address space is non-shared (ie. mm->count == 1) we avoid
792 * cross calls when we want to flush the currently running process's
793 * tlb state. This is done by clearing all cpu bits except the current
794 * processor's in current->active_mm->cpu_vm_mask and performing the
795 * flush locally only. This will force any subsequent cpus which run
796 * this task to flush the context from the local tlb if the process
797 * migrates to another cpu (again).
799 * 3) For shared address spaces (threads) and swapping we bite the
800 * bullet for most cases and perform the cross call (but only to
801 * the cpus listed in cpu_vm_mask).
803 * The performance gain from "optimizing" away the cross call for threads is
804 * questionable (in theory the big win for threads is the massive sharing of
805 * address space state across processors).
807 void smp_flush_tlb_mm(struct mm_struct *mm)
810 * This code is called from two places, dup_mmap and exit_mmap. In the
811 * former case, we really need a flush. In the later case, the callers
812 * are single threaded exec_mmap (really need a flush), multithreaded
813 * exec_mmap case (do not need to flush, since the caller gets a new
814 * context via activate_mm), and all other callers of mmput() whence
815 * the flush can be optimized since the associated threads are dead and
816 * the mm is being torn down (__exit_mm and other mmput callers) or the
817 * owning thread is dissociating itself from the mm. The
818 * (atomic_read(&mm->mm_users) == 0) check ensures real work is done
819 * for single thread exec and dup_mmap cases. An alternate check might
820 * have been (current->mm != mm).
823 if (atomic_read(&mm->mm_users) == 0)
827 u32 ctx = CTX_HWBITS(mm->context);
830 if (atomic_read(&mm->mm_users) == 1) {
831 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
832 goto local_flush_and_out;
835 smp_cross_call_masked(&xcall_flush_tlb_mm,
840 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
846 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
848 u32 ctx = CTX_HWBITS(mm->context);
851 if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1) {
852 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
853 goto local_flush_and_out;
855 /* This optimization is not valid. Normally
856 * we will be holding the page_table_lock, but
857 * there is an exception which is copy_page_range()
858 * when forking. The lock is held during the individual
859 * page table updates in the parent, but not at the
860 * top level, which is where we are invoked.
863 cpumask_t this_cpu_mask = cpumask_of_cpu(cpu);
865 /* By virtue of running under the mm->page_table_lock,
866 * and mmu_context.h:switch_mm doing the same, the
867 * following operation is safe.
869 if (cpus_equal(mm->cpu_vm_mask, this_cpu_mask))
870 goto local_flush_and_out;
874 smp_cross_call_masked(&xcall_flush_tlb_pending,
875 ctx, nr, (unsigned long) vaddrs,
879 __flush_tlb_pending(ctx, nr, vaddrs);
884 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
887 end = PAGE_ALIGN(end);
889 smp_cross_call(&xcall_flush_tlb_kernel_range,
892 __flush_tlb_kernel_range(start, end);
897 /* #define CAPTURE_DEBUG */
898 extern unsigned long xcall_capture;
900 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
901 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
902 static unsigned long penguins_are_doing_time;
904 void smp_capture(void)
906 int result = __atomic_add(1, &smp_capture_depth);
908 membar("#StoreStore | #LoadStore");
910 int ncpus = num_online_cpus();
913 printk("CPU[%d]: Sending penguins to jail...",
916 penguins_are_doing_time = 1;
917 membar("#StoreStore | #LoadStore");
918 atomic_inc(&smp_capture_registry);
919 smp_cross_call(&xcall_capture, 0, 0, 0);
920 while (atomic_read(&smp_capture_registry) != ncpus)
928 void smp_release(void)
930 if (atomic_dec_and_test(&smp_capture_depth)) {
932 printk("CPU[%d]: Giving pardon to "
933 "imprisoned penguins\n",
936 penguins_are_doing_time = 0;
937 membar("#StoreStore | #StoreLoad");
938 atomic_dec(&smp_capture_registry);
942 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
943 * can service tlb flush xcalls...
945 extern void prom_world(int);
946 extern void save_alternate_globals(unsigned long *);
947 extern void restore_alternate_globals(unsigned long *);
948 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
950 unsigned long global_save[24];
952 clear_softint(1 << irq);
956 __asm__ __volatile__("flushw");
957 save_alternate_globals(global_save);
959 atomic_inc(&smp_capture_registry);
960 membar("#StoreLoad | #StoreStore");
961 while (penguins_are_doing_time)
963 restore_alternate_globals(global_save);
964 atomic_dec(&smp_capture_registry);
970 extern unsigned long xcall_promstop;
972 void smp_promstop_others(void)
974 smp_cross_call(&xcall_promstop, 0, 0, 0);
977 #define prof_multiplier(__cpu) cpu_data(__cpu).multiplier
978 #define prof_counter(__cpu) cpu_data(__cpu).counter
980 void smp_percpu_timer_interrupt(struct pt_regs *regs)
982 unsigned long compare, tick, pstate;
983 int cpu = smp_processor_id();
984 int user = user_mode(regs);
987 * Check for level 14 softint.
990 unsigned long tick_mask = tick_ops->softint_mask;
992 if (!(get_softint() & tick_mask)) {
993 extern void handler_irq(int, struct pt_regs *);
995 handler_irq(14, regs);
998 clear_softint(tick_mask);
1002 profile_tick(CPU_PROFILING, regs);
1003 if (!--prof_counter(cpu)) {
1006 if (cpu == boot_cpu_id) {
1007 kstat_this_cpu.irqs[0]++;
1008 timer_tick_interrupt(regs);
1011 update_process_times(user);
1015 prof_counter(cpu) = prof_multiplier(cpu);
1018 /* Guarantee that the following sequences execute
1021 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
1022 "wrpr %0, %1, %%pstate"
1026 compare = tick_ops->add_compare(current_tick_offset);
1027 tick = tick_ops->get_tick();
1029 /* Restore PSTATE_IE. */
1030 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
1033 } while (time_after_eq(tick, compare));
1036 static void __init smp_setup_percpu_timer(void)
1038 int cpu = smp_processor_id();
1039 unsigned long pstate;
1041 prof_counter(cpu) = prof_multiplier(cpu) = 1;
1043 /* Guarantee that the following sequences execute
1046 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
1047 "wrpr %0, %1, %%pstate"
1051 tick_ops->init_tick(current_tick_offset);
1053 /* Restore PSTATE_IE. */
1054 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
1059 void __init smp_tick_init(void)
1061 boot_cpu_id = hard_smp_processor_id();
1062 current_tick_offset = timer_tick_offset;
1064 cpu_set(boot_cpu_id, cpu_online_map);
1065 prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1;
1068 cycles_t cacheflush_time;
1069 unsigned long cache_decay_ticks;
1071 extern unsigned long cheetah_tune_scheduling(void);
1073 static void __init smp_tune_scheduling(void)
1075 unsigned long orig_flush_base, flush_base, flags, *p;
1076 unsigned int ecache_size, order;
1077 cycles_t tick1, tick2, raw;
1080 /* Approximate heuristic for SMP scheduling. It is an
1081 * estimation of the time it takes to flush the L2 cache
1082 * on the local processor.
1084 * The ia32 chooses to use the L1 cache flush time instead,
1085 * and I consider this complete nonsense. The Ultra can service
1086 * a miss to the L1 with a hit to the L2 in 7 or 8 cycles, and
1087 * L2 misses are what create extra bus traffic (ie. the "cost"
1088 * of moving a process from one cpu to another).
1090 printk("SMP: Calibrating ecache flush... ");
1091 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1092 cacheflush_time = cheetah_tune_scheduling();
1096 cpu_find_by_instance(0, &cpu_node, NULL);
1097 ecache_size = prom_getintdefault(cpu_node,
1098 "ecache-size", (512 * 1024));
1099 if (ecache_size > (4 * 1024 * 1024))
1100 ecache_size = (4 * 1024 * 1024);
1101 orig_flush_base = flush_base =
1102 __get_free_pages(GFP_KERNEL, order = get_order(ecache_size));
1104 if (flush_base != 0UL) {
1105 local_irq_save(flags);
1107 /* Scan twice the size once just to get the TLB entries
1108 * loaded and make sure the second scan measures pure misses.
1110 for (p = (unsigned long *)flush_base;
1111 ((unsigned long)p) < (flush_base + (ecache_size<<1));
1112 p += (64 / sizeof(unsigned long)))
1113 *((volatile unsigned long *)p);
1115 tick1 = tick_ops->get_tick();
1117 __asm__ __volatile__("1:\n\t"
1118 "ldx [%0 + 0x000], %%g1\n\t"
1119 "ldx [%0 + 0x040], %%g2\n\t"
1120 "ldx [%0 + 0x080], %%g3\n\t"
1121 "ldx [%0 + 0x0c0], %%g5\n\t"
1122 "add %0, 0x100, %0\n\t"
1124 "bne,pt %%xcc, 1b\n\t"
1126 : "=&r" (flush_base)
1128 "r" (flush_base + ecache_size)
1129 : "g1", "g2", "g3", "g5");
1131 tick2 = tick_ops->get_tick();
1133 local_irq_restore(flags);
1135 raw = (tick2 - tick1);
1137 /* Dampen it a little, considering two processes
1138 * sharing the cache and fitting.
1140 cacheflush_time = (raw - (raw >> 2));
1142 free_pages(orig_flush_base, order);
1144 cacheflush_time = ((ecache_size << 2) +
1145 (ecache_size << 1));
1148 /* Convert ticks/sticks to jiffies. */
1149 cache_decay_ticks = cacheflush_time / timer_tick_offset;
1150 if (cache_decay_ticks < 1)
1151 cache_decay_ticks = 1;
1153 printk("Using heuristic of %ld cycles, %ld ticks.\n",
1154 cacheflush_time, cache_decay_ticks);
1157 /* /proc/profile writes can call this, don't __init it please. */
1158 static spinlock_t prof_setup_lock = SPIN_LOCK_UNLOCKED;
1160 int setup_profiling_timer(unsigned int multiplier)
1162 unsigned long flags;
1165 if ((!multiplier) || (timer_tick_offset / multiplier) < 1000)
1168 spin_lock_irqsave(&prof_setup_lock, flags);
1169 for (i = 0; i < NR_CPUS; i++)
1170 prof_multiplier(i) = multiplier;
1171 current_tick_offset = (timer_tick_offset / multiplier);
1172 spin_unlock_irqrestore(&prof_setup_lock, flags);
1177 void __init smp_prepare_cpus(unsigned int max_cpus)
1182 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1184 cpu_set(mid, phys_cpu_present_map);
1188 if (num_possible_cpus() > max_cpus) {
1190 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1191 if (mid != boot_cpu_id) {
1192 cpu_clear(mid, phys_cpu_present_map);
1193 if (num_possible_cpus() <= max_cpus)
1200 smp_store_cpu_info(boot_cpu_id);
1203 void __devinit smp_prepare_boot_cpu(void)
1205 if (hard_smp_processor_id() >= NR_CPUS) {
1206 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
1210 current_thread_info()->cpu = hard_smp_processor_id();
1211 cpu_set(smp_processor_id(), cpu_online_map);
1212 cpu_set(smp_processor_id(), phys_cpu_present_map);
1215 int __devinit __cpu_up(unsigned int cpu)
1217 int ret = smp_boot_one_cpu(cpu);
1220 cpu_set(cpu, smp_commenced_mask);
1221 while (!cpu_isset(cpu, cpu_online_map))
1223 if (!cpu_isset(cpu, cpu_online_map)) {
1226 smp_synchronize_one_tick(cpu);
1232 void __init smp_cpus_done(unsigned int max_cpus)
1234 unsigned long bogosum = 0;
1237 for (i = 0; i < NR_CPUS; i++) {
1239 bogosum += cpu_data(i).udelay_val;
1241 printk("Total of %ld processors activated "
1242 "(%lu.%02lu BogoMIPS).\n",
1243 (long) num_online_cpus(),
1244 bogosum/(500000/HZ),
1245 (bogosum/(5000/HZ))%100);
1247 /* We want to run this with all the other cpus spinning
1250 smp_tune_scheduling();
1253 /* This needn't do anything as we do not sleep the cpu
1254 * inside of the idler task, so an interrupt is not needed
1255 * to get a clean fast response.
1257 * XXX Reverify this assumption... -DaveM
1259 * Addendum: We do want it to do something for the signal
1260 * delivery case, we detect that by just seeing
1261 * if we are trying to send this to an idler or not.
1263 void smp_send_reschedule(int cpu)
1265 if (cpu_data(cpu).idle_volume == 0)
1266 smp_receive_signal(cpu);
1269 /* This is a nop because we capture all other cpus
1270 * anyways when making the PROM active.
1272 void smp_send_stop(void)