arch/alpha/kernel/traps.c

   1 /*
   2  * arch/alpha/kernel/traps.c
   3  *
   4  * (C) Copyright 1994 Linus Torvalds
   5  */
   6
   7 /*
   8  * This file initializes the trap entry points
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/mm.h>
  13 #include <linux/sched.h>
  14 #include <linux/tty.h>
  15 #include <linux/delay.h>
  16 #include <linux/smp_lock.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19
  20 #include <asm/gentrap.h>
  21 #include <asm/uaccess.h>
  22 #include <asm/unaligned.h>
  23 #include <asm/sysinfo.h>
  24 #include <asm/hwrpb.h>
  25 #include <asm/mmu_context.h>
  26
  27 #include "proto.h"
  28
  29 /* Work-around for some SRMs which mishandle opDEC faults.  */
  30
  31 static int opDEC_fix;
  32
  33 static void __init
  34 opDEC_check(void)
  35 {
  36         __asm__ __volatile__ (
  37         /* Load the address of... */
  38         "       br      $16, 1f\n"
  39         /* A stub instruction fault handler.  Just add 4 to the
  40            pc and continue.  */
  41         "       ldq     $16, 8($sp)\n"
  42         "       addq    $16, 4, $16\n"
  43         "       stq     $16, 8($sp)\n"
  44         "       call_pal %[rti]\n"
  45         /* Install the instruction fault handler.  */
  46         "1:     lda     $17, 3\n"
  47         "       call_pal %[wrent]\n"
  48         /* With that in place, the fault from the round-to-minf fp
  49            insn will arrive either at the "lda 4" insn (bad) or one
  50            past that (good).  This places the correct fixup in %0.  */
  51         "       lda %[fix], 0\n"
  52         "       cvttq/svm $f31,$f31\n"
  53         "       lda %[fix], 4"
  54         : [fix] "=r" (opDEC_fix)
  55         : [rti] "n" (PAL_rti), [wrent] "n" (PAL_wrent)
  56         : "$0", "$1", "$16", "$17", "$22", "$23", "$24", "$25");
  57
  58         if (opDEC_fix)
  59                 printk("opDEC fixup enabled.\n");
  60 }
  61
  62 void
  63 dik_show_regs(struct pt_regs *regs, unsigned long *r9_15)
  64 {
  65         printk("pc = [<%016lx>]  ra = [<%016lx>]  ps = %04lx    %s\n",
  66                regs->pc, regs->r26, regs->ps, print_tainted());
  67         printk("v0 = %016lx  t0 = %016lx  t1 = %016lx\n",
  68                regs->r0, regs->r1, regs->r2);
  69         printk("t2 = %016lx  t3 = %016lx  t4 = %016lx\n",
  70                regs->r3, regs->r4, regs->r5);
  71         printk("t5 = %016lx  t6 = %016lx  t7 = %016lx\n",
  72                regs->r6, regs->r7, regs->r8);
  73
  74         if (r9_15) {
  75                 printk("s0 = %016lx  s1 = %016lx  s2 = %016lx\n",
  76                        r9_15[9], r9_15[10], r9_15[11]);
  77                 printk("s3 = %016lx  s4 = %016lx  s5 = %016lx\n",
  78                        r9_15[12], r9_15[13], r9_15[14]);
  79                 printk("s6 = %016lx\n", r9_15[15]);
  80         }
  81
  82         printk("a0 = %016lx  a1 = %016lx  a2 = %016lx\n",
  83                regs->r16, regs->r17, regs->r18);
  84         printk("a3 = %016lx  a4 = %016lx  a5 = %016lx\n",
  85                regs->r19, regs->r20, regs->r21);
  86         printk("t8 = %016lx  t9 = %016lx  t10= %016lx\n",
  87                regs->r22, regs->r23, regs->r24);
  88         printk("t11= %016lx  pv = %016lx  at = %016lx\n",
  89                regs->r25, regs->r27, regs->r28);
  90         printk("gp = %016lx  sp = %p\n", regs->gp, regs+1);
  91 #if 0
  92 __halt();
  93 #endif
  94 }
  95
  96 #if 0
  97 static char * ireg_name[] = {"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
  98                            "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6",
  99                            "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
 100                            "t10", "t11", "ra", "pv", "at", "gp", "sp", "zero"};
 101 #endif
 102
 103 static void
 104 dik_show_code(unsigned int *pc)
 105 {
 106         long i;
 107
 108         printk("Code:");
 109         for (i = -6; i < 2; i++) {
 110                 unsigned int insn;
 111                 if (__get_user(insn, pc+i))
 112                         break;
 113                 printk("%c%08x%c", i ? ' ' : '<', insn, i ? ' ' : '>');
 114         }
 115         printk("\n");
 116 }
 117
 118 static void
 119 dik_show_trace(unsigned long *sp)
 120 {
 121         long i = 0;
 122         printk("Trace:");
 123         while (0x1ff8 & (unsigned long) sp) {
 124                 extern char _stext[], _etext[];
 125                 unsigned long tmp = *sp;
 126                 sp++;
 127                 if (tmp < (unsigned long) &_stext)
 128                         continue;
 129                 if (tmp >= (unsigned long) &_etext)
 130                         continue;
 131                 printk("%lx%c", tmp, ' ');
 132                 if (i > 40) {
 133                         printk(" ...");
 134                         break;
 135                 }
 136         }
 137         printk("\n");
 138 }
 139
 140 static int kstack_depth_to_print = 24;
 141
 142 void show_stack(struct task_struct *task, unsigned long *sp)
 143 {
 144         unsigned long *stack;
 145         int i;
 146
 147         /*
 148          * debugging aid: "show_stack(NULL);" prints the
 149          * back trace for this cpu.
 150          */
 151         if(sp==NULL)
 152                 sp=(unsigned long*)&sp;
 153
 154         stack = sp;
 155         for(i=0; i < kstack_depth_to_print; i++) {
 156                 if (((long) stack & (THREAD_SIZE-1)) == 0)
 157                         break;
 158                 if (i && ((i % 4) == 0))
 159                         printk("\n       ");
 160                 printk("%016lx ", *stack++);
 161         }
 162         printk("\n");
 163         dik_show_trace(sp);
 164 }
 165
 166 void dump_stack(void)
 167 {
 168         show_stack(NULL, NULL);
 169 }
 170
 171 EXPORT_SYMBOL(dump_stack);
 172
 173 void
 174 die_if_kernel(char * str, struct pt_regs *regs, long err, unsigned long *r9_15)
 175 {
 176         if (regs->ps & 8)
 177                 return;
 178 #ifdef CONFIG_SMP
 179         printk("CPU %d ", hard_smp_processor_id());
 180 #endif
 181         printk("%s(%d): %s %ld\n", current->comm, current->pid, str, err);
 182         dik_show_regs(regs, r9_15);
 183         dik_show_trace((unsigned long *)(regs+1));
 184         dik_show_code((unsigned int *)regs->pc);
 185
 186         if (test_and_set_thread_flag (TIF_DIE_IF_KERNEL)) {
 187                 printk("die_if_kernel recursion detected.\n");
 188                 local_irq_enable();
 189                 while (1);
 190         }
 191         do_exit(SIGSEGV);
 192 }
 193
 194 #ifndef CONFIG_MATHEMU
 195 static long dummy_emul(void) { return 0; }
 196 long (*alpha_fp_emul_imprecise)(struct pt_regs *regs, unsigned long writemask)
 197   = (void *)dummy_emul;
 198 long (*alpha_fp_emul) (unsigned long pc)
 199   = (void *)dummy_emul;
 200 #else
 201 long alpha_fp_emul_imprecise(struct pt_regs *regs, unsigned long writemask);
 202 long alpha_fp_emul (unsigned long pc);
 203 #endif
 204
 205 asmlinkage void
 206 do_entArith(unsigned long summary, unsigned long write_mask,
 207             struct pt_regs *regs)
 208 {
 209         long si_code = FPE_FLTINV;
 210         siginfo_t info;
 211
 212         if (summary & 1) {
 213                 /* Software-completion summary bit is set, so try to
 214                    emulate the instruction.  If the processor supports
 215                    precise exceptions, we don't have to search.  */
 216                 if (!amask(AMASK_PRECISE_TRAP))
 217                         si_code = alpha_fp_emul(regs->pc - 4);
 218                 else
 219                         si_code = alpha_fp_emul_imprecise(regs, write_mask);
 220                 if (si_code == 0)
 221                         return;
 222         }
 223         die_if_kernel("Arithmetic fault", regs, 0, 0);
 224
 225         info.si_signo = SIGFPE;
 226         info.si_errno = 0;
 227         info.si_code = si_code;
 228         info.si_addr = (void *) regs->pc;
 229         send_sig_info(SIGFPE, &info, current);
 230 }
 231
 232 asmlinkage void
 233 do_entIF(unsigned long type, struct pt_regs *regs)
 234 {
 235         siginfo_t info;
 236         int signo, code;
 237
 238         if (regs->ps == 0) {
 239                 if (type == 1) {
 240                         const unsigned int *data
 241                           = (const unsigned int *) regs->pc;
 242                         printk("Kernel bug at %s:%d\n",
 243                                (const char *)(data[1] | (long)data[2] << 32),
 244                                data[0]);
 245                 }
 246                 die_if_kernel((type == 1 ? "Kernel Bug" : "Instruction fault"),
 247                               regs, type, 0);
 248         }
 249
 250         switch (type) {
 251               case 0: /* breakpoint */
 252                 info.si_signo = SIGTRAP;
 253                 info.si_errno = 0;
 254                 info.si_code = TRAP_BRKPT;
 255                 info.si_trapno = 0;
 256                 info.si_addr = (void *) regs->pc;
 257
 258                 if (ptrace_cancel_bpt(current)) {
 259                         regs->pc -= 4;  /* make pc point to former bpt */
 260                 }
 261
 262                 send_sig_info(SIGTRAP, &info, current);
 263                 return;
 264
 265               case 1: /* bugcheck */
 266                 info.si_signo = SIGTRAP;
 267                 info.si_errno = 0;
 268                 info.si_code = __SI_FAULT;
 269                 info.si_addr = (void *) regs->pc;
 270                 info.si_trapno = 0;
 271                 send_sig_info(SIGTRAP, &info, current);
 272                 return;
 273
 274               case 2: /* gentrap */
 275                 info.si_addr = (void *) regs->pc;
 276                 info.si_trapno = regs->r16;
 277                 switch ((long) regs->r16) {
 278                 case GEN_INTOVF:
 279                         signo = SIGFPE;
 280                         code = FPE_INTOVF;
 281                         break;
 282                 case GEN_INTDIV:
 283                         signo = SIGFPE;
 284                         code = FPE_INTDIV;
 285                         break;
 286                 case GEN_FLTOVF:
 287                         signo = SIGFPE;
 288                         code = FPE_FLTOVF;
 289                         break;
 290                 case GEN_FLTDIV:
 291                         signo = SIGFPE;
 292                         code = FPE_FLTDIV;
 293                         break;
 294                 case GEN_FLTUND:
 295                         signo = SIGFPE;
 296                         code = FPE_FLTUND;
 297                         break;
 298                 case GEN_FLTINV:
 299                         signo = SIGFPE;
 300                         code = FPE_FLTINV;
 301                         break;
 302                 case GEN_FLTINE:
 303                         signo = SIGFPE;
 304                         code = FPE_FLTRES;
 305                         break;
 306                 case GEN_ROPRAND:
 307                         signo = SIGFPE;
 308                         code = __SI_FAULT;
 309                         break;
 310
 311                 case GEN_DECOVF:
 312                 case GEN_DECDIV:
 313                 case GEN_DECINV:
 314                 case GEN_ASSERTERR:
 315                 case GEN_NULPTRERR:
 316                 case GEN_STKOVF:
 317                 case GEN_STRLENERR:
 318                 case GEN_SUBSTRERR:
 319                 case GEN_RANGERR:
 320                 case GEN_SUBRNG:
 321                 case GEN_SUBRNG1:
 322                 case GEN_SUBRNG2:
 323                 case GEN_SUBRNG3:
 324                 case GEN_SUBRNG4:
 325                 case GEN_SUBRNG5:
 326                 case GEN_SUBRNG6:
 327                 case GEN_SUBRNG7:
 328                 default:
 329                         signo = SIGTRAP;
 330                         code = __SI_FAULT;
 331                         break;
 332                 }
 333
 334                 info.si_signo = signo;
 335                 info.si_errno = 0;
 336                 info.si_code = code;
 337                 info.si_addr = (void *) regs->pc;
 338                 send_sig_info(signo, &info, current);
 339                 return;
 340
 341               case 4: /* opDEC */
 342                 if (implver() == IMPLVER_EV4) {
 343                         long si_code;
 344
 345                         /* The some versions of SRM do not handle
 346                            the opDEC properly - they return the PC of the
 347                            opDEC fault, not the instruction after as the
 348                            Alpha architecture requires.  Here we fix it up.
 349                            We do this by intentionally causing an opDEC
 350                            fault during the boot sequence and testing if
 351                            we get the correct PC.  If not, we set a flag
 352                            to correct it every time through.  */
 353                         regs->pc += opDEC_fix;
 354
 355                         /* EV4 does not implement anything except normal
 356                            rounding.  Everything else will come here as
 357                            an illegal instruction.  Emulate them.  */
 358                         si_code = alpha_fp_emul(regs->pc - 4);
 359                         if (si_code == 0)
 360                                 return;
 361                         if (si_code > 0) {
 362                                 info.si_signo = SIGFPE;
 363                                 info.si_errno = 0;
 364                                 info.si_code = si_code;
 365                                 info.si_addr = (void *) regs->pc;
 366                                 send_sig_info(SIGFPE, &info, current);
 367                                 return;
 368                         }
 369                 }
 370                 break;
 371
 372               case 3: /* FEN fault */
 373                 /* Irritating users can call PAL_clrfen to disable the
 374                    FPU for the process.  The kernel will then trap in
 375                    do_switch_stack and undo_switch_stack when we try
 376                    to save and restore the FP registers.
 377
 378                    Given that GCC by default generates code that uses the
 379                    FP registers, PAL_clrfen is not useful except for DoS
 380                    attacks.  So turn the bleeding FPU back on and be done
 381                    with it.  */
 382                 current_thread_info()->pcb.flags |= 1;
 383                 __reload_thread(&current_thread_info()->pcb);
 384                 return;
 385
 386               case 5: /* illoc */
 387               default: /* unexpected instruction-fault type */
 388                       ;
 389         }
 390
 391         info.si_signo = SIGILL;
 392         info.si_errno = 0;
 393         info.si_code = ILL_ILLOPC;
 394         info.si_addr = (void *) regs->pc;
 395         send_sig_info(SIGILL, &info, current);
 396 }
 397
 398 /* There is an ifdef in the PALcode in MILO that enables a
 399    "kernel debugging entry point" as an unprivileged call_pal.
 400
 401    We don't want to have anything to do with it, but unfortunately
 402    several versions of MILO included in distributions have it enabled,
 403    and if we don't put something on the entry point we'll oops.  */
 404
 405 asmlinkage void
 406 do_entDbg(struct pt_regs *regs)
 407 {
 408         siginfo_t info;
 409
 410         die_if_kernel("Instruction fault", regs, 0, 0);
 411
 412         info.si_signo = SIGILL;
 413         info.si_errno = 0;
 414         info.si_code = ILL_ILLOPC;
 415         info.si_addr = (void *) regs->pc;
 416         force_sig_info(SIGILL, &info, current);
 417 }
 418
 419
 420 /*
 421  * entUna has a different register layout to be reasonably simple. It
 422  * needs access to all the integer registers (the kernel doesn't use
 423  * fp-regs), and it needs to have them in order for simpler access.
 424  *
 425  * Due to the non-standard register layout (and because we don't want
 426  * to handle floating-point regs), user-mode unaligned accesses are
 427  * handled separately by do_entUnaUser below.
 428  *
 429  * Oh, btw, we don't handle the "gp" register correctly, but if we fault
 430  * on a gp-register unaligned load/store, something is _very_ wrong
 431  * in the kernel anyway..
 432  */
 433 struct allregs {
 434         unsigned long regs[32];
 435         unsigned long ps, pc, gp, a0, a1, a2;
 436 };
 437
 438 struct unaligned_stat {
 439         unsigned long count, va, pc;
 440 } unaligned[2];
 441
 442
 443 /* Macro for exception fixup code to access integer registers.  */
 444 #define una_reg(r)  (regs.regs[(r) >= 16 && (r) <= 18 ? (r)+19 : (r)])
 445
 446
 447 asmlinkage void
 448 do_entUna(void * va, unsigned long opcode, unsigned long reg,
 449           unsigned long a3, unsigned long a4, unsigned long a5,
 450           struct allregs regs)
 451 {
 452         long error, tmp1, tmp2, tmp3, tmp4;
 453         unsigned long pc = regs.pc - 4;
 454         const struct exception_table_entry *fixup;
 455
 456         unaligned[0].count++;
 457         unaligned[0].va = (unsigned long) va;
 458         unaligned[0].pc = pc;
 459
 460         /* We don't want to use the generic get/put unaligned macros as
 461            we want to trap exceptions.  Only if we actually get an
 462            exception will we decide whether we should have caught it.  */
 463
 464         switch (opcode) {
 465         case 0x0c: /* ldwu */
 466                 __asm__ __volatile__(
 467                 "1:     ldq_u %1,0(%3)\n"
 468                 "2:     ldq_u %2,1(%3)\n"
 469                 "       extwl %1,%3,%1\n"
 470                 "       extwh %2,%3,%2\n"
 471                 "3:\n"
 472                 ".section __ex_table,\"a\"\n"
 473                 "       .long 1b - .\n"
 474                 "       lda %1,3b-1b(%0)\n"
 475                 "       .long 2b - .\n"
 476                 "       lda %2,3b-2b(%0)\n"
 477                 ".previous"
 478                         : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
 479                         : "r"(va), "0"(0));
 480                 if (error)
 481                         goto got_exception;
 482                 una_reg(reg) = tmp1|tmp2;
 483                 return;
 484
 485         case 0x28: /* ldl */
 486                 __asm__ __volatile__(
 487                 "1:     ldq_u %1,0(%3)\n"
 488                 "2:     ldq_u %2,3(%3)\n"
 489                 "       extll %1,%3,%1\n"
 490                 "       extlh %2,%3,%2\n"
 491                 "3:\n"
 492                 ".section __ex_table,\"a\"\n"
 493                 "       .long 1b - .\n"
 494                 "       lda %1,3b-1b(%0)\n"
 495                 "       .long 2b - .\n"
 496                 "       lda %2,3b-2b(%0)\n"
 497                 ".previous"
 498                         : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
 499                         : "r"(va), "0"(0));
 500                 if (error)
 501                         goto got_exception;
 502                 una_reg(reg) = (int)(tmp1|tmp2);
 503                 return;
 504
 505         case 0x29: /* ldq */
 506                 __asm__ __volatile__(
 507                 "1:     ldq_u %1,0(%3)\n"
 508                 "2:     ldq_u %2,7(%3)\n"
 509                 "       extql %1,%3,%1\n"
 510                 "       extqh %2,%3,%2\n"
 511                 "3:\n"
 512                 ".section __ex_table,\"a\"\n"
 513                 "       .long 1b - .\n"
 514                 "       lda %1,3b-1b(%0)\n"
 515                 "       .long 2b - .\n"
 516                 "       lda %2,3b-2b(%0)\n"
 517                 ".previous"
 518                         : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
 519                         : "r"(va), "0"(0));
 520                 if (error)
 521                         goto got_exception;
 522                 una_reg(reg) = tmp1|tmp2;
 523                 return;
 524
 525         /* Note that the store sequences do not indicate that they change
 526            memory because it _should_ be affecting nothing in this context.
 527            (Otherwise we have other, much larger, problems.)  */
 528         case 0x0d: /* stw */
 529                 __asm__ __volatile__(
 530                 "1:     ldq_u %2,1(%5)\n"
 531                 "2:     ldq_u %1,0(%5)\n"
 532                 "       inswh %6,%5,%4\n"
 533                 "       inswl %6,%5,%3\n"
 534                 "       mskwh %2,%5,%2\n"
 535                 "       mskwl %1,%5,%1\n"
 536                 "       or %2,%4,%2\n"
 537                 "       or %1,%3,%1\n"
 538                 "3:     stq_u %2,1(%5)\n"
 539                 "4:     stq_u %1,0(%5)\n"
 540                 "5:\n"
 541                 ".section __ex_table,\"a\"\n"
 542                 "       .long 1b - .\n"
 543                 "       lda %2,5b-1b(%0)\n"
 544                 "       .long 2b - .\n"
 545                 "       lda %1,5b-2b(%0)\n"
 546                 "       .long 3b - .\n"
 547                 "       lda $31,5b-3b(%0)\n"
 548                 "       .long 4b - .\n"
 549                 "       lda $31,5b-4b(%0)\n"
 550                 ".previous"
 551                         : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
 552                           "=&r"(tmp3), "=&r"(tmp4)
 553                         : "r"(va), "r"(una_reg(reg)), "0"(0));
 554                 if (error)
 555                         goto got_exception;
 556                 return;
 557
 558         case 0x2c: /* stl */
 559                 __asm__ __volatile__(
 560                 "1:     ldq_u %2,3(%5)\n"
 561                 "2:     ldq_u %1,0(%5)\n"
 562                 "       inslh %6,%5,%4\n"
 563                 "       insll %6,%5,%3\n"
 564                 "       msklh %2,%5,%2\n"
 565                 "       mskll %1,%5,%1\n"
 566                 "       or %2,%4,%2\n"
 567                 "       or %1,%3,%1\n"
 568                 "3:     stq_u %2,3(%5)\n"
 569                 "4:     stq_u %1,0(%5)\n"
 570                 "5:\n"
 571                 ".section __ex_table,\"a\"\n"
 572                 "       .long 1b - .\n"
 573                 "       lda %2,5b-1b(%0)\n"
 574                 "       .long 2b - .\n"
 575                 "       lda %1,5b-2b(%0)\n"
 576                 "       .long 3b - .\n"
 577                 "       lda $31,5b-3b(%0)\n"
 578                 "       .long 4b - .\n"
 579                 "       lda $31,5b-4b(%0)\n"
 580                 ".previous"
 581                         : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
 582                           "=&r"(tmp3), "=&r"(tmp4)
 583                         : "r"(va), "r"(una_reg(reg)), "0"(0));
 584                 if (error)
 585                         goto got_exception;
 586                 return;
 587
 588         case 0x2d: /* stq */
 589                 __asm__ __volatile__(
 590                 "1:     ldq_u %2,7(%5)\n"
 591                 "2:     ldq_u %1,0(%5)\n"
 592                 "       insqh %6,%5,%4\n"
 593                 "       insql %6,%5,%3\n"
 594                 "       mskqh %2,%5,%2\n"
 595                 "       mskql %1,%5,%1\n"
 596                 "       or %2,%4,%2\n"
 597                 "       or %1,%3,%1\n"
 598                 "3:     stq_u %2,7(%5)\n"
 599                 "4:     stq_u %1,0(%5)\n"
 600                 "5:\n"
 601                 ".section __ex_table,\"a\"\n\t"
 602                 "       .long 1b - .\n"
 603                 "       lda %2,5b-1b(%0)\n"
 604                 "       .long 2b - .\n"
 605                 "       lda %1,5b-2b(%0)\n"
 606                 "       .long 3b - .\n"
 607                 "       lda $31,5b-3b(%0)\n"
 608                 "       .long 4b - .\n"
 609                 "       lda $31,5b-4b(%0)\n"
 610                 ".previous"
 611                         : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
 612                           "=&r"(tmp3), "=&r"(tmp4)
 613                         : "r"(va), "r"(una_reg(reg)), "0"(0));
 614                 if (error)
 615                         goto got_exception;
 616                 return;
 617         }
 618
 619         lock_kernel();
 620         printk("Bad unaligned kernel access at %016lx: %p %lx %ld\n",
 621                 pc, va, opcode, reg);
 622         do_exit(SIGSEGV);
 623
 624 got_exception:
 625         /* Ok, we caught the exception, but we don't want it.  Is there
 626            someone to pass it along to?  */
 627         if ((fixup = search_exception_tables(pc)) != 0) {
 628                 unsigned long newpc;
 629                 newpc = fixup_exception(una_reg, fixup, pc);
 630
 631                 printk("Forwarding unaligned exception at %lx (%lx)\n",
 632                        pc, newpc);
 633
 634                 (&regs)->pc = newpc;
 635                 return;
 636         }
 637
 638         /*
 639          * Yikes!  No one to forward the exception to.
 640          * Since the registers are in a weird format, dump them ourselves.
 641          */
 642         lock_kernel();
 643
 644         printk("%s(%d): unhandled unaligned exception\n",
 645                current->comm, current->pid);
 646
 647         printk("pc = [<%016lx>]  ra = [<%016lx>]  ps = %04lx\n",
 648                pc, una_reg(26), regs.ps);
 649         printk("r0 = %016lx  r1 = %016lx  r2 = %016lx\n",
 650                una_reg(0), una_reg(1), una_reg(2));
 651         printk("r3 = %016lx  r4 = %016lx  r5 = %016lx\n",
 652                una_reg(3), una_reg(4), una_reg(5));
 653         printk("r6 = %016lx  r7 = %016lx  r8 = %016lx\n",
 654                una_reg(6), una_reg(7), una_reg(8));
 655         printk("r9 = %016lx  r10= %016lx  r11= %016lx\n",
 656                una_reg(9), una_reg(10), una_reg(11));
 657         printk("r12= %016lx  r13= %016lx  r14= %016lx\n",
 658                una_reg(12), una_reg(13), una_reg(14));
 659         printk("r15= %016lx\n", una_reg(15));
 660         printk("r16= %016lx  r17= %016lx  r18= %016lx\n",
 661                una_reg(16), una_reg(17), una_reg(18));
 662         printk("r19= %016lx  r20= %016lx  r21= %016lx\n",
 663                una_reg(19), una_reg(20), una_reg(21));
 664         printk("r22= %016lx  r23= %016lx  r24= %016lx\n",
 665                una_reg(22), una_reg(23), una_reg(24));
 666         printk("r25= %016lx  r27= %016lx  r28= %016lx\n",
 667                una_reg(25), una_reg(27), una_reg(28));
 668         printk("gp = %016lx  sp = %p\n", regs.gp, &regs+1);
 669
 670         dik_show_code((unsigned int *)pc);
 671         dik_show_trace((unsigned long *)(&regs+1));
 672
 673         if (test_and_set_thread_flag (TIF_DIE_IF_KERNEL)) {
 674                 printk("die_if_kernel recursion detected.\n");
 675                 local_irq_enable();
 676                 while (1);
 677         }
 678         do_exit(SIGSEGV);
 679 }
 680
 681 /*
 682  * Convert an s-floating point value in memory format to the
 683  * corresponding value in register format.  The exponent
 684  * needs to be remapped to preserve non-finite values
 685  * (infinities, not-a-numbers, denormals).
 686  */
 687 static inline unsigned long
 688 s_mem_to_reg (unsigned long s_mem)
 689 {
 690         unsigned long frac    = (s_mem >>  0) & 0x7fffff;
 691         unsigned long sign    = (s_mem >> 31) & 0x1;
 692         unsigned long exp_msb = (s_mem >> 30) & 0x1;
 693         unsigned long exp_low = (s_mem >> 23) & 0x7f;
 694         unsigned long exp;
 695
 696         exp = (exp_msb << 10) | exp_low;        /* common case */
 697         if (exp_msb) {
 698                 if (exp_low == 0x7f) {
 699                         exp = 0x7ff;
 700                 }
 701         } else {
 702                 if (exp_low == 0x00) {
 703                         exp = 0x000;
 704                 } else {
 705                         exp |= (0x7 << 7);
 706                 }
 707         }
 708         return (sign << 63) | (exp << 52) | (frac << 29);
 709 }
 710
 711 /*
 712  * Convert an s-floating point value in register format to the
 713  * corresponding value in memory format.
 714  */
 715 static inline unsigned long
 716 s_reg_to_mem (unsigned long s_reg)
 717 {
 718         return ((s_reg >> 62) << 30) | ((s_reg << 5) >> 34);
 719 }
 720
 721 /*
 722  * Handle user-level unaligned fault.  Handling user-level unaligned
 723  * faults is *extremely* slow and produces nasty messages.  A user
 724  * program *should* fix unaligned faults ASAP.
 725  *
 726  * Notice that we have (almost) the regular kernel stack layout here,
 727  * so finding the appropriate registers is a little more difficult
 728  * than in the kernel case.
 729  *
 730  * Finally, we handle regular integer load/stores only.  In
 731  * particular, load-linked/store-conditionally and floating point
 732  * load/stores are not supported.  The former make no sense with
 733  * unaligned faults (they are guaranteed to fail) and I don't think
 734  * the latter will occur in any decent program.
 735  *
 736  * Sigh. We *do* have to handle some FP operations, because GCC will
 737  * uses them as temporary storage for integer memory to memory copies.
 738  * However, we need to deal with stt/ldt and sts/lds only.
 739  */
 740
 741 #define OP_INT_MASK     ( 1L << 0x28 | 1L << 0x2c   /* ldl stl */       \
 742                         | 1L << 0x29 | 1L << 0x2d   /* ldq stq */       \
 743                         | 1L << 0x0c | 1L << 0x0d   /* ldwu stw */      \
 744                         | 1L << 0x0a | 1L << 0x0e ) /* ldbu stb */
 745
 746 #define OP_WRITE_MASK   ( 1L << 0x26 | 1L << 0x27   /* sts stt */       \
 747                         | 1L << 0x2c | 1L << 0x2d   /* stl stq */       \
 748                         | 1L << 0x0d | 1L << 0x0e ) /* stw stb */
 749
 750 #define R(x)    ((size_t) &((struct pt_regs *)0)->x)
 751
 752 static int unauser_reg_offsets[32] = {
 753         R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), R(r8),
 754         /* r9 ... r15 are stored in front of regs.  */
 755         -56, -48, -40, -32, -24, -16, -8,
 756         R(r16), R(r17), R(r18),
 757         R(r19), R(r20), R(r21), R(r22), R(r23), R(r24), R(r25), R(r26),
 758         R(r27), R(r28), R(gp),
 759         0, 0
 760 };
 761
 762 #undef R
 763
 764 asmlinkage void
 765 do_entUnaUser(void * va, unsigned long opcode,
 766               unsigned long reg, struct pt_regs *regs)
 767 {
 768         static int cnt = 0;
 769         static long last_time = 0;
 770
 771         unsigned long tmp1, tmp2, tmp3, tmp4;
 772         unsigned long fake_reg, *reg_addr = &fake_reg;
 773         siginfo_t info;
 774         long error;
 775
 776         /* Check the UAC bits to decide what the user wants us to do
 777            with the unaliged access.  */
 778
 779         if (!test_thread_flag (TIF_UAC_NOPRINT)) {
 780                 if (cnt >= 5 && jiffies - last_time > 5*HZ) {
 781                         cnt = 0;
 782                 }
 783                 if (++cnt < 5) {
 784                         printk("%s(%d): unaligned trap at %016lx: %p %lx %ld\n",
 785                                current->comm, current->pid,
 786                                regs->pc - 4, va, opcode, reg);
 787                 }
 788                 last_time = jiffies;
 789         }
 790         if (test_thread_flag (TIF_UAC_SIGBUS))
 791                 goto give_sigbus;
 792         /* Not sure why you'd want to use this, but... */
 793         if (test_thread_flag (TIF_UAC_NOFIX))
 794                 return;
 795
 796         /* Don't bother reading ds in the access check since we already
 797            know that this came from the user.  Also rely on the fact that
 798            the page at TASK_SIZE is unmapped and so can't be touched anyway. */
 799         if (!__access_ok((unsigned long)va, 0, USER_DS))
 800                 goto give_sigsegv;
 801
 802         ++unaligned[1].count;
 803         unaligned[1].va = (unsigned long)va;
 804         unaligned[1].pc = regs->pc - 4;
 805
 806         if ((1L << opcode) & OP_INT_MASK) {
 807                 /* it's an integer load/store */
 808                 if (reg < 30) {
 809                         reg_addr = (unsigned long *)
 810                           ((char *)regs + unauser_reg_offsets[reg]);
 811                 } else if (reg == 30) {
 812                         /* usp in PAL regs */
 813                         fake_reg = rdusp();
 814                 } else {
 815                         /* zero "register" */
 816                         fake_reg = 0;
 817                 }
 818         }
 819
 820         /* We don't want to use the generic get/put unaligned macros as
 821            we want to trap exceptions.  Only if we actually get an
 822            exception will we decide whether we should have caught it.  */
 823
 824         switch (opcode) {
 825         case 0x0c: /* ldwu */
 826                 __asm__ __volatile__(
 827                 "1:     ldq_u %1,0(%3)\n"
 828                 "2:     ldq_u %2,1(%3)\n"
 829                 "       extwl %1,%3,%1\n"
 830                 "       extwh %2,%3,%2\n"
 831                 "3:\n"
 832                 ".section __ex_table,\"a\"\n"
 833                 "       .long 1b - .\n"
 834                 "       lda %1,3b-1b(%0)\n"
 835                 "       .long 2b - .\n"
 836                 "       lda %2,3b-2b(%0)\n"
 837                 ".previous"
 838                         : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
 839                         : "r"(va), "0"(0));
 840                 if (error)
 841                         goto give_sigsegv;
 842                 *reg_addr = tmp1|tmp2;
 843                 break;
 844
 845         case 0x22: /* lds */
 846                 __asm__ __volatile__(
 847                 "1:     ldq_u %1,0(%3)\n"
 848                 "2:     ldq_u %2,3(%3)\n"
 849                 "       extll %1,%3,%1\n"
 850                 "       extlh %2,%3,%2\n"
 851                 "3:\n"
 852                 ".section __ex_table,\"a\"\n"
 853                 "       .long 1b - .\n"
 854                 "       lda %1,3b-1b(%0)\n"
 855                 "       .long 2b - .\n"
 856                 "       lda %2,3b-2b(%0)\n"
 857                 ".previous"
 858                         : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
 859                         : "r"(va), "0"(0));
 860                 if (error)
 861                         goto give_sigsegv;
 862                 alpha_write_fp_reg(reg, s_mem_to_reg((int)(tmp1|tmp2)));
 863                 return;
 864
 865         case 0x23: /* ldt */
 866                 __asm__ __volatile__(
 867                 "1:     ldq_u %1,0(%3)\n"
 868                 "2:     ldq_u %2,7(%3)\n"
 869                 "       extql %1,%3,%1\n"
 870                 "       extqh %2,%3,%2\n"
 871                 "3:\n"
 872                 ".section __ex_table,\"a\"\n"
 873                 "       .long 1b - .\n"
 874                 "       lda %1,3b-1b(%0)\n"
 875                 "       .long 2b - .\n"
 876                 "       lda %2,3b-2b(%0)\n"
 877                 ".previous"
 878                         : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
 879                         : "r"(va), "0"(0));
 880                 if (error)
 881                         goto give_sigsegv;
 882                 alpha_write_fp_reg(reg, tmp1|tmp2);
 883                 return;
 884
 885         case 0x28: /* ldl */
 886                 __asm__ __volatile__(
 887                 "1:     ldq_u %1,0(%3)\n"
 888                 "2:     ldq_u %2,3(%3)\n"
 889                 "       extll %1,%3,%1\n"
 890                 "       extlh %2,%3,%2\n"
 891                 "3:\n"
 892                 ".section __ex_table,\"a\"\n"
 893                 "       .long 1b - .\n"
 894                 "       lda %1,3b-1b(%0)\n"
 895                 "       .long 2b - .\n"
 896                 "       lda %2,3b-2b(%0)\n"
 897                 ".previous"
 898                         : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
 899                         : "r"(va), "0"(0));
 900                 if (error)
 901                         goto give_sigsegv;
 902                 *reg_addr = (int)(tmp1|tmp2);
 903                 break;
 904
 905         case 0x29: /* ldq */
 906                 __asm__ __volatile__(
 907                 "1:     ldq_u %1,0(%3)\n"
 908                 "2:     ldq_u %2,7(%3)\n"
 909                 "       extql %1,%3,%1\n"
 910                 "       extqh %2,%3,%2\n"
 911                 "3:\n"
 912                 ".section __ex_table,\"a\"\n"
 913                 "       .long 1b - .\n"
 914                 "       lda %1,3b-1b(%0)\n"
 915                 "       .long 2b - .\n"
 916                 "       lda %2,3b-2b(%0)\n"
 917                 ".previous"
 918                         : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
 919                         : "r"(va), "0"(0));
 920                 if (error)
 921                         goto give_sigsegv;
 922                 *reg_addr = tmp1|tmp2;
 923                 break;
 924
 925         /* Note that the store sequences do not indicate that they change
 926            memory because it _should_ be affecting nothing in this context.
 927            (Otherwise we have other, much larger, problems.)  */
 928         case 0x0d: /* stw */
 929                 __asm__ __volatile__(
 930                 "1:     ldq_u %2,1(%5)\n"
 931                 "2:     ldq_u %1,0(%5)\n"
 932                 "       inswh %6,%5,%4\n"
 933                 "       inswl %6,%5,%3\n"
 934                 "       mskwh %2,%5,%2\n"
 935                 "       mskwl %1,%5,%1\n"
 936                 "       or %2,%4,%2\n"
 937                 "       or %1,%3,%1\n"
 938                 "3:     stq_u %2,1(%5)\n"
 939                 "4:     stq_u %1,0(%5)\n"
 940                 "5:\n"
 941                 ".section __ex_table,\"a\"\n"
 942                 "       .long 1b - .\n"
 943                 "       lda %2,5b-1b(%0)\n"
 944                 "       .long 2b - .\n"
 945                 "       lda %1,5b-2b(%0)\n"
 946                 "       .long 3b - .\n"
 947                 "       lda $31,5b-3b(%0)\n"
 948                 "       .long 4b - .\n"
 949                 "       lda $31,5b-4b(%0)\n"
 950                 ".previous"
 951                         : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
 952                           "=&r"(tmp3), "=&r"(tmp4)
 953                         : "r"(va), "r"(*reg_addr), "0"(0));
 954                 if (error)
 955                         goto give_sigsegv;
 956                 return;
 957
 958         case 0x26: /* sts */
 959                 fake_reg = s_reg_to_mem(alpha_read_fp_reg(reg));
 960                 /* FALLTHRU */
 961
 962         case 0x2c: /* stl */
 963                 __asm__ __volatile__(
 964                 "1:     ldq_u %2,3(%5)\n"
 965                 "2:     ldq_u %1,0(%5)\n"
 966                 "       inslh %6,%5,%4\n"
 967                 "       insll %6,%5,%3\n"
 968                 "       msklh %2,%5,%2\n"
 969                 "       mskll %1,%5,%1\n"
 970                 "       or %2,%4,%2\n"
 971                 "       or %1,%3,%1\n"
 972                 "3:     stq_u %2,3(%5)\n"
 973                 "4:     stq_u %1,0(%5)\n"
 974                 "5:\n"
 975                 ".section __ex_table,\"a\"\n"
 976                 "       .long 1b - .\n"
 977                 "       lda %2,5b-1b(%0)\n"
 978                 "       .long 2b - .\n"
 979                 "       lda %1,5b-2b(%0)\n"
 980                 "       .long 3b - .\n"
 981                 "       lda $31,5b-3b(%0)\n"
 982                 "       .long 4b - .\n"
 983                 "       lda $31,5b-4b(%0)\n"
 984                 ".previous"
 985                         : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
 986                           "=&r"(tmp3), "=&r"(tmp4)
 987                         : "r"(va), "r"(*reg_addr), "0"(0));
 988                 if (error)
 989                         goto give_sigsegv;
 990                 return;
 991
 992         case 0x27: /* stt */
 993                 fake_reg = alpha_read_fp_reg(reg);
 994                 /* FALLTHRU */
 995
 996         case 0x2d: /* stq */
 997                 __asm__ __volatile__(
 998                 "1:     ldq_u %2,7(%5)\n"
 999                 "2:     ldq_u %1,0(%5)\n"
1000                 "       insqh %6,%5,%4\n"
1001                 "       insql %6,%5,%3\n"
1002                 "       mskqh %2,%5,%2\n"
1003                 "       mskql %1,%5,%1\n"
1004                 "       or %2,%4,%2\n"
1005                 "       or %1,%3,%1\n"
1006                 "3:     stq_u %2,7(%5)\n"
1007                 "4:     stq_u %1,0(%5)\n"
1008                 "5:\n"
1009                 ".section __ex_table,\"a\"\n\t"
1010                 "       .long 1b - .\n"
1011                 "       lda %2,5b-1b(%0)\n"
1012                 "       .long 2b - .\n"
1013                 "       lda %1,5b-2b(%0)\n"
1014                 "       .long 3b - .\n"
1015                 "       lda $31,5b-3b(%0)\n"
1016                 "       .long 4b - .\n"
1017                 "       lda $31,5b-4b(%0)\n"
1018                 ".previous"
1019                         : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
1020                           "=&r"(tmp3), "=&r"(tmp4)
1021                         : "r"(va), "r"(*reg_addr), "0"(0));
1022                 if (error)
1023                         goto give_sigsegv;
1024                 return;
1025
1026         default:
1027                 /* What instruction were you trying to use, exactly?  */
1028                 goto give_sigbus;
1029         }
1030
1031         /* Only integer loads should get here; everyone else returns early. */
1032         if (reg == 30)
1033                 wrusp(fake_reg);
1034         return;
1035
1036 give_sigsegv:
1037         regs->pc -= 4;  /* make pc point to faulting insn */
1038         info.si_signo = SIGSEGV;
1039         info.si_errno = 0;
1040
1041         /* We need to replicate some of the logic in mm/fault.c,
1042            since we don't have access to the fault code in the
1043            exception handling return path.  */
1044         if (!__access_ok((unsigned long)va, 0, USER_DS))
1045                 info.si_code = SEGV_ACCERR;
1046         else {
1047                 struct mm_struct *mm = current->mm;
1048                 down_read(&mm->mmap_sem);
1049                 if (find_vma(mm, (unsigned long)va))
1050                         info.si_code = SEGV_ACCERR;
1051                 else
1052                         info.si_code = SEGV_MAPERR;
1053                 up_read(&mm->mmap_sem);
1054         }
1055         info.si_addr = va;
1056         send_sig_info(SIGSEGV, &info, current);
1057         return;
1058
1059 give_sigbus:
1060         regs->pc -= 4;
1061         info.si_signo = SIGBUS;
1062         info.si_errno = 0;
1063         info.si_code = BUS_ADRALN;
1064         info.si_addr = va;
1065         send_sig_info(SIGBUS, &info, current);
1066         return;
1067 }
1068
1069 void __init
1070 trap_init(void)
1071 {
1072         /* Tell PAL-code what global pointer we want in the kernel.  */
1073         register unsigned long gptr __asm__("$29");
1074         wrkgp(gptr);
1075
1076         /* Hack for Multia (UDB) and JENSEN: some of their SRMs have
1077            a bug in the handling of the opDEC fault.  Fix it up if so.  */
1078         if (implver() == IMPLVER_EV4)
1079                 opDEC_check();
1080
1081         wrent(entArith, 1);
1082         wrent(entMM, 2);
1083         wrent(entIF, 3);
1084         wrent(entUna, 4);
1085         wrent(entSys, 5);
1086         wrent(entDbg, 6);
1087 }