arch/arm/boot/compressed/head.S

   1 /*
   2  *  linux/arch/arm/boot/compressed/head.S
   3  *
   4  *  Copyright (C) 1996-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/config.h>
  11 #include <linux/linkage.h>
  12
  13 /*
  14  * Debugging stuff
  15  *
  16  * Note that these macros must not contain any code which is not
  17  * 100% relocatable.  Any attempt to do so will result in a crash.
  18  * Please select one of the following when turning on debugging.
  19  */
  20 #ifdef DEBUG
  21 #if defined(CONFIG_DEBUG_DC21285_PORT)
  22                 .macro  loadsp, rb
  23                 mov     \rb, #0x42000000
  24                 .endm
  25                 .macro  writeb, rb
  26                 str     \rb, [r3, #0x160]
  27                 .endm
  28 #elif defined(CONFIG_DEBUG_ICEDCC)
  29                 .macro  loadsp, rb
  30                 .endm
  31                 .macro writeb, rb
  32                 mcr     p14, 0, \rb, c0, c1, 0
  33                 .endm
  34 #elif defined(CONFIG_FOOTBRIDGE)
  35                 .macro  loadsp, rb
  36                 mov     \rb, #0x7c000000
  37                 .endm
  38                 .macro  writeb, rb
  39                 strb    \rb, [r3, #0x3f8]
  40                 .endm
  41 #elif defined(CONFIG_ARCH_RPC)
  42                 .macro  loadsp, rb
  43                 mov     \rb, #0x03000000
  44                 orr     \rb, \rb, #0x00010000
  45                 .endm
  46                 .macro  writeb, rb
  47                 strb    \rb, [r3, #0x3f8 << 2]
  48                 .endm
  49 #elif defined(CONFIG_ARCH_INTEGRATOR)
  50                 .macro  loadsp, rb
  51                 mov     \rb, #0x16000000
  52                 .endm
  53                 .macro  writeb, rb
  54                 strb    \rb, [r3, #0]
  55                 .endm
  56 #elif defined(CONFIG_ARCH_PXA) /* Xscale-type */
  57                 .macro  loadsp, rb
  58                 mov     \rb, #0x40000000
  59                 orr     \rb, \rb, #0x00100000
  60                 .endm
  61                 .macro  writeb, rb
  62                 strb    \rb, [r3, #0]
  63                 .endm
  64 #elif defined(CONFIG_ARCH_SA1100)
  65                 .macro  loadsp, rb
  66                 mov     \rb, #0x80000000        @ physical base address
  67 #  if defined(CONFIG_DEBUG_LL_SER3)
  68                 add     \rb, \rb, #0x00050000   @ Ser3
  69 #  else
  70                 add     \rb, \rb, #0x00010000   @ Ser1
  71 #  endif
  72                 .endm
  73                 .macro  writeb, rb
  74                 str     \rb, [r3, #0x14]        @ UTDR
  75                 .endm
  76 #elif defined(CONFIG_ARCH_IXP4XX)
  77                 .macro  loadsp, rb
  78                 mov     \rb, #0xc8000000
  79                 .endm
  80                 .macro  writeb, rb
  81                 str     \rb, [r3, #0]
  82 #elif defined(CONFIG_ARCH_LH7A40X)
  83                 .macro  loadsp, rb
  84                 ldr     \rb, =0x80000700        @ UART2 UARTBASE
  85                 .endm
  86                 .macro  writeb, rb
  87                 strb    \rb, [r3, #0]
  88                 .endm
  89 #elif defined(CONFIG_ARCH_OMAP)
  90                 .macro  loadsp, rb
  91                 mov     \rb, #0xff000000        @ physical base address
  92                 add     \rb, \rb, #0x00fb0000
  93 #if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
  94                 add     \rb, \rb, #0x00000800
  95 #endif
  96 #ifdef CONFIG_OMAP_LL_DEBUG_UART3
  97                 add     \rb, \rb, #0x00009000
  98 #endif
  99                 .endm
 100                 .macro  writeb, rb
 101                 strb    \rb, [r3]
 102                 .endm
 103 #else
 104 #error no serial architecture defined
 105 #endif
 106 #endif
 107
 108                 .macro  kputc,val
 109                 mov     r0, \val
 110                 bl      putc
 111                 .endm
 112
 113                 .macro  kphex,val,len
 114                 mov     r0, \val
 115                 mov     r1, #\len
 116                 bl      phex
 117                 .endm
 118
 119                 .macro  debug_reloc_start
 120 #ifdef DEBUG
 121                 kputc   #'\n'
 122                 kphex   r6, 8           /* processor id */
 123                 kputc   #':'
 124                 kphex   r7, 8           /* architecture id */
 125                 kputc   #':'
 126                 mrc     p15, 0, r0, c1, c0
 127                 kphex   r0, 8           /* control reg */
 128                 kputc   #'\n'
 129                 kphex   r5, 8           /* decompressed kernel start */
 130                 kputc   #'-'
 131                 kphex   r8, 8           /* decompressed kernel end  */
 132                 kputc   #'>'
 133                 kphex   r4, 8           /* kernel execution address */
 134                 kputc   #'\n'
 135 #endif
 136                 .endm
 137
 138                 .macro  debug_reloc_end
 139 #ifdef DEBUG
 140                 kphex   r5, 8           /* end of kernel */
 141                 kputc   #'\n'
 142                 mov     r0, r4
 143                 bl      memdump         /* dump 256 bytes at start of kernel */
 144 #endif
 145                 .endm
 146
 147                 .section ".start", #alloc, #execinstr
 148 /*
 149  * sort out different calling conventions
 150  */
 151                 .align
 152 start:
 153                 .type   start,#function
 154                 .rept   8
 155                 mov     r0, r0
 156                 .endr
 157
 158                 b       1f
 159                 .word   0x016f2818              @ Magic numbers to help the loader
 160                 .word   start                   @ absolute load/run zImage address
 161                 .word   _edata                  @ zImage end address
 162 1:              mov     r7, r1                  @ save architecture ID
 163                 mov     r8, #0                  @ save r0
 164
 165 #ifndef __ARM_ARCH_2__
 166                 /*
 167                  * Booting from Angel - need to enter SVC mode and disable
 168                  * FIQs/IRQs (numeric definitions from angel arm.h source).
 169                  * We only do this if we were in user mode on entry.
 170                  */
 171                 mrs     r2, cpsr                @ get current mode
 172                 tst     r2, #3                  @ not user?
 173                 bne     not_angel
 174                 mov     r0, #0x17               @ angel_SWIreason_EnterSVC
 175                 swi     0x123456                @ angel_SWI_ARM
 176 not_angel:
 177                 mrs     r2, cpsr                @ turn off interrupts to
 178                 orr     r2, r2, #0xc0           @ prevent angel from running
 179                 msr     cpsr_c, r2
 180 #else
 181                 teqp    pc, #0x0c000003         @ turn off interrupts
 182 #endif
 183
 184                 /*
 185                  * Note that some cache flushing and other stuff may
 186                  * be needed here - is there an Angel SWI call for this?
 187                  */
 188
 189                 /*
 190                  * some architecture specific code can be inserted
 191                  * by the linker here, but it should preserve r7 and r8.
 192                  */
 193
 194                 .text
 195                 adr     r0, LC0
 196                 ldmia   r0, {r1, r2, r3, r4, r5, r6, ip, sp}
 197                 subs    r0, r0, r1              @ calculate the delta offset
 198
 199                                                 @ if delta is zero, we are
 200                 beq     not_relocated           @ running at the address we
 201                                                 @ were linked at.
 202
 203                 /*
 204                  * We're running at a different address.  We need to fix
 205                  * up various pointers:
 206                  *   r5 - zImage base address
 207                  *   r6 - GOT start
 208                  *   ip - GOT end
 209                  */
 210                 add     r5, r5, r0
 211                 add     r6, r6, r0
 212                 add     ip, ip, r0
 213
 214 #ifndef CONFIG_ZBOOT_ROM
 215                 /*
 216                  * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
 217                  * we need to fix up pointers into the BSS region.
 218                  *   r2 - BSS start
 219                  *   r3 - BSS end
 220                  *   sp - stack pointer
 221                  */
 222                 add     r2, r2, r0
 223                 add     r3, r3, r0
 224                 add     sp, sp, r0
 225
 226                 /*
 227                  * Relocate all entries in the GOT table.
 228                  */
 229 1:              ldr     r1, [r6, #0]            @ relocate entries in the GOT
 230                 add     r1, r1, r0              @ table.  This fixes up the
 231                 str     r1, [r6], #4            @ C references.
 232                 cmp     r6, ip
 233                 blo     1b
 234 #else
 235
 236                 /*
 237                  * Relocate entries in the GOT table.  We only relocate
 238                  * the entries that are outside the (relocated) BSS region.
 239                  */
 240 1:              ldr     r1, [r6, #0]            @ relocate entries in the GOT
 241                 cmp     r1, r2                  @ entry < bss_start ||
 242                 cmphs   r3, r1                  @ _end < entry
 243                 addlo   r1, r1, r0              @ table.  This fixes up the
 244                 str     r1, [r6], #4            @ C references.
 245                 cmp     r6, ip
 246                 blo     1b
 247 #endif
 248
 249 not_relocated:  mov     r0, #0
 250 1:              str     r0, [r2], #4            @ clear bss
 251                 str     r0, [r2], #4
 252                 str     r0, [r2], #4
 253                 str     r0, [r2], #4
 254                 cmp     r2, r3
 255                 blo     1b
 256
 257                 /*
 258                  * The C runtime environment should now be setup
 259                  * sufficiently.  Turn the cache on, set up some
 260                  * pointers, and start decompressing.
 261                  */
 262                 bl      cache_on
 263
 264                 mov     r1, sp                  @ malloc space above stack
 265                 add     r2, sp, #0x10000        @ 64k max
 266
 267 /*
 268  * Check to see if we will overwrite ourselves.
 269  *   r4 = final kernel address
 270  *   r5 = start of this image
 271  *   r2 = end of malloc space (and therefore this image)
 272  * We basically want:
 273  *   r4 >= r2 -> OK
 274  *   r4 + image length <= r5 -> OK
 275  */
 276                 cmp     r4, r2
 277                 bhs     wont_overwrite
 278                 add     r0, r4, #4096*1024      @ 4MB largest kernel size
 279                 cmp     r0, r5
 280                 bls     wont_overwrite
 281
 282                 mov     r5, r2                  @ decompress after malloc space
 283                 mov     r0, r5
 284                 mov     r3, r7
 285                 bl      decompress_kernel
 286
 287                 add     r0, r0, #127
 288                 bic     r0, r0, #127            @ align the kernel length
 289 /*
 290  * r0     = decompressed kernel length
 291  * r1-r3  = unused
 292  * r4     = kernel execution address
 293  * r5     = decompressed kernel start
 294  * r6     = processor ID
 295  * r7     = architecture ID
 296  * r8-r14 = unused
 297  */
 298                 add     r1, r5, r0              @ end of decompressed kernel
 299                 adr     r2, reloc_start
 300                 ldr     r3, LC1
 301                 add     r3, r2, r3
 302 1:              ldmia   r2!, {r8 - r13}         @ copy relocation code
 303                 stmia   r1!, {r8 - r13}
 304                 ldmia   r2!, {r8 - r13}
 305                 stmia   r1!, {r8 - r13}
 306                 cmp     r2, r3
 307                 blo     1b
 308
 309                 bl      cache_clean_flush
 310                 add     pc, r5, r0              @ call relocation code
 311
 312 /*
 313  * We're not in danger of overwriting ourselves.  Do this the simple way.
 314  *
 315  * r4     = kernel execution address
 316  * r7     = architecture ID
 317  */
 318 wont_overwrite: mov     r0, r4
 319                 mov     r3, r7
 320                 bl      decompress_kernel
 321                 b       call_kernel
 322
 323                 .type   LC0, #object
 324 LC0:            .word   LC0                     @ r1
 325                 .word   __bss_start             @ r2
 326                 .word   _end                    @ r3
 327                 .word   _load_addr              @ r4
 328                 .word   _start                  @ r5
 329                 .word   _got_start              @ r6
 330                 .word   _got_end                @ ip
 331                 .word   user_stack+4096         @ sp
 332 LC1:            .word   reloc_end - reloc_start
 333                 .size   LC0, . - LC0
 334
 335 /*
 336  * Turn on the cache.  We need to setup some page tables so that we
 337  * can have both the I and D caches on.
 338  *
 339  * We place the page tables 16k down from the kernel execution address,
 340  * and we hope that nothing else is using it.  If we're using it, we
 341  * will go pop!
 342  *
 343  * On entry,
 344  *  r4 = kernel execution address
 345  *  r6 = processor ID
 346  *  r7 = architecture number
 347  *  r8 = run-time address of "start"
 348  * On exit,
 349  *  r1, r2, r3, r8, r9, r12 corrupted
 350  * This routine must preserve:
 351  *  r4, r5, r6, r7
 352  */
 353                 .align  5
 354 cache_on:       mov     r3, #8                  @ cache_on function
 355                 b       call_cache_fn
 356
 357 __setup_mmu:    sub     r3, r4, #16384          @ Page directory size
 358                 bic     r3, r3, #0xff           @ Align the pointer
 359                 bic     r3, r3, #0x3f00
 360 /*
 361  * Initialise the page tables, turning on the cacheable and bufferable
 362  * bits for the RAM area only.
 363  */
 364                 mov     r0, r3
 365                 mov     r8, r0, lsr #18
 366                 mov     r8, r8, lsl #18         @ start of RAM
 367                 add     r9, r8, #0x10000000     @ a reasonable RAM size
 368                 mov     r1, #0x12
 369                 orr     r1, r1, #3 << 10
 370                 add     r2, r3, #16384
 371 1:              cmp     r1, r8                  @ if virt > start of RAM
 372                 orrhs   r1, r1, #0x0c           @ set cacheable, bufferable
 373                 cmp     r1, r9                  @ if virt > end of RAM
 374                 bichs   r1, r1, #0x0c           @ clear cacheable, bufferable
 375                 str     r1, [r0], #4            @ 1:1 mapping
 376                 add     r1, r1, #1048576
 377                 teq     r0, r2
 378                 bne     1b
 379 /*
 380  * If ever we are running from Flash, then we surely want the cache
 381  * to be enabled also for our execution instance...  We map 2MB of it
 382  * so there is no map overlap problem for up to 1 MB compressed kernel.
 383  * If the execution is in RAM then we would only be duplicating the above.
 384  */
 385                 mov     r1, #0x1e
 386                 orr     r1, r1, #3 << 10
 387                 mov     r2, pc, lsr #20
 388                 orr     r1, r1, r2, lsl #20
 389                 add     r0, r3, r2, lsl #2
 390                 str     r1, [r0], #4
 391                 add     r1, r1, #1048576
 392                 str     r1, [r0]
 393                 mov     pc, lr
 394
 395 __armv4_cache_on:
 396                 mov     r12, lr
 397                 bl      __setup_mmu
 398                 mov     r0, #0
 399                 mcr     p15, 0, r0, c7, c10, 4  @ drain write buffer
 400                 mcr     p15, 0, r0, c8, c7, 0   @ flush I,D TLBs
 401                 mrc     p15, 0, r0, c1, c0, 0   @ read control reg
 402                 orr     r0, r0, #0x5000         @ I-cache enable, RR cache replacement
 403                 orr     r0, r0, #0x0030
 404                 bl      __common_cache_on
 405                 mov     r0, #0
 406                 mcr     p15, 0, r0, c8, c7, 0   @ flush I,D TLBs
 407                 mov     pc, r12
 408
 409 __arm6_cache_on:
 410                 mov     r12, lr
 411                 bl      __setup_mmu
 412                 mov     r0, #0
 413                 mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
 414                 mcr     p15, 0, r0, c5, c0, 0   @ invalidate whole TLB v3
 415                 mov     r0, #0x30
 416                 bl      __common_cache_on
 417                 mov     r0, #0
 418                 mcr     p15, 0, r0, c5, c0, 0   @ invalidate whole TLB v3
 419                 mov     pc, r12
 420
 421 __common_cache_on:
 422 #ifndef DEBUG
 423                 orr     r0, r0, #0x000d         @ Write buffer, mmu
 424 #endif
 425                 mov     r1, #-1
 426                 mcr     p15, 0, r3, c2, c0, 0   @ load page table pointer
 427                 mcr     p15, 0, r1, c3, c0, 0   @ load domain access control
 428                 mcr     p15, 0, r0, c1, c0, 0   @ load control register
 429                 mov     pc, lr
 430
 431 /*
 432  * All code following this line is relocatable.  It is relocated by
 433  * the above code to the end of the decompressed kernel image and
 434  * executed there.  During this time, we have no stacks.
 435  *
 436  * r0     = decompressed kernel length
 437  * r1-r3  = unused
 438  * r4     = kernel execution address
 439  * r5     = decompressed kernel start
 440  * r6     = processor ID
 441  * r7     = architecture ID
 442  * r8-r14 = unused
 443  */
 444                 .align  5
 445 reloc_start:    add     r8, r5, r0
 446                 debug_reloc_start
 447                 mov     r1, r4
 448 1:
 449                 .rept   4
 450                 ldmia   r5!, {r0, r2, r3, r9 - r13}     @ relocate kernel
 451                 stmia   r1!, {r0, r2, r3, r9 - r13}
 452                 .endr
 453
 454                 cmp     r5, r8
 455                 blo     1b
 456                 debug_reloc_end
 457
 458 call_kernel:    bl      cache_clean_flush
 459                 bl      cache_off
 460                 mov     r0, #0
 461                 mov     r1, r7                  @ restore architecture number
 462                 mov     pc, r4                  @ call kernel
 463
 464 /*
 465  * Here follow the relocatable cache support functions for the
 466  * various processors.  This is a generic hook for locating an
 467  * entry and jumping to an instruction at the specified offset
 468  * from the start of the block.  Please note this is all position
 469  * independent code.
 470  *
 471  *  r1  = corrupted
 472  *  r2  = corrupted
 473  *  r3  = block offset
 474  *  r6  = corrupted
 475  *  r12 = corrupted
 476  */
 477
 478 call_cache_fn:  adr     r12, proc_types
 479                 mrc     p15, 0, r6, c0, c0      @ get processor ID
 480 1:              ldr     r1, [r12, #0]           @ get value
 481                 ldr     r2, [r12, #4]           @ get mask
 482                 eor     r1, r1, r6              @ (real ^ match)
 483                 tst     r1, r2                  @       & mask
 484                 addeq   pc, r12, r3             @ call cache function
 485                 add     r12, r12, #4*5
 486                 b       1b
 487
 488 /*
 489  * Table for cache operations.  This is basically:
 490  *   - CPU ID match
 491  *   - CPU ID mask
 492  *   - 'cache on' method instruction
 493  *   - 'cache off' method instruction
 494  *   - 'cache flush' method instruction
 495  *
 496  * We match an entry using: ((real_id ^ match) & mask) == 0
 497  *
 498  * Writethrough caches generally only need 'on' and 'off'
 499  * methods.  Writeback caches _must_ have the flush method
 500  * defined.
 501  */
 502                 .type   proc_types,#object
 503 proc_types:
 504                 .word   0x41560600              @ ARM6/610
 505                 .word   0xffffffe0
 506                 b       __arm6_cache_off        @ works, but slow
 507                 b       __arm6_cache_off
 508                 mov     pc, lr
 509 @               b       __arm6_cache_on         @ untested
 510 @               b       __arm6_cache_off
 511 @               b       __armv3_cache_flush
 512
 513                 .word   0x00000000              @ old ARM ID
 514                 .word   0x0000f000
 515                 mov     pc, lr
 516                 mov     pc, lr
 517                 mov     pc, lr
 518
 519                 .word   0x41007000              @ ARM7/710
 520                 .word   0xfff8fe00
 521                 b       __arm7_cache_off
 522                 b       __arm7_cache_off
 523                 mov     pc, lr
 524
 525                 .word   0x41807200              @ ARM720T (writethrough)
 526                 .word   0xffffff00
 527                 b       __armv4_cache_on
 528                 b       __armv4_cache_off
 529                 mov     pc, lr
 530
 531                 .word   0x00007000              @ ARM7 IDs
 532                 .word   0x0000f000
 533                 mov     pc, lr
 534                 mov     pc, lr
 535                 mov     pc, lr
 536
 537                 @ Everything from here on will be the new ID system.
 538
 539                 .word   0x4401a100              @ sa110 / sa1100
 540                 .word   0xffffffe0
 541                 b       __armv4_cache_on
 542                 b       __armv4_cache_off
 543                 b       __armv4_cache_flush
 544
 545                 .word   0x6901b110              @ sa1110
 546                 .word   0xfffffff0
 547                 b       __armv4_cache_on
 548                 b       __armv4_cache_off
 549                 b       __armv4_cache_flush
 550
 551                 @ These match on the architecture ID
 552
 553                 .word   0x00020000              @ ARMv4T
 554                 .word   0x000f0000
 555                 b       __armv4_cache_on
 556                 b       __armv4_cache_off
 557                 b       __armv4_cache_flush
 558
 559                 .word   0x00050000              @ ARMv5TE
 560                 .word   0x000f0000
 561                 b       __armv4_cache_on
 562                 b       __armv4_cache_off
 563                 b       __armv4_cache_flush
 564
 565                 .word   0x00060000              @ ARMv5TEJ
 566                 .word   0x000f0000
 567                 b       __armv4_cache_on
 568                 b       __armv4_cache_off
 569                 b       __armv4_cache_flush
 570
 571                 .word   0                       @ unrecognised type
 572                 .word   0
 573                 mov     pc, lr
 574                 mov     pc, lr
 575                 mov     pc, lr
 576
 577                 .size   proc_types, . - proc_types
 578
 579 /*
 580  * Turn off the Cache and MMU.  ARMv3 does not support
 581  * reading the control register, but ARMv4 does.
 582  *
 583  * On entry,  r6 = processor ID
 584  * On exit,   r0, r1, r2, r3, r12 corrupted
 585  * This routine must preserve: r4, r6, r7
 586  */
 587                 .align  5
 588 cache_off:      mov     r3, #12                 @ cache_off function
 589                 b       call_cache_fn
 590
 591 __armv4_cache_off:
 592                 mrc     p15, 0, r0, c1, c0
 593                 bic     r0, r0, #0x000d
 594                 mcr     p15, 0, r0, c1, c0      @ turn MMU and cache off
 595                 mov     r0, #0
 596                 mcr     p15, 0, r0, c7, c7      @ invalidate whole cache v4
 597                 mcr     p15, 0, r0, c8, c7      @ invalidate whole TLB v4
 598                 mov     pc, lr
 599
 600 __arm6_cache_off:
 601                 mov     r0, #0x00000030         @ ARM6 control reg.
 602                 b       __armv3_cache_off
 603
 604 __arm7_cache_off:
 605                 mov     r0, #0x00000070         @ ARM7 control reg.
 606                 b       __armv3_cache_off
 607
 608 __armv3_cache_off:
 609                 mcr     p15, 0, r0, c1, c0, 0   @ turn MMU and cache off
 610                 mov     r0, #0
 611                 mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
 612                 mcr     p15, 0, r0, c5, c0, 0   @ invalidate whole TLB v3
 613                 mov     pc, lr
 614
 615 /*
 616  * Clean and flush the cache to maintain consistency.
 617  *
 618  * On entry,
 619  *  r6 = processor ID
 620  * On exit,
 621  *  r1, r2, r3, r11, r12 corrupted
 622  * This routine must preserve:
 623  *  r0, r4, r5, r6, r7
 624  */
 625                 .align  5
 626 cache_clean_flush:
 627                 mov     r3, #16
 628                 b       call_cache_fn
 629
 630 __armv4_cache_flush:
 631                 mov     r2, #64*1024            @ default: 32K dcache size (*2)
 632                 mov     r11, #32                @ default: 32 byte line size
 633                 mrc     p15, 0, r3, c0, c0, 1   @ read cache type
 634                 teq     r3, r6                  @ cache ID register present?
 635                 beq     no_cache_id
 636                 mov     r1, r3, lsr #18
 637                 and     r1, r1, #7
 638                 mov     r2, #1024
 639                 mov     r2, r2, lsl r1          @ base dcache size *2
 640                 tst     r3, #1 << 14            @ test M bit
 641                 addne   r2, r2, r2, lsr #1      @ +1/2 size if M == 1
 642                 mov     r3, r3, lsr #12
 643                 and     r3, r3, #3
 644                 mov     r11, #8
 645                 mov     r11, r11, lsl r3        @ cache line size in bytes
 646 no_cache_id:
 647                 bic     r1, pc, #63             @ align to longest cache line
 648                 add     r2, r1, r2
 649 1:              ldr     r3, [r1], r11           @ s/w flush D cache
 650                 teq     r1, r2
 651                 bne     1b
 652
 653                 mcr     p15, 0, r1, c7, c5, 0   @ flush I cache
 654                 mcr     p15, 0, r1, c7, c6, 0   @ flush D cache
 655                 mcr     p15, 0, r1, c7, c10, 4  @ drain WB
 656                 mov     pc, lr
 657
 658 __armv3_cache_flush:
 659                 mov     r1, #0
 660                 mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
 661                 mov     pc, lr
 662
 663 /*
 664  * Various debugging routines for printing hex characters and
 665  * memory, which again must be relocatable.
 666  */
 667 #ifdef DEBUG
 668                 .type   phexbuf,#object
 669 phexbuf:        .space  12
 670                 .size   phexbuf, . - phexbuf
 671
 672 phex:           adr     r3, phexbuf
 673                 mov     r2, #0
 674                 strb    r2, [r3, r1]
 675 1:              subs    r1, r1, #1
 676                 movmi   r0, r3
 677                 bmi     puts
 678                 and     r2, r0, #15
 679                 mov     r0, r0, lsr #4
 680                 cmp     r2, #10
 681                 addge   r2, r2, #7
 682                 add     r2, r2, #'0'
 683                 strb    r2, [r3, r1]
 684                 b       1b
 685
 686 puts:           loadsp  r3
 687 1:              ldrb    r2, [r0], #1
 688                 teq     r2, #0
 689                 moveq   pc, lr
 690 2:              writeb  r2
 691                 mov     r1, #0x00020000
 692 3:              subs    r1, r1, #1
 693                 bne     3b
 694                 teq     r2, #'\n'
 695                 moveq   r2, #'\r'
 696                 beq     2b
 697                 teq     r0, #0
 698                 bne     1b
 699                 mov     pc, lr
 700 putc:
 701                 mov     r2, r0
 702                 mov     r0, #0
 703                 loadsp  r3
 704                 b       2b
 705
 706 memdump:        mov     r12, r0
 707                 mov     r10, lr
 708                 mov     r11, #0
 709 2:              mov     r0, r11, lsl #2
 710                 add     r0, r0, r12
 711                 mov     r1, #8
 712                 bl      phex
 713                 mov     r0, #':'
 714                 bl      putc
 715 1:              mov     r0, #' '
 716                 bl      putc
 717                 ldr     r0, [r12, r11, lsl #2]
 718                 mov     r1, #8
 719                 bl      phex
 720                 and     r0, r11, #7
 721                 teq     r0, #3
 722                 moveq   r0, #' '
 723                 bleq    putc
 724                 and     r0, r11, #7
 725                 add     r11, r11, #1
 726                 teq     r0, #7
 727                 bne     1b
 728                 mov     r0, #'\n'
 729                 bl      putc
 730                 cmp     r11, #64
 731                 blt     2b
 732                 mov     pc, r10
 733 #endif
 734
 735 reloc_end:
 736
 737                 .align
 738                 .section ".stack", "w"
 739 user_stack:     .space  4096