2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/config.h>
11 #include <linux/linkage.h>
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
21 #if defined(CONFIG_DEBUG_DC21285_PORT)
28 #elif defined(CONFIG_DEBUG_ICEDCC)
32 mcr p14, 0, \rb, c0, c1, 0
34 #elif defined(CONFIG_FOOTBRIDGE)
39 strb \rb, [r3, #0x3f8]
41 #elif defined(CONFIG_ARCH_RPC)
44 orr \rb, \rb, #0x00010000
47 strb \rb, [r3, #0x3f8 << 2]
49 #elif defined(CONFIG_ARCH_INTEGRATOR)
56 #elif defined(CONFIG_ARCH_PXA) /* Xscale-type */
59 orr \rb, \rb, #0x00100000
64 #elif defined(CONFIG_ARCH_SA1100)
66 mov \rb, #0x80000000 @ physical base address
67 # if defined(CONFIG_DEBUG_LL_SER3)
68 add \rb, \rb, #0x00050000 @ Ser3
70 add \rb, \rb, #0x00010000 @ Ser1
74 str \rb, [r3, #0x14] @ UTDR
76 #elif defined(CONFIG_ARCH_LH7A40X)
78 ldr \rb, =0x80000700 @ UART2 UARTBASE
84 #error no serial architecture defined
99 .macro debug_reloc_start
102 kphex r6, 8 /* processor id */
104 kphex r7, 8 /* architecture id */
106 mrc p15, 0, r0, c1, c0
107 kphex r0, 8 /* control reg */
109 kphex r5, 8 /* decompressed kernel start */
111 kphex r8, 8 /* decompressed kernel end */
113 kphex r4, 8 /* kernel execution address */
118 .macro debug_reloc_end
120 kphex r5, 8 /* end of kernel */
123 bl memdump /* dump 256 bytes at start of kernel */
127 .section ".start", #alloc, #execinstr
129 * sort out different calling conventions
133 .type start,#function
139 .word 0x016f2818 @ Magic numbers to help the loader
140 .word start @ absolute load/run zImage address
141 .word _edata @ zImage end address
142 1: mov r7, r1 @ save architecture ID
145 #ifndef __ARM_ARCH_2__
147 * Booting from Angel - need to enter SVC mode and disable
148 * FIQs/IRQs (numeric definitions from angel arm.h source).
149 * We only do this if we were in user mode on entry.
151 mrs r2, cpsr @ get current mode
152 tst r2, #3 @ not user?
154 mov r0, #0x17 @ angel_SWIreason_EnterSVC
155 swi 0x123456 @ angel_SWI_ARM
157 mrs r2, cpsr @ turn off interrupts to
158 orr r2, r2, #0xc0 @ prevent angel from running
161 teqp pc, #0x0c000003 @ turn off interrupts
165 * Note that some cache flushing and other stuff may
166 * be needed here - is there an Angel SWI call for this?
170 * some architecture specific code can be inserted
171 * by the linker here, but it should preserve r7 and r8.
176 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
177 subs r0, r0, r1 @ calculate the delta offset
179 @ if delta is zero, we're
180 beq not_relocated @ running at the address we
184 * We're running at a different address. We need to fix
185 * up various pointers:
186 * r5 - zImage base address
194 #ifndef CONFIG_ZBOOT_ROM
196 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
197 * we need to fix up pointers into the BSS region.
207 * Relocate all entries in the GOT table.
209 1: ldr r1, [r6, #0] @ relocate entries in the GOT
210 add r1, r1, r0 @ table. This fixes up the
211 str r1, [r6], #4 @ C references.
217 * Relocate entries in the GOT table. We only relocate
218 * the entries that are outside the (relocated) BSS region.
220 1: ldr r1, [r6, #0] @ relocate entries in the GOT
221 cmp r1, r2 @ entry < bss_start ||
222 cmphs r3, r1 @ _end < entry
223 addlo r1, r1, r0 @ table. This fixes up the
224 str r1, [r6], #4 @ C references.
229 not_relocated: mov r0, #0
230 1: str r0, [r2], #4 @ clear bss
238 * The C runtime environment should now be setup
239 * sufficiently. Turn the cache on, set up some
240 * pointers, and start decompressing.
244 mov r1, sp @ malloc space above stack
245 add r2, sp, #0x10000 @ 64k max
248 * Check to see if we will overwrite ourselves.
249 * r4 = final kernel address
250 * r5 = start of this image
251 * r2 = end of malloc space (and therefore this image)
254 * r4 + image length <= r5 -> OK
258 add r0, r4, #4096*1024 @ 4MB largest kernel size
262 mov r5, r2 @ decompress after malloc space
268 bic r0, r0, #127 @ align the kernel length
270 * r0 = decompressed kernel length
272 * r4 = kernel execution address
273 * r5 = decompressed kernel start
275 * r7 = architecture ID
278 add r1, r5, r0 @ end of decompressed kernel
282 1: ldmia r2!, {r8 - r13} @ copy relocation code
283 stmia r1!, {r8 - r13}
284 ldmia r2!, {r8 - r13}
285 stmia r1!, {r8 - r13}
290 add pc, r5, r0 @ call relocation code
293 * We're not in danger of overwriting ourselves. Do this the simple way.
295 * r4 = kernel execution address
296 * r7 = architecture ID
298 wont_overwrite: mov r0, r4
305 .word __bss_start @ r2
307 .word _load_addr @ r4
309 .word _got_start @ r6
311 .word user_stack+4096 @ sp
312 LC1: .word reloc_end - reloc_start
316 * Turn on the cache. We need to setup some page tables so that we
317 * can have both the I and D caches on.
319 * We place the page tables 16k down from the kernel execution address,
320 * and we hope that nothing else is using it. If we're using it, we
324 * r4 = kernel execution address
326 * r7 = architecture number
327 * r8 = run-time address of "start"
329 * r1, r2, r3, r8, r9, r12 corrupted
330 * This routine must preserve:
334 cache_on: mov r3, #8 @ cache_on function
337 __setup_mmu: sub r3, r4, #16384 @ Page directory size
338 bic r3, r3, #0xff @ Align the pointer
341 * Initialise the page tables, turning on the cacheable and bufferable
342 * bits for the RAM area only.
346 mov r8, r8, lsl #18 @ start of RAM
347 add r9, r8, #0x10000000 @ a reasonable RAM size
351 1: cmp r1, r8 @ if virt > start of RAM
352 orrhs r1, r1, #0x0c @ set cacheable, bufferable
353 cmp r1, r9 @ if virt > end of RAM
354 bichs r1, r1, #0x0c @ clear cacheable, bufferable
355 str r1, [r0], #4 @ 1:1 mapping
360 * If ever we are running from Flash, then we surely want the cache
361 * to be enabled also for our execution instance... We map 2MB of it
362 * so there is no map overlap problem for up to 1 MB compressed kernel.
363 * If the execution is in RAM then we would only be duplicating the above.
368 orr r1, r1, r2, lsl #20
369 add r0, r3, r2, lsl #2
379 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
380 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
381 mrc p15, 0, r0, c1, c0, 0 @ read control reg
382 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
386 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
393 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
394 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
398 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
403 orr r0, r0, #0x000d @ Write buffer, mmu
406 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
407 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
408 mcr p15, 0, r0, c1, c0, 0 @ load control register
412 * All code following this line is relocatable. It is relocated by
413 * the above code to the end of the decompressed kernel image and
414 * executed there. During this time, we have no stacks.
416 * r0 = decompressed kernel length
418 * r4 = kernel execution address
419 * r5 = decompressed kernel start
421 * r7 = architecture ID
425 reloc_start: add r8, r5, r0
430 ldmia r5!, {r0, r2, r3, r9 - r13} @ relocate kernel
431 stmia r1!, {r0, r2, r3, r9 - r13}
438 call_kernel: bl cache_clean_flush
441 mov r1, r7 @ restore architecture number
442 mov pc, r4 @ call kernel
445 * Here follow the relocatable cache support functions for the
446 * various processors. This is a generic hook for locating an
447 * entry and jumping to an instruction at the specified offset
448 * from the start of the block. Please note this is all position
458 call_cache_fn: adr r12, proc_types
459 mrc p15, 0, r6, c0, c0 @ get processor ID
460 1: ldr r1, [r12, #0] @ get value
461 ldr r2, [r12, #4] @ get mask
462 eor r1, r1, r6 @ (real ^ match)
464 addeq pc, r12, r3 @ call cache function
469 * Table for cache operations. This is basically:
472 * - 'cache on' method instruction
473 * - 'cache off' method instruction
474 * - 'cache flush' method instruction
476 * We match an entry using: ((real_id ^ match) & mask) == 0
478 * Writethrough caches generally only need 'on' and 'off'
479 * methods. Writeback caches _must_ have the flush method
482 .type proc_types,#object
484 .word 0x41560600 @ ARM6/610
486 b __arm6_cache_off @ works, but slow
489 @ b __arm6_cache_on @ untested
491 @ b __armv3_cache_flush
493 .word 0x00000000 @ old ARM ID
499 .word 0x41007000 @ ARM7/710
505 .word 0x41807200 @ ARM720T (writethrough)
511 .word 0x00007000 @ ARM7 IDs
517 @ Everything from here on will be the new ID system.
519 .word 0x4401a100 @ sa110 / sa1100
523 b __armv4_cache_flush
525 .word 0x6901b110 @ sa1110
529 b __armv4_cache_flush
531 @ These match on the architecture ID
533 .word 0x00020000 @ ARMv4T
537 b __armv4_cache_flush
539 .word 0x00050000 @ ARMv5TE
543 b __armv4_cache_flush
545 .word 0x00060000 @ ARMv5TEJ
549 b __armv4_cache_flush
551 .word 0 @ unrecognised type
557 .size proc_types, . - proc_types
560 * Turn off the Cache and MMU. ARMv3 does not support
561 * reading the control register, but ARMv4 does.
563 * On entry, r6 = processor ID
564 * On exit, r0, r1, r2, r3, r12 corrupted
565 * This routine must preserve: r4, r6, r7
568 cache_off: mov r3, #12 @ cache_off function
572 mrc p15, 0, r0, c1, c0
574 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
576 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
577 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
581 mov r0, #0x00000030 @ ARM6 control reg.
585 mov r0, #0x00000070 @ ARM7 control reg.
589 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
591 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
592 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
596 * Clean and flush the cache to maintain consistency.
601 * r1, r2, r3, r11, r12 corrupted
602 * This routine must preserve:
611 mov r2, #64*1024 @ default: 32K dcache size (*2)
612 mov r11, #32 @ default: 32 byte line size
613 mrc p15, 0, r3, c0, c0, 1 @ read cache type
614 teq r3, r6 @ cache ID register present?
619 mov r2, r2, lsl r1 @ base dcache size *2
620 tst r3, #1 << 14 @ test M bit
621 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
625 mov r11, r11, lsl r3 @ cache line size in bytes
627 bic r1, pc, #63 @ align to longest cache line
629 1: ldr r3, [r1], r11 @ s/w flush D cache
633 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
634 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
635 mcr p15, 0, r1, c7, c10, 4 @ drain WB
640 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
644 * Various debugging routines for printing hex characters and
645 * memory, which again must be relocatable.
648 .type phexbuf,#object
650 .size phexbuf, . - phexbuf
652 phex: adr r3, phexbuf
689 2: mov r0, r11, lsl #2
697 ldr r0, [r12, r11, lsl #2]
718 .section ".stack", "w"
719 user_stack: .space 4096