2 * linux/arch/arm/mach-h720x/cpu-h7202.c
4 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
5 * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
6 * 2004 Sascha Hauer <s.hauer@pengutronix.de>
8 * processor specific stuff for the Hynix h7201
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <asm/types.h>
20 #include <asm/hardware.h>
22 #include <asm/arch/irqs.h>
23 #include <asm/mach/irq.h>
24 #include <asm/mach/time.h>
25 #include <linux/device.h>
27 static struct resource h7202ps2_resources[] = {
31 .flags = IORESOURCE_MEM,
36 .flags = IORESOURCE_IRQ,
40 static struct platform_device h7202ps2_device = {
43 .num_resources = ARRAY_SIZE(h7202ps2_resources),
44 .resource = h7202ps2_resources,
47 static struct platform_device *devices[] __initdata = {
51 extern unsigned long h720x_gettimeoffset(void);
52 extern void __init h720x_init_irq (void);
54 /* Although we have two interrupt lines for the timers, we only have one
55 * status register which clears all pending timer interrupts on reading. So
56 * we have to handle all timer interrupts in one place.
59 h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
62 unsigned int mask, irq;
64 mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
66 if ( mask & TSTAT_T0INT ) {
68 if( mask == TSTAT_T0INT )
74 desc = irq_desc + irq;
77 desc->handle(irq, desc, regs);
85 * Timer interrupt handler
88 h7202_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
90 h7202_timerx_demux_handler(0, NULL, regs);
95 * mask multiplexed timer irq's
97 static void inline mask_timerx_irq (u32 irq)
100 bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
101 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
105 * unmask multiplexed timer irq's
107 static void inline unmask_timerx_irq (u32 irq)
110 bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
111 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
114 static struct irqchip h7202_timerx_chip = {
115 .ack = mask_timerx_irq,
116 .mask = mask_timerx_irq,
117 .unmask = unmask_timerx_irq,
120 static struct irqaction h7202_timer_irq = {
121 .name = "h7202 Timer Tick",
122 .flags = SA_INTERRUPT,
123 .handler = h7202_timer_interrupt
127 * Setup TIMER0 as system timer
129 void __init h7202_init_time(void)
131 gettimeoffset = h720x_gettimeoffset;
133 CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
134 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
135 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
136 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
138 setup_irq(IRQ_TIMER0, &h7202_timer_irq);
141 void __init h7202_init_irq (void)
145 CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0;
147 for (irq = IRQ_TIMER1;
148 irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
149 mask_timerx_irq(irq);
150 set_irq_chip(irq, &h7202_timerx_chip);
151 set_irq_handler(irq, do_edge_IRQ);
152 set_irq_flags(irq, IRQF_VALID );
154 set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
159 void __init init_hw_h7202(void)
162 CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE;
164 (void) platform_add_devices(devices, ARRAY_SIZE(devices));