arch/arm/mach-integrator/integrator_cp.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_cp.c
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/list.h>
  14 #include <linux/device.h>
  15 #include <linux/slab.h>
  16 #include <linux/string.h>
  17 #include <linux/sysdev.h>
  18
  19 #include <asm/hardware.h>
  20 #include <asm/io.h>
  21 #include <asm/irq.h>
  22 #include <asm/setup.h>
  23 #include <asm/mach-types.h>
  24 #include <asm/hardware/amba.h>
  25 #include <asm/hardware/amba_kmi.h>
  26 #include <asm/hardware/icst525.h>
  27
  28 #include <asm/arch/lm.h>
  29
  30 #include <asm/mach/arch.h>
  31 #include <asm/mach/flash.h>
  32 #include <asm/mach/irq.h>
  33 #include <asm/mach/mmc.h>
  34 #include <asm/mach/map.h>
  35
  36 #include "clock.h"
  37
  38 #define INTCP_PA_MMC_BASE               0x1c000000
  39 #define INTCP_PA_AACI_BASE              0x1d000000
  40
  41 #define INTCP_PA_FLASH_BASE             0x24000000
  42 #define INTCP_FLASH_SIZE                SZ_32M
  43
  44 #define INTCP_PA_CLCD_BASE              0xc0000000
  45
  46 #define INTCP_VA_CIC_BASE               0xf1000040
  47 #define INTCP_VA_PIC_BASE               0xf1400000
  48 #define INTCP_VA_SIC_BASE               0xfca00000
  49
  50 #define INTCP_PA_ETH_BASE               0xc8000000
  51 #define INTCP_ETH_SIZE                  0x10
  52
  53 #define INTCP_VA_CTRL_BASE              0xfcb00000
  54 #define INTCP_FLASHPROG                 0x04
  55 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
  56 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
  57
  58 /*
  59  * Logical      Physical
  60  * f1000000     10000000        Core module registers
  61  * f1100000     11000000        System controller registers
  62  * f1200000     12000000        EBI registers
  63  * f1300000     13000000        Counter/Timer
  64  * f1400000     14000000        Interrupt controller
  65  * f1600000     16000000        UART 0
  66  * f1700000     17000000        UART 1
  67  * f1a00000     1a000000        Debug LEDs
  68  * f1b00000     1b000000        GPIO
  69  */
  70
  71 static struct map_desc intcp_io_desc[] __initdata = {
  72  { IO_ADDRESS(INTEGRATOR_HDR_BASE),   INTEGRATOR_HDR_BASE,   SZ_4K,  MT_DEVICE },
  73  { IO_ADDRESS(INTEGRATOR_SC_BASE),    INTEGRATOR_SC_BASE,    SZ_4K,  MT_DEVICE },
  74  { IO_ADDRESS(INTEGRATOR_EBI_BASE),   INTEGRATOR_EBI_BASE,   SZ_4K,  MT_DEVICE },
  75  { IO_ADDRESS(INTEGRATOR_CT_BASE),    INTEGRATOR_CT_BASE,    SZ_4K,  MT_DEVICE },
  76  { IO_ADDRESS(INTEGRATOR_IC_BASE),    INTEGRATOR_IC_BASE,    SZ_4K,  MT_DEVICE },
  77  { IO_ADDRESS(INTEGRATOR_UART0_BASE), INTEGRATOR_UART0_BASE, SZ_4K,  MT_DEVICE },
  78  { IO_ADDRESS(INTEGRATOR_UART1_BASE), INTEGRATOR_UART1_BASE, SZ_4K,  MT_DEVICE },
  79  { IO_ADDRESS(INTEGRATOR_DBG_BASE),   INTEGRATOR_DBG_BASE,   SZ_4K,  MT_DEVICE },
  80  { IO_ADDRESS(INTEGRATOR_GPIO_BASE),  INTEGRATOR_GPIO_BASE,  SZ_4K,  MT_DEVICE },
  81  { 0xfc900000, 0xc9000000, SZ_4K, MT_DEVICE },
  82  { 0xfca00000, 0xca000000, SZ_4K, MT_DEVICE },
  83  { 0xfcb00000, 0xcb000000, SZ_4K, MT_DEVICE },
  84 };
  85
  86 static void __init intcp_map_io(void)
  87 {
  88         iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
  89 }
  90
  91 #define cic_writel      __raw_writel
  92 #define cic_readl       __raw_readl
  93 #define pic_writel      __raw_writel
  94 #define pic_readl       __raw_readl
  95 #define sic_writel      __raw_writel
  96 #define sic_readl       __raw_readl
  97
  98 static void cic_mask_irq(unsigned int irq)
  99 {
 100         irq -= IRQ_CIC_START;
 101         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
 102 }
 103
 104 static void cic_unmask_irq(unsigned int irq)
 105 {
 106         irq -= IRQ_CIC_START;
 107         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
 108 }
 109
 110 static struct irqchip cic_chip = {
 111         .ack    = cic_mask_irq,
 112         .mask   = cic_mask_irq,
 113         .unmask = cic_unmask_irq,
 114 };
 115
 116 static void pic_mask_irq(unsigned int irq)
 117 {
 118         irq -= IRQ_PIC_START;
 119         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
 120 }
 121
 122 static void pic_unmask_irq(unsigned int irq)
 123 {
 124         irq -= IRQ_PIC_START;
 125         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
 126 }
 127
 128 static struct irqchip pic_chip = {
 129         .ack    = pic_mask_irq,
 130         .mask   = pic_mask_irq,
 131         .unmask = pic_unmask_irq,
 132 };
 133
 134 static void sic_mask_irq(unsigned int irq)
 135 {
 136         irq -= IRQ_SIC_START;
 137         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
 138 }
 139
 140 static void sic_unmask_irq(unsigned int irq)
 141 {
 142         irq -= IRQ_SIC_START;
 143         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
 144 }
 145
 146 static struct irqchip sic_chip = {
 147         .ack    = sic_mask_irq,
 148         .mask   = sic_mask_irq,
 149         .unmask = sic_unmask_irq,
 150 };
 151
 152 static void
 153 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
 154 {
 155         unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
 156
 157         if (status == 0) {
 158                 do_bad_IRQ(irq, desc, regs);
 159                 return;
 160         }
 161
 162         do {
 163                 irq = ffs(status) - 1;
 164                 status &= ~(1 << irq);
 165
 166                 irq += IRQ_SIC_START;
 167
 168                 desc = irq_desc + irq;
 169                 desc->handle(irq, desc, regs);
 170         } while (status);
 171 }
 172
 173 static void __init intcp_init_irq(void)
 174 {
 175         unsigned int i;
 176
 177         /*
 178          * Disable all interrupt sources
 179          */
 180         pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
 181         pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
 182
 183         for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
 184                 if (i == 11)
 185                         i = 22;
 186                 if (i == IRQ_CP_CPPLDINT)
 187                         i++;
 188                 if (i == 29)
 189                         break;
 190                 set_irq_chip(i, &pic_chip);
 191                 set_irq_handler(i, do_level_IRQ);
 192                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 193         }
 194
 195         cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
 196         cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
 197
 198         for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
 199                 set_irq_chip(i, &cic_chip);
 200                 set_irq_handler(i, do_level_IRQ);
 201                 set_irq_flags(i, IRQF_VALID);
 202         }
 203
 204         sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
 205         sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
 206
 207         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 208                 set_irq_chip(i, &sic_chip);
 209                 set_irq_handler(i, do_level_IRQ);
 210                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 211         }
 212
 213         set_irq_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
 214         pic_unmask_irq(IRQ_CP_CPPLDINT);
 215 }
 216
 217 /*
 218  * Clock handling
 219  */
 220 #define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
 221 #define CM_AUXOSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+0x1c)
 222
 223 static const struct icst525_params cp_auxvco_params = {
 224         .ref            = 24000,
 225         .vco_max        = 320000,
 226         .vd_min         = 8,
 227         .vd_max         = 263,
 228         .rd_min         = 3,
 229         .rd_max         = 65,
 230 };
 231
 232 static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco)
 233 {
 234         u32 val;
 235
 236         val = readl(CM_AUXOSC) & ~0x7ffff;
 237         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 238
 239         writel(0xa05f, CM_LOCK);
 240         writel(val, CM_AUXOSC);
 241         writel(0, CM_LOCK);
 242 }
 243
 244 static struct clk cp_clcd_clk = {
 245         .name   = "CLCDCLK",
 246         .params = &cp_auxvco_params,
 247         .setvco = cp_auxvco_set,
 248 };
 249
 250 static struct clk cp_mmci_clk = {
 251         .name   = "MCLK",
 252         .rate   = 14745600,
 253 };
 254
 255 /*
 256  * Flash handling.
 257  */
 258 static int intcp_flash_init(void)
 259 {
 260         u32 val;
 261
 262         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 263         val |= CINTEGRATOR_FLASHPROG_FLWREN;
 264         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 265
 266         return 0;
 267 }
 268
 269 static void intcp_flash_exit(void)
 270 {
 271         u32 val;
 272
 273         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 274         val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
 275         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 276 }
 277
 278 static void intcp_flash_set_vpp(int on)
 279 {
 280         u32 val;
 281
 282         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 283         if (on)
 284                 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
 285         else
 286                 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
 287         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 288 }
 289
 290 static struct flash_platform_data intcp_flash_data = {
 291         .map_name       = "cfi_probe",
 292         .width          = 4,
 293         .init           = intcp_flash_init,
 294         .exit           = intcp_flash_exit,
 295         .set_vpp        = intcp_flash_set_vpp,
 296 };
 297
 298 static struct resource intcp_flash_resource = {
 299         .start          = INTCP_PA_FLASH_BASE,
 300         .end            = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
 301         .flags          = IORESOURCE_MEM,
 302 };
 303
 304 static struct platform_device intcp_flash_device = {
 305         .name           = "armflash",
 306         .id             = 0,
 307         .dev            = {
 308                 .platform_data  = &intcp_flash_data,
 309         },
 310         .num_resources  = 1,
 311         .resource       = &intcp_flash_resource,
 312 };
 313
 314 static struct resource smc91x_resources[] = {
 315         [0] = {
 316                 .start  = INTCP_PA_ETH_BASE,
 317                 .end    = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1,
 318                 .flags  = IORESOURCE_MEM,
 319         },
 320         [1] = {
 321                 .start  = IRQ_CP_ETHINT,
 322                 .end    = IRQ_CP_ETHINT,
 323                 .flags  = IORESOURCE_IRQ,
 324         },
 325 };
 326
 327 static struct platform_device smc91x_device = {
 328         .name           = "smc91x",
 329         .id             = 0,
 330         .num_resources  = ARRAY_SIZE(smc91x_resources),
 331         .resource       = smc91x_resources,
 332 };
 333
 334 static struct platform_device *intcp_devs[] __initdata = {
 335         &intcp_flash_device,
 336         &smc91x_device,
 337 };
 338
 339 /*
 340  * It seems that the card insertion interrupt remains active after
 341  * we've acknowledged it.  We therefore ignore the interrupt, and
 342  * rely on reading it from the SIC.  This also means that we must
 343  * clear the latched interrupt.
 344  */
 345 static unsigned int mmc_status(struct device *dev)
 346 {
 347         unsigned int status = readl(0xfca00004);
 348         writel(8, 0xfcb00008);
 349
 350         return status & 8;
 351 }
 352
 353 static struct mmc_platform_data mmc_data = {
 354         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 355         .status         = mmc_status,
 356 };
 357
 358 static struct amba_device mmc_device = {
 359         .dev            = {
 360                 .bus_id = "mb:1c",
 361                 .platform_data = &mmc_data,
 362         },
 363         .res            = {
 364                 .start  = INTCP_PA_MMC_BASE,
 365                 .end    = INTCP_PA_MMC_BASE + SZ_4K - 1,
 366                 .flags  = IORESOURCE_MEM,
 367         },
 368         .irq            = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
 369         .periphid       = 0,
 370 };
 371
 372 static struct amba_device aaci_device = {
 373         .dev            = {
 374                 .bus_id = "mb:1d",
 375         },
 376         .res            = {
 377                 .start  = INTCP_PA_AACI_BASE,
 378                 .end    = INTCP_PA_AACI_BASE + SZ_4K - 1,
 379                 .flags  = IORESOURCE_MEM,
 380         },
 381         .irq            = { IRQ_CP_AACIINT, NO_IRQ },
 382         .periphid       = 0,
 383 };
 384
 385 static struct amba_device clcd_device = {
 386         .dev            = {
 387                 .bus_id = "mb:c0",
 388                 .coherent_dma_mask = ~0,
 389         },
 390         .res            = {
 391                 .start  = INTCP_PA_CLCD_BASE,
 392                 .end    = INTCP_PA_CLCD_BASE + SZ_4K - 1,
 393                 .flags  = IORESOURCE_MEM,
 394         },
 395         .dma_mask       = ~0,
 396         .irq            = { IRQ_CP_CLCDCINT, NO_IRQ },
 397         .periphid       = 0,
 398 };
 399
 400 static struct amba_device *amba_devs[] __initdata = {
 401         &mmc_device,
 402         &aaci_device,
 403         &clcd_device,
 404 };
 405
 406 static void __init intcp_init(void)
 407 {
 408         int i;
 409
 410         clk_register(&cp_clcd_clk);
 411         clk_register(&cp_mmci_clk);
 412
 413         platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
 414
 415         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 416                 struct amba_device *d = amba_devs[i];
 417                 amba_device_register(d, &iomem_resource);
 418         }
 419 }
 420
 421 #define TIMER_CTRL_IE   (1 << 5)                        /* Interrupt Enable */
 422
 423 static void __init intcp_init_time(void)
 424 {
 425         integrator_time_init(1000000 / HZ, TIMER_CTRL_IE);
 426 }
 427
 428 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
 429         MAINTAINER("ARM Ltd/Deep Blue Solutions Ltd")
 430         BOOT_MEM(0x00000000, 0x16000000, 0xf1600000)
 431         BOOT_PARAMS(0x00000100)
 432         MAPIO(intcp_map_io)
 433         INITIRQ(intcp_init_irq)
 434         INITTIME(intcp_init_time)
 435         INIT_MACHINE(intcp_init)
 436 MACHINE_END