arch/arm/mach-ixp2000/core.c

   1 /*
   2  * arch/arm/mach-ixp2000/common.c
   3  *
   4  * Common routines used by all IXP2400/2800 based platforms.
   5  *
   6  * Author: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2004 (C) MontaVista Software, Inc.
   9  *
  10  * Based on work Copyright (C) 2002-2003 Intel Corporation
  11  *
  12  * This file is licensed under the terms of the GNU General Public
  13  * License version 2. This program is licensed "as is" without any
  14  * warranty of any kind, whether express or implied.
  15  */
  16
  17 #include <linux/config.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/sched.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/serial.h>
  24 #include <linux/tty.h>
  25 #include <linux/bitops.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/mm.h>
  28
  29 #include <asm/types.h>
  30 #include <asm/setup.h>
  31 #include <asm/memory.h>
  32 #include <asm/hardware.h>
  33 #include <asm/mach-types.h>
  34 #include <asm/irq.h>
  35 #include <asm/system.h>
  36 #include <asm/tlbflush.h>
  37 #include <asm/pgtable.h>
  38
  39 #include <asm/mach/map.h>
  40 #include <asm/mach/time.h>
  41 #include <asm/mach/irq.h>
  42
  43 static DEFINE_SPINLOCK(ixp2000_slowport_lock);
  44 static unsigned long ixp2000_slowport_irq_flags;
  45
  46 /*************************************************************************
  47  * Slowport access routines
  48  *************************************************************************/
  49 void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
  50 {
  51
  52         spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
  53
  54         old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
  55         old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
  56         old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
  57         old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
  58         old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
  59
  60         ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
  61         ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
  62         ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
  63         ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
  64         ixp2000_reg_write(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
  65 }
  66
  67 void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
  68 {
  69         ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
  70         ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
  71         ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
  72         ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
  73         ixp2000_reg_write(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
  74
  75         spin_unlock_irqrestore(&ixp2000_slowport_lock,
  76                                         ixp2000_slowport_irq_flags);
  77 }
  78
  79 /*************************************************************************
  80  * Chip specific mappings shared by all IXP2000 systems
  81  *************************************************************************/
  82 static struct map_desc ixp2000_small_io_desc[] __initdata = {
  83         {
  84                 .virtual        = IXP2000_GLOBAL_REG_VIRT_BASE,
  85                 .physical       = IXP2000_GLOBAL_REG_PHYS_BASE,
  86                 .length         = IXP2000_GLOBAL_REG_SIZE,
  87                 .type           = MT_DEVICE
  88         }, {
  89                 .virtual        = IXP2000_GPIO_VIRT_BASE,
  90                 .physical       = IXP2000_GPIO_PHYS_BASE,
  91                 .length         = IXP2000_GPIO_SIZE,
  92                 .type           = MT_DEVICE
  93         }, {
  94                 .virtual        = IXP2000_TIMER_VIRT_BASE,
  95                 .physical       = IXP2000_TIMER_PHYS_BASE,
  96                 .length         = IXP2000_TIMER_SIZE,
  97                 .type           = MT_DEVICE
  98         }, {
  99                 .virtual        = IXP2000_UART_VIRT_BASE,
 100                 .physical       = IXP2000_UART_PHYS_BASE,
 101                 .length         = IXP2000_UART_SIZE,
 102                 .type           = MT_DEVICE
 103         }, {
 104                 .virtual        = IXP2000_SLOWPORT_CSR_VIRT_BASE,
 105                 .physical       = IXP2000_SLOWPORT_CSR_PHYS_BASE,
 106                 .length         = IXP2000_SLOWPORT_CSR_SIZE,
 107                 .type           = MT_DEVICE
 108         }, {
 109                 .virtual        = IXP2000_INTCTL_VIRT_BASE,
 110                 .physical       = IXP2000_INTCTL_PHYS_BASE,
 111                 .length         = IXP2000_INTCTL_SIZE,
 112                 .type           = MT_DEVICE
 113         }, {
 114                 .virtual        = IXP2000_PCI_CREG_VIRT_BASE,
 115                 .physical       = IXP2000_PCI_CREG_PHYS_BASE,
 116                 .length         = IXP2000_PCI_CREG_SIZE,
 117                 .type           = MT_DEVICE
 118         }
 119 };
 120
 121 static struct map_desc ixp2000_large_io_desc[] __initdata = {
 122         {
 123                 .virtual        = IXP2000_PCI_CSR_VIRT_BASE,
 124                 .physical       = IXP2000_PCI_CSR_PHYS_BASE,
 125                 .length         = IXP2000_PCI_CSR_SIZE,
 126                 .type           = MT_DEVICE
 127         }, {
 128                 .virtual        = IXP2000_PCI_IO_VIRT_BASE,
 129                 .physical       = IXP2000_PCI_IO_PHYS_BASE,
 130                 .length         = IXP2000_PCI_IO_SIZE,
 131                 .type           = MT_DEVICE
 132         }, {
 133                 .virtual        = IXP2000_PCI_CFG0_VIRT_BASE,
 134                 .physical       = IXP2000_PCI_CFG0_PHYS_BASE,
 135                 .length         = IXP2000_PCI_CFG0_SIZE,
 136                 .type           = MT_DEVICE
 137         }, {
 138                 .virtual        = IXP2000_PCI_CFG1_VIRT_BASE,
 139                 .physical       = IXP2000_PCI_CFG1_PHYS_BASE,
 140                 .length         = IXP2000_PCI_CFG1_SIZE,
 141                 .type           = MT_DEVICE
 142         }
 143 };
 144
 145 static struct uart_port ixp2000_serial_port = {
 146         .membase        = (char *)(IXP2000_UART_VIRT_BASE + 3),
 147         .mapbase        = IXP2000_UART_PHYS_BASE + 3,
 148         .irq            = IRQ_IXP2000_UART,
 149         .flags          = UPF_SKIP_TEST,
 150         .iotype         = UPIO_MEM,
 151         .regshift       = 2,
 152         .uartclk        = 50000000,
 153         .line           = 0,
 154         .type           = PORT_XSCALE,
 155         .fifosize       = 16
 156 };
 157
 158 void __init ixp2000_map_io(void)
 159 {
 160         iotable_init(ixp2000_small_io_desc, ARRAY_SIZE(ixp2000_small_io_desc));
 161         iotable_init(ixp2000_large_io_desc, ARRAY_SIZE(ixp2000_large_io_desc));
 162         early_serial_setup(&ixp2000_serial_port);
 163
 164         /* Set slowport to 8-bit mode.  */
 165         ixp2000_reg_write(IXP2000_SLOWPORT_FRM, 1);
 166 }
 167
 168 /*************************************************************************
 169  * Timer-tick functions for IXP2000
 170  *************************************************************************/
 171 static unsigned ticks_per_jiffy;
 172 static unsigned ticks_per_usec;
 173 static unsigned next_jiffy_time;
 174
 175 unsigned long ixp2000_gettimeoffset (void)
 176 {
 177         unsigned long offset;
 178
 179         offset = next_jiffy_time - *IXP2000_T4_CSR;
 180
 181         return offset / ticks_per_usec;
 182 }
 183
 184 static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 185 {
 186         write_seqlock(&xtime_lock);
 187
 188         /* clear timer 1 */
 189         ixp2000_reg_write(IXP2000_T1_CLR, 1);
 190
 191         while ((next_jiffy_time - *IXP2000_T4_CSR) > ticks_per_jiffy) {
 192                 timer_tick(regs);
 193                 next_jiffy_time -= ticks_per_jiffy;
 194         }
 195
 196         write_sequnlock(&xtime_lock);
 197
 198         return IRQ_HANDLED;
 199 }
 200
 201 static struct irqaction ixp2000_timer_irq = {
 202         .name           = "IXP2000 Timer Tick",
 203         .flags          = SA_INTERRUPT,
 204         .handler        = ixp2000_timer_interrupt
 205 };
 206
 207 void __init ixp2000_init_time(unsigned long tick_rate)
 208 {
 209         ixp2000_reg_write(IXP2000_T1_CLR, 0);
 210         ixp2000_reg_write(IXP2000_T4_CLR, 0);
 211
 212         ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
 213         ticks_per_usec = tick_rate / 1000000;
 214
 215         ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy);
 216         ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
 217
 218         /*
 219          * We use T4 as a monotonic counter to track missed jiffies
 220          */
 221         ixp2000_reg_write(IXP2000_T4_CLD, -1);
 222         ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7));
 223         next_jiffy_time = 0xffffffff - ticks_per_jiffy;
 224
 225         /* register for interrupt */
 226         setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
 227 }
 228
 229 /*************************************************************************
 230  * GPIO helpers
 231  *************************************************************************/
 232 static unsigned long GPIO_IRQ_rising_edge;
 233 static unsigned long GPIO_IRQ_falling_edge;
 234 static unsigned long GPIO_IRQ_level_low;
 235 static unsigned long GPIO_IRQ_level_high;
 236
 237 void gpio_line_config(int line, int style)
 238 {
 239         unsigned long flags;
 240
 241         local_irq_save(flags);
 242
 243         if(style == GPIO_OUT) {
 244                 /* if it's an output, it ain't an interrupt anymore */
 245                 ixp2000_reg_write(IXP2000_GPIO_PDSR, (1 << line));
 246                 GPIO_IRQ_falling_edge &= ~(1 << line);
 247                 GPIO_IRQ_rising_edge &= ~(1 << line);
 248                 GPIO_IRQ_level_low &= ~(1 << line);
 249                 GPIO_IRQ_level_high &= ~(1 << line);
 250                 ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
 251                 ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
 252                 ixp2000_reg_write(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
 253                 ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
 254                 irq_desc[line+IRQ_IXP2000_GPIO0].valid = 0;
 255         } else if(style == GPIO_IN) {
 256                 ixp2000_reg_write(IXP2000_GPIO_PDCR, (1 << line));
 257         }
 258
 259         local_irq_restore(flags);
 260 }
 261
 262
 263 /*************************************************************************
 264  * IRQ handling IXP2000
 265  *************************************************************************/
 266 static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
 267 {
 268         int i;
 269         unsigned long status = *IXP2000_GPIO_INST;
 270
 271         for (i = 0; i <= 7; i++) {
 272                 if (status & (1<<i)) {
 273                         desc = irq_desc + i + IRQ_IXP2000_GPIO0;
 274                         desc->handle(i + IRQ_IXP2000_GPIO0, desc, regs);
 275                 }
 276         }
 277 }
 278
 279 static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
 280 {
 281         ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 282         ixp2000_reg_write(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
 283 }
 284
 285 static void ixp2000_GPIO_irq_mask(unsigned int irq)
 286 {
 287         ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 288 }
 289
 290 static void ixp2000_GPIO_irq_unmask(unsigned int irq)
 291 {
 292         ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 293 }
 294
 295 static struct irqchip ixp2000_GPIO_irq_chip = {
 296         .ack    = ixp2000_GPIO_irq_mask_ack,
 297         .mask   = ixp2000_GPIO_irq_mask,
 298         .unmask = ixp2000_GPIO_irq_unmask
 299 };
 300
 301 static void ixp2000_pci_irq_mask(unsigned int irq)
 302 {
 303         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
 304         if (irq == IRQ_IXP2000_PCIA)
 305                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
 306         else if (irq == IRQ_IXP2000_PCIB)
 307                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
 308 }
 309
 310 static void ixp2000_pci_irq_unmask(unsigned int irq)
 311 {
 312         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
 313         if (irq == IRQ_IXP2000_PCIA)
 314                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
 315         else if (irq == IRQ_IXP2000_PCIB)
 316                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
 317 }
 318
 319 static struct irqchip ixp2000_pci_irq_chip = {
 320         .ack    = ixp2000_pci_irq_mask,
 321         .mask   = ixp2000_pci_irq_mask,
 322         .unmask = ixp2000_pci_irq_unmask
 323 };
 324
 325 static void ixp2000_irq_mask(unsigned int irq)
 326 {
 327         ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
 328 }
 329
 330 static void ixp2000_irq_unmask(unsigned int irq)
 331 {
 332         ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET,  (1 << irq));
 333 }
 334
 335 static struct irqchip ixp2000_irq_chip = {
 336         .ack    = ixp2000_irq_mask,
 337         .mask   = ixp2000_irq_mask,
 338         .unmask = ixp2000_irq_unmask
 339 };
 340
 341 void __init ixp2000_init_irq(void)
 342 {
 343         int irq;
 344
 345         /*
 346          * Mask all sources
 347          */
 348         ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
 349         ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
 350
 351         /* clear all GPIO edge/level detects */
 352         ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
 353         ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
 354         ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
 355         ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
 356         ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
 357
 358         /* clear PCI interrupt sources */
 359         ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
 360
 361         /*
 362          * Certain bits in the IRQ status register of the
 363          * IXP2000 are reserved. Instead of trying to map
 364          * things non 1:1 from bit position to IRQ number,
 365          * we mark the reserved IRQs as invalid. This makes
 366          * our mask/unmask code much simpler.
 367          */
 368         for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
 369                 if((1 << irq) & IXP2000_VALID_IRQ_MASK) {
 370                         set_irq_chip(irq, &ixp2000_irq_chip);
 371                         set_irq_handler(irq, do_level_IRQ);
 372                         set_irq_flags(irq, IRQF_VALID);
 373                 } else set_irq_flags(irq, 0);
 374         }
 375
 376         /*
 377          * GPIO IRQs are invalid until someone sets the interrupt mode
 378          * by calling gpio_line_set();
 379          */
 380         for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
 381                 set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
 382                 set_irq_handler(irq, do_level_IRQ);
 383                 set_irq_flags(irq, 0);
 384         }
 385         set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
 386
 387         /*
 388          * Enable PCI irq
 389          */
 390         ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
 391         for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
 392                 set_irq_chip(irq, &ixp2000_pci_irq_chip);
 393                 set_irq_handler(irq, do_level_IRQ);
 394                 set_irq_flags(irq, IRQF_VALID);
 395         }
 396 }
 397