arch/arm/mach-ixp2000/ixdp2x01.c

   1 /*
   2  * arch/arm/mach-ixp2000/ixdp2x01.c
   3  *
   4  * Code common to Intel IXDP2401 and IXDP2801 platforms
   5  *
   6  * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
   7  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   8  *
   9  * Copyright (C) 2002-2003 Intel Corp.
  10  * Copyright (C) 2003-2004 MontaVista Software, Inc.
  11  *
  12  *  This program is free software; you can redistribute  it and/or modify it
  13  *  under  the terms of  the GNU General  Public License as published by the
  14  *  Free Software Foundation;  either version 2 of the  License, or (at your
  15  *  option) any later version.
  16  */
  17
  18 #include <linux/config.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/mm.h>
  22 #include <linux/sched.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/bitops.h>
  25 #include <linux/pci.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/delay.h>
  29 #include <linux/serial.h>
  30 #include <linux/tty.h>
  31 #include <linux/serial_core.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/serial_8250.h>
  34
  35 #include <asm/io.h>
  36 #include <asm/irq.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/page.h>
  39 #include <asm/system.h>
  40 #include <asm/hardware.h>
  41 #include <asm/mach-types.h>
  42
  43 #include <asm/mach/pci.h>
  44 #include <asm/mach/map.h>
  45 #include <asm/mach/irq.h>
  46 #include <asm/mach/time.h>
  47 #include <asm/mach/arch.h>
  48 #include <asm/mach/flash.h>
  49
  50 /*************************************************************************
  51  * IXDP2x01 IRQ Handling
  52  *************************************************************************/
  53 static void ixdp2x01_irq_mask(unsigned int irq)
  54 {
  55         ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG,
  56                                 IXP2000_BOARD_IRQ_MASK(irq));
  57 }
  58
  59 static void ixdp2x01_irq_unmask(unsigned int irq)
  60 {
  61         ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG,
  62                                 IXP2000_BOARD_IRQ_MASK(irq));
  63 }
  64
  65 static u32 valid_irq_mask;
  66
  67 static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
  68 {
  69         u32 ex_interrupt;
  70         int i;
  71
  72         desc->chip->mask(irq);
  73
  74         ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask;
  75
  76         if (!ex_interrupt) {
  77                 printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n");
  78                 return;
  79         }
  80
  81         for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
  82                 if (ex_interrupt & (1 << i)) {
  83                         struct irqdesc *cpld_desc;
  84                         int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
  85                         cpld_desc = irq_desc + cpld_irq;
  86                         desc_handle_irq(cpld_irq, cpld_desc, regs);
  87                 }
  88         }
  89
  90         desc->chip->unmask(irq);
  91 }
  92
  93 static struct irqchip ixdp2x01_irq_chip = {
  94         .mask   = ixdp2x01_irq_mask,
  95         .ack    = ixdp2x01_irq_mask,
  96         .unmask = ixdp2x01_irq_unmask
  97 };
  98
  99 /*
 100  * We only do anything if we are the master NPU on the board.
 101  * The slave NPU only has the ethernet chip going directly to
 102  * the PCIB interrupt input.
 103  */
 104 void __init ixdp2x01_init_irq(void)
 105 {
 106         int irq = 0;
 107
 108         /* initialize chip specific interrupts */
 109         ixp2000_init_irq();
 110
 111         if (machine_is_ixdp2401())
 112                 valid_irq_mask = IXDP2401_VALID_IRQ_MASK;
 113         else
 114                 valid_irq_mask = IXDP2801_VALID_IRQ_MASK;
 115
 116         /* Mask all interrupts from CPLD, disable simulation */
 117         ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
 118         ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0);
 119
 120         for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
 121                 if (irq & valid_irq_mask) {
 122                         set_irq_chip(irq, &ixdp2x01_irq_chip);
 123                         set_irq_handler(irq, do_level_IRQ);
 124                         set_irq_flags(irq, IRQF_VALID);
 125                 } else {
 126                         set_irq_flags(irq, 0);
 127                 }
 128         }
 129
 130         /* Hook into PCI interrupts */
 131         set_irq_chained_handler(IRQ_IXP2000_PCIB, &ixdp2x01_irq_handler);
 132 }
 133
 134
 135 /*************************************************************************
 136  * IXDP2x01 memory map
 137  *************************************************************************/
 138 static struct map_desc ixdp2x01_io_desc __initdata = {
 139         .virtual        = IXDP2X01_VIRT_CPLD_BASE,
 140         .pfn            = __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE),
 141         .length         = IXDP2X01_CPLD_REGION_SIZE,
 142         .type           = MT_DEVICE
 143 };
 144
 145 static void __init ixdp2x01_map_io(void)
 146 {
 147         ixp2000_map_io();
 148         iotable_init(&ixdp2x01_io_desc, 1);
 149 }
 150
 151
 152 /*************************************************************************
 153  * IXDP2x01 serial ports
 154  *************************************************************************/
 155 static struct plat_serial8250_port ixdp2x01_serial_port1[] = {
 156         {
 157                 .mapbase        = (unsigned long)IXDP2X01_UART1_PHYS_BASE,
 158                 .membase        = (char *)IXDP2X01_UART1_VIRT_BASE,
 159                 .irq            = IRQ_IXDP2X01_UART1,
 160                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 161                 .iotype         = UPIO_MEM32,
 162                 .regshift       = 2,
 163                 .uartclk        = IXDP2X01_UART_CLK,
 164         },
 165         { }
 166 };
 167
 168 static struct resource ixdp2x01_uart_resource1 = {
 169         .start          = IXDP2X01_UART1_PHYS_BASE,
 170         .end            = IXDP2X01_UART1_PHYS_BASE + 0xffff,
 171         .flags          = IORESOURCE_MEM,
 172 };
 173
 174 static struct platform_device ixdp2x01_serial_device1 = {
 175         .name           = "serial8250",
 176         .id             = PLAT8250_DEV_PLATFORM1,
 177         .dev            = {
 178                 .platform_data          = ixdp2x01_serial_port1,
 179         },
 180         .num_resources  = 1,
 181         .resource       = &ixdp2x01_uart_resource1,
 182 };
 183
 184 static struct plat_serial8250_port ixdp2x01_serial_port2[] = {
 185         {
 186                 .mapbase        = (unsigned long)IXDP2X01_UART2_PHYS_BASE,
 187                 .membase        = (char *)IXDP2X01_UART2_VIRT_BASE,
 188                 .irq            = IRQ_IXDP2X01_UART2,
 189                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 190                 .iotype         = UPIO_MEM32,
 191                 .regshift       = 2,
 192                 .uartclk        = IXDP2X01_UART_CLK,
 193         },
 194         { }
 195 };
 196
 197 static struct resource ixdp2x01_uart_resource2 = {
 198         .start          = IXDP2X01_UART2_PHYS_BASE,
 199         .end            = IXDP2X01_UART2_PHYS_BASE + 0xffff,
 200         .flags          = IORESOURCE_MEM,
 201 };
 202
 203 static struct platform_device ixdp2x01_serial_device2 = {
 204         .name           = "serial8250",
 205         .id             = PLAT8250_DEV_PLATFORM2,
 206         .dev            = {
 207                 .platform_data          = ixdp2x01_serial_port2,
 208         },
 209         .num_resources  = 1,
 210         .resource       = &ixdp2x01_uart_resource2,
 211 };
 212
 213 static void ixdp2x01_uart_init(void)
 214 {
 215         platform_device_register(&ixdp2x01_serial_device1);
 216         platform_device_register(&ixdp2x01_serial_device2);
 217 }
 218
 219
 220 /*************************************************************************
 221  * IXDP2x01 timer tick configuration
 222  *************************************************************************/
 223 static unsigned int ixdp2x01_clock;
 224
 225 static int __init ixdp2x01_clock_setup(char *str)
 226 {
 227         ixdp2x01_clock = simple_strtoul(str, NULL, 10);
 228
 229         return 1;
 230 }
 231
 232 __setup("ixdp2x01_clock=", ixdp2x01_clock_setup);
 233
 234 static void __init ixdp2x01_timer_init(void)
 235 {
 236         if (!ixdp2x01_clock)
 237                 ixdp2x01_clock = 50000000;
 238
 239         ixp2000_init_time(ixdp2x01_clock);
 240 }
 241
 242 static struct sys_timer ixdp2x01_timer = {
 243         .init           = ixdp2x01_timer_init,
 244         .offset         = ixp2000_gettimeoffset,
 245 };
 246
 247 /*************************************************************************
 248  * IXDP2x01 PCI
 249  *************************************************************************/
 250 void __init ixdp2x01_pci_preinit(void)
 251 {
 252         ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000);
 253         ixp2000_pci_preinit();
 254         pcibios_setup("firmware");
 255 }
 256
 257 #define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
 258
 259 static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 260 {
 261         u8 bus = dev->bus->number;
 262         u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
 263         struct pci_bus *tmp_bus = dev->bus;
 264
 265         /* Primary bus, no interrupts here */
 266         if (bus == 0) {
 267                 return -1;
 268         }
 269
 270         /* Lookup first leaf in bus tree */
 271         while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) {
 272                 tmp_bus = tmp_bus->parent;
 273         }
 274
 275         /* Select between known bridges */
 276         switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
 277         /* Device is located after first MB bridge */
 278         case 0x0008:
 279                 if (tmp_bus == dev->bus) {
 280                         /* Device is located directy after first MB bridge */
 281                         switch (devpin) {
 282                         case DEVPIN(1, 1):      /* Onboard 82546 ch 0 */
 283                                 if (machine_is_ixdp2401())
 284                                         return IRQ_IXDP2401_INTA_82546;
 285                                 return -1;
 286                         case DEVPIN(1, 2):      /* Onboard 82546 ch 1 */
 287                                 if (machine_is_ixdp2401())
 288                                         return IRQ_IXDP2401_INTB_82546;
 289                                 return -1;
 290                         case DEVPIN(0, 1):      /* PMC INTA# */
 291                                 return IRQ_IXDP2X01_SPCI_PMC_INTA;
 292                         case DEVPIN(0, 2):      /* PMC INTB# */
 293                                 return IRQ_IXDP2X01_SPCI_PMC_INTB;
 294                         case DEVPIN(0, 3):      /* PMC INTC# */
 295                                 return IRQ_IXDP2X01_SPCI_PMC_INTC;
 296                         case DEVPIN(0, 4):      /* PMC INTD# */
 297                                 return IRQ_IXDP2X01_SPCI_PMC_INTD;
 298                         }
 299                 }
 300                 break;
 301         case 0x0010:
 302                 if (tmp_bus == dev->bus) {
 303                         /* Device is located directy after second MB bridge */
 304                         /* Secondary bus of second bridge */
 305                         switch (devpin) {
 306                         case DEVPIN(0, 1):      /* DB#0 */
 307                                 return IRQ_IXDP2X01_SPCI_DB_0;
 308                         case DEVPIN(1, 1):      /* DB#1 */
 309                                 return IRQ_IXDP2X01_SPCI_DB_1;
 310                         }
 311                 } else {
 312                         /* Device is located indirectly after second MB bridge */
 313                         /* Not supported now */
 314                 }
 315                 break;
 316         }
 317
 318         return -1;
 319 }
 320
 321
 322 static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys)
 323 {
 324         sys->mem_offset = 0xe0000000;
 325
 326         if (machine_is_ixdp2801() || machine_is_ixdp28x5())
 327                 sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16);
 328
 329         return ixp2000_pci_setup(nr, sys);
 330 }
 331
 332 struct hw_pci ixdp2x01_pci __initdata = {
 333         .nr_controllers = 1,
 334         .setup          = ixdp2x01_pci_setup,
 335         .preinit        = ixdp2x01_pci_preinit,
 336         .scan           = ixp2000_pci_scan_bus,
 337         .map_irq        = ixdp2x01_pci_map_irq,
 338 };
 339
 340 int __init ixdp2x01_pci_init(void)
 341 {
 342         if (machine_is_ixdp2401() || machine_is_ixdp2801() ||\
 343                 machine_is_ixdp28x5())
 344                 pci_common_init(&ixdp2x01_pci);
 345
 346         return 0;
 347 }
 348
 349 subsys_initcall(ixdp2x01_pci_init);
 350
 351 /*************************************************************************
 352  * IXDP2x01 Machine Intialization
 353  *************************************************************************/
 354 static struct flash_platform_data ixdp2x01_flash_platform_data = {
 355         .map_name       = "cfi_probe",
 356         .width          = 1,
 357 };
 358
 359 static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
 360 {
 361         ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
 362                 ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN));
 363         return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
 364 }
 365
 366 static struct ixp2000_flash_data ixdp2x01_flash_data = {
 367         .platform_data  = &ixdp2x01_flash_platform_data,
 368         .bank_setup     = ixdp2x01_flash_bank_setup
 369 };
 370
 371 static struct resource ixdp2x01_flash_resource = {
 372         .start          = 0xc4000000,
 373         .end            = 0xc4000000 + 0x01ffffff,
 374         .flags          = IORESOURCE_MEM,
 375 };
 376
 377 static struct platform_device ixdp2x01_flash = {
 378         .name           = "IXP2000-Flash",
 379         .id             = 0,
 380         .dev            = {
 381                 .platform_data = &ixdp2x01_flash_data,
 382         },
 383         .num_resources  = 1,
 384         .resource       = &ixdp2x01_flash_resource,
 385 };
 386
 387 static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = {
 388         .sda_pin        = IXDP2X01_GPIO_SDA,
 389         .scl_pin        = IXDP2X01_GPIO_SCL,
 390 };
 391
 392 static struct platform_device ixdp2x01_i2c_controller = {
 393         .name           = "IXP2000-I2C",
 394         .id             = 0,
 395         .dev            = {
 396                 .platform_data = &ixdp2x01_i2c_gpio_pins,
 397         },
 398         .num_resources  = 0
 399 };
 400
 401 static struct platform_device *ixdp2x01_devices[] __initdata = {
 402         &ixdp2x01_flash,
 403         &ixdp2x01_i2c_controller
 404 };
 405
 406 static void __init ixdp2x01_init_machine(void)
 407 {
 408         ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
 409                 (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN));
 410
 411         ixdp2x01_flash_data.nr_banks =
 412                 ((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1);
 413
 414         platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices));
 415         ixp2000_uart_init();
 416         ixdp2x01_uart_init();
 417 }
 418
 419
 420 #ifdef CONFIG_ARCH_IXDP2401
 421 MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
 422         /* Maintainer: MontaVista Software, Inc. */
 423         .phys_io        = IXP2000_UART_PHYS_BASE,
 424         .io_pg_offst    = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
 425         .boot_params    = 0x00000100,
 426         .map_io         = ixdp2x01_map_io,
 427         .init_irq       = ixdp2x01_init_irq,
 428         .timer          = &ixdp2x01_timer,
 429         .init_machine   = ixdp2x01_init_machine,
 430 MACHINE_END
 431 #endif
 432
 433 #ifdef CONFIG_ARCH_IXDP2801
 434 MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
 435         /* Maintainer: MontaVista Software, Inc. */
 436         .phys_io        = IXP2000_UART_PHYS_BASE,
 437         .io_pg_offst    = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
 438         .boot_params    = 0x00000100,
 439         .map_io         = ixdp2x01_map_io,
 440         .init_irq       = ixdp2x01_init_irq,
 441         .timer          = &ixdp2x01_timer,
 442         .init_machine   = ixdp2x01_init_machine,
 443 MACHINE_END
 444
 445 /*
 446  * IXDP28x5 is basically an IXDP2801 with a different CPU but Intel
 447  * changed the machine ID in the bootloader
 448  */
 449 MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform")
 450         /* Maintainer: MontaVista Software, Inc. */
 451         .phys_io        = IXP2000_UART_PHYS_BASE,
 452         .io_pg_offst    = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
 453         .boot_params    = 0x00000100,
 454         .map_io         = ixdp2x01_map_io,
 455         .init_irq       = ixdp2x01_init_irq,
 456         .timer          = &ixdp2x01_timer,
 457         .init_machine   = ixdp2x01_init_machine,
 458 MACHINE_END
 459 #endif
 460
 461