2 * arch/arm/mach-ixp4xx/common.c
4 * Generic code shared across all IXP4XX platforms
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/serial.h>
21 #include <linux/sched.h>
22 #include <linux/tty.h>
23 #include <linux/serial_core.h>
24 #include <linux/bootmem.h>
25 #include <linux/interrupt.h>
26 #include <linux/bitops.h>
27 #include <linux/time.h>
28 #include <linux/timex.h>
30 #include <asm/hardware.h>
31 #include <asm/uaccess.h>
33 #include <asm/pgtable.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/irq.h>
41 /*************************************************************************
42 * GPIO acces functions
43 *************************************************************************/
46 * Configure GPIO line for input, interrupt, or output operation
48 * TODO: Enable/disable the irq_desc based on interrupt or output mode.
49 * TODO: Should these be named ixp4xx_gpio_?
51 void gpio_line_config(u8 line, u32 style)
54 volatile u32 *int_reg;
57 enable = *IXP4XX_GPIO_GPOER;
59 if (style & IXP4XX_GPIO_OUT) {
60 enable &= ~((1) << line);
61 } else if (style & IXP4XX_GPIO_IN) {
62 enable |= ((1) << line);
64 switch (style & IXP4XX_GPIO_INTSTYLE_MASK)
66 case (IXP4XX_GPIO_ACTIVE_HIGH):
67 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
69 case (IXP4XX_GPIO_ACTIVE_LOW):
70 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
72 case (IXP4XX_GPIO_RISING_EDGE):
73 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
75 case (IXP4XX_GPIO_FALLING_EDGE):
76 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
78 case (IXP4XX_GPIO_TRANSITIONAL):
79 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
82 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
86 if (line >= 8) { /* pins 8-15 */
88 int_reg = IXP4XX_GPIO_GPIT2R;
91 int_reg = IXP4XX_GPIO_GPIT1R;
94 /* Clear the style for the appropriate pin */
95 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
96 (line * IXP4XX_GPIO_STYLE_SIZE));
98 /* Set the new style */
99 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
102 *IXP4XX_GPIO_GPOER = enable;
105 EXPORT_SYMBOL(gpio_line_config);
107 /*************************************************************************
108 * IXP4xx chipset I/O mapping
109 *************************************************************************/
110 static struct map_desc ixp4xx_io_desc[] __initdata = {
111 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
112 .virtual = IXP4XX_PERIPHERAL_BASE_VIRT,
113 .physical = IXP4XX_PERIPHERAL_BASE_PHYS,
114 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
116 }, { /* Expansion Bus Config Registers */
117 .virtual = IXP4XX_EXP_CFG_BASE_VIRT,
118 .physical = IXP4XX_EXP_CFG_BASE_PHYS,
119 .length = IXP4XX_EXP_CFG_REGION_SIZE,
121 }, { /* PCI Registers */
122 .virtual = IXP4XX_PCI_CFG_BASE_VIRT,
123 .physical = IXP4XX_PCI_CFG_BASE_PHYS,
124 .length = IXP4XX_PCI_CFG_REGION_SIZE,
129 void __init ixp4xx_map_io(void)
131 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
135 /*************************************************************************
136 * IXP4xx chipset IRQ handling
138 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
139 * (be it PCI or something else) configures that GPIO line
140 * as an IRQ. Also, we should use a different chip structure for
141 * level-based GPIO vs edge-based GPIO. Currently nobody needs this as
142 * all HW that's publically available uses level IRQs, so we'll
143 * worry about it if/when we have HW to test.
144 **************************************************************************/
145 static void ixp4xx_irq_mask(unsigned int irq)
147 *IXP4XX_ICMR &= ~(1 << irq);
150 static void ixp4xx_irq_mask_ack(unsigned int irq)
152 ixp4xx_irq_mask(irq);
155 static void ixp4xx_irq_unmask(unsigned int irq)
157 static int irq2gpio[NR_IRQS] = {
158 -1, -1, -1, -1, -1, -1, 0, 1,
159 -1, -1, -1, -1, -1, -1, -1, -1,
160 -1, -1, -1, 2, 3, 4, 5, 6,
161 7, 8, 9, 10, 11, 12, -1, -1,
163 int line = irq2gpio[irq];
166 * This only works for LEVEL gpio IRQs as per the IXP4xx developer's
167 * manual. If edge-triggered, need to move it to the mask_ack.
168 * Nobody seems to be using the edge-triggered mode on the GPIOs.
171 gpio_line_isr_clear(line);
173 *IXP4XX_ICMR |= (1 << irq);
176 static struct irqchip ixp4xx_irq_chip = {
177 .ack = ixp4xx_irq_mask_ack,
178 .mask = ixp4xx_irq_mask,
179 .unmask = ixp4xx_irq_unmask,
182 void __init ixp4xx_init_irq(void)
186 /* Route all sources to IRQ instead of FIQ */
189 /* Disable all interrupt */
192 for(i = 0; i < NR_IRQS; i++)
194 set_irq_chip(i, &ixp4xx_irq_chip);
195 set_irq_handler(i, do_level_IRQ);
196 set_irq_flags(i, IRQF_VALID);
201 /*************************************************************************
203 * We use OS timer1 on the CPU for the timer tick and the timestamp
204 * counter as a source of real clock ticks to account for missed jiffies.
205 *************************************************************************/
207 static unsigned volatile last_jiffy_time;
209 #define CLOCK_TICKS_PER_USEC (CLOCK_TICK_RATE / USEC_PER_SEC)
211 /* IRQs are disabled before entering here from do_gettimeofday() */
212 static unsigned long ixp4xx_gettimeoffset(void)
216 elapsed = *IXP4XX_OSTS - last_jiffy_time;
218 return elapsed / CLOCK_TICKS_PER_USEC;
221 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
223 /* Clear Pending Interrupt by writing '1' to it */
224 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
227 * Catch up with the real idea of time
231 last_jiffy_time += LATCH;
232 } while((*IXP4XX_OSTS - last_jiffy_time) > LATCH);
237 extern unsigned long (*gettimeoffset)(void);
239 static struct irqaction timer_irq = {
240 .name = "IXP4xx Timer Tick",
241 .flags = SA_INTERRUPT
244 void __init time_init(void)
246 gettimeoffset = ixp4xx_gettimeoffset;
247 timer_irq.handler = ixp4xx_timer_interrupt;
249 /* Clear Pending Interrupt by writing '1' to it */
250 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
252 /* Setup the Timer counter value */
253 *IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
255 /* Reset time-stamp counter */
259 /* Connect the interrupt handler and enable the interrupt */
260 setup_irq(IRQ_IXP4XX_TIMER1, &timer_irq);