arch/arm/mach-omap/dma.c

   1 /*
   2  * linux/arch/arm/omap/dma.c
   3  *
   4  * Copyright (C) 2003 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  *
   7  * Support functions for the OMAP internal DMA channels.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/sched.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/errno.h>
  20 #include <linux/interrupt.h>
  21
  22 #include <asm/system.h>
  23 #include <asm/irq.h>
  24 #include <asm/hardware.h>
  25 #include <asm/dma.h>
  26 #include <asm/io.h>
  27
  28 #define OMAP_DMA_ACTIVE         0x01
  29
  30 #define OMAP_DMA_CCR_EN         (1 << 7)
  31
  32 #define OMAP_FUNC_MUX_ARM_BASE  (0xfffe1000 + 0xec)
  33
  34 static int enable_1510_mode = 0;
  35
  36 struct omap_dma_lch {
  37         int dev_id;
  38         u16 saved_csr;
  39         u16 enabled_irqs;
  40         const char *dev_name;
  41         void (* callback)(int lch, u16 ch_status, void *data);
  42         void *data;
  43         long flags;
  44 };
  45
  46 static int dma_chan_count;
  47
  48 static spinlock_t dma_chan_lock;
  49 static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
  50
  51 const static u8 dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
  52         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
  53         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
  54         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
  55         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
  56         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
  57 };
  58
  59 static inline int get_gdma_dev(int req)
  60 {
  61         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
  62         int shift = ((req - 1) % 5) * 6;
  63
  64         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
  65 }
  66
  67 static inline void set_gdma_dev(int req, int dev)
  68 {
  69         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
  70         int shift = ((req - 1) % 5) * 6;
  71         u32 l;
  72
  73         l = omap_readl(reg);
  74         l &= ~(0x3f << shift);
  75         l |= (dev - 1) << shift;
  76         omap_writel(l, reg);
  77 }
  78
  79 static void clear_lch_regs(int lch)
  80 {
  81         int i;
  82         u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
  83
  84         for (i = 0; i < 0x2c; i += 2)
  85                 omap_writew(0, lch_base + i);
  86 }
  87
  88 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
  89                                   int frame_count, int sync_mode)
  90 {
  91         u16 w;
  92
  93         w = omap_readw(OMAP_DMA_CSDP_REG(lch));
  94         w &= ~0x03;
  95         w |= data_type;
  96         omap_writew(w, OMAP_DMA_CSDP_REG(lch));
  97
  98         w = omap_readw(OMAP_DMA_CCR_REG(lch));
  99         w &= ~(1 << 5);
 100         if (sync_mode == OMAP_DMA_SYNC_FRAME)
 101                 w |= 1 << 5;
 102         omap_writew(w, OMAP_DMA_CCR_REG(lch));
 103
 104         w = omap_readw(OMAP_DMA_CCR2_REG(lch));
 105         w &= ~(1 << 2);
 106         if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 107                 w |= 1 << 2;
 108         omap_writew(w, OMAP_DMA_CCR2_REG(lch));
 109
 110         omap_writew(elem_count, OMAP_DMA_CEN_REG(lch));
 111         omap_writew(frame_count, OMAP_DMA_CFN_REG(lch));
 112
 113 }
 114
 115 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 116                              unsigned long src_start)
 117 {
 118         u16 w;
 119
 120         w = omap_readw(OMAP_DMA_CSDP_REG(lch));
 121         w &= ~(0x1f << 2);
 122         w |= src_port << 2;
 123         omap_writew(w, OMAP_DMA_CSDP_REG(lch));
 124
 125         w = omap_readw(OMAP_DMA_CCR_REG(lch));
 126         w &= ~(0x03 << 12);
 127         w |= src_amode << 12;
 128         omap_writew(w, OMAP_DMA_CCR_REG(lch));
 129
 130         omap_writew(src_start >> 16, OMAP_DMA_CSSA_U_REG(lch));
 131         omap_writew(src_start, OMAP_DMA_CSSA_L_REG(lch));
 132 }
 133
 134 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 135                               unsigned long dest_start)
 136 {
 137         u16 w;
 138
 139         w = omap_readw(OMAP_DMA_CSDP_REG(lch));
 140         w &= ~(0x1f << 9);
 141         w |= dest_port << 9;
 142         omap_writew(w, OMAP_DMA_CSDP_REG(lch));
 143
 144         w = omap_readw(OMAP_DMA_CCR_REG(lch));
 145         w &= ~(0x03 << 14);
 146         w |= dest_amode << 14;
 147         omap_writew(w, OMAP_DMA_CCR_REG(lch));
 148
 149         omap_writew(dest_start >> 16, OMAP_DMA_CDSA_U_REG(lch));
 150         omap_writew(dest_start, OMAP_DMA_CDSA_L_REG(lch));
 151 }
 152
 153 void omap_start_dma(int lch)
 154 {
 155         u16 w;
 156
 157         /* Read CSR to make sure it's cleared. */
 158         w = omap_readw(OMAP_DMA_CSR_REG(lch));
 159         /* Enable some nice interrupts. */
 160         omap_writew(dma_chan[lch].enabled_irqs, OMAP_DMA_CICR_REG(lch));
 161
 162         w = omap_readw(OMAP_DMA_CCR_REG(lch));
 163         w |= OMAP_DMA_CCR_EN;
 164         omap_writew(w, OMAP_DMA_CCR_REG(lch));
 165         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 166 }
 167
 168 void omap_stop_dma(int lch)
 169 {
 170         u16 w;
 171
 172         /* Disable all interrupts on the channel */
 173         omap_writew(0, OMAP_DMA_CICR_REG(lch));
 174
 175         w = omap_readw(OMAP_DMA_CCR_REG(lch));
 176         w &= ~OMAP_DMA_CCR_EN;
 177         omap_writew(w, OMAP_DMA_CCR_REG(lch));
 178         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 179 }
 180
 181 void omap_enable_dma_irq(int lch, u16 bits)
 182 {
 183         dma_chan[lch].enabled_irqs |= bits;
 184 }
 185
 186 void omap_disable_dma_irq(int lch, u16 bits)
 187 {
 188         dma_chan[lch].enabled_irqs &= ~bits;
 189 }
 190
 191 static int dma_handle_ch(int ch)
 192 {
 193         u16 csr;
 194
 195         if (enable_1510_mode && ch >= 6) {
 196                 csr = dma_chan[ch].saved_csr;
 197                 dma_chan[ch].saved_csr = 0;
 198         } else
 199                 csr = omap_readw(OMAP_DMA_CSR_REG(ch));
 200         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
 201                 dma_chan[ch + 6].saved_csr = csr >> 7;
 202                 csr &= 0x7f;
 203         }
 204         if (!csr)
 205                 return 0;
 206         if (unlikely(dma_chan[ch].dev_id == -1)) {
 207                 printk(KERN_WARNING "Spurious interrupt from DMA channel %d (CSR %04x)\n",
 208                        ch, csr);
 209                 return 0;
 210         }
 211         if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
 212                 printk(KERN_WARNING "DMA timeout with device %d\n", dma_chan[ch].dev_id);
 213         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
 214                 printk(KERN_WARNING "DMA synchronization event drop occurred with device %d\n",
 215                        dma_chan[ch].dev_id);
 216         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
 217                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
 218         if (likely(dma_chan[ch].callback != NULL))
 219                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
 220         return 1;
 221 }
 222
 223 static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 224 {
 225         int ch = ((int) dev_id) - 1;
 226         int handled = 0;
 227
 228         for (;;) {
 229                 int handled_now = 0;
 230
 231                 handled_now += dma_handle_ch(ch);
 232                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
 233                         handled_now += dma_handle_ch(ch + 6);
 234                 if (!handled_now)
 235                         break;
 236                 handled += handled_now;
 237         }
 238
 239         return handled ? IRQ_HANDLED : IRQ_NONE;
 240 }
 241
 242 int omap_request_dma(int dev_id, const char *dev_name,
 243                      void (* callback)(int lch, u16 ch_status, void *data),
 244                      void *data, int *dma_ch_out)
 245 {
 246         int ch, free_ch = -1;
 247         unsigned long flags;
 248         struct omap_dma_lch *chan;
 249
 250         spin_lock_irqsave(&dma_chan_lock, flags);
 251         for (ch = 0; ch < dma_chan_count; ch++) {
 252                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 253                         free_ch = ch;
 254                         if (dev_id == 0)
 255                                 break;
 256                 }
 257                 if (dev_id != 0 && dma_chan[ch].dev_id == dev_id) {
 258                         spin_unlock_irqrestore(&dma_chan_lock, flags);
 259                         return -EAGAIN;
 260                 }
 261         }
 262         if (free_ch == -1) {
 263                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 264                 return -EBUSY;
 265         }
 266         chan = dma_chan + free_ch;
 267         chan->dev_id = dev_id;
 268         clear_lch_regs(free_ch);
 269         spin_unlock_irqrestore(&dma_chan_lock, flags);
 270
 271         chan->dev_id = dev_id;
 272         chan->dev_name = dev_name;
 273         chan->callback = callback;
 274         chan->data = data;
 275         chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 276
 277         if (cpu_is_omap1610() || cpu_is_omap5912()) {
 278                 /* If the sync device is set, configure it dynamically. */
 279                 if (dev_id != 0) {
 280                         set_gdma_dev(free_ch + 1, dev_id);
 281                         dev_id = free_ch + 1;
 282                 }
 283                 /* Disable the 1510 compatibility mode and set the sync device
 284                  * id. */
 285                 omap_writew(dev_id | (1 << 10), OMAP_DMA_CCR_REG(free_ch));
 286         } else {
 287                 omap_writew(dev_id, OMAP_DMA_CCR_REG(free_ch));
 288         }
 289         *dma_ch_out = free_ch;
 290
 291         return 0;
 292 }
 293
 294 void omap_free_dma(int ch)
 295 {
 296         unsigned long flags;
 297
 298         spin_lock_irqsave(&dma_chan_lock, flags);
 299         if (dma_chan[ch].dev_id == -1) {
 300                 printk("omap_dma: trying to free nonallocated DMA channel %d\n", ch);
 301                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 302                 return;
 303         }
 304         dma_chan[ch].dev_id = -1;
 305         spin_unlock_irqrestore(&dma_chan_lock, flags);
 306
 307         /* Disable all DMA interrupts for the channel. */
 308         omap_writew(0, OMAP_DMA_CICR_REG(ch));
 309         /* Make sure the DMA transfer is stopped. */
 310         omap_writew(0, OMAP_DMA_CCR_REG(ch));
 311 }
 312
 313 int omap_dma_in_1510_mode(void)
 314 {
 315         return enable_1510_mode;
 316 }
 317
 318
 319 static struct lcd_dma_info {
 320         spinlock_t lock;
 321         int reserved;
 322         void (* callback)(u16 status, void *data);
 323         void *cb_data;
 324
 325         unsigned long addr, size;
 326         int rotate, data_type, xres, yres;
 327 } lcd_dma;
 328
 329 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
 330                          int data_type)
 331 {
 332         lcd_dma.addr = addr;
 333         lcd_dma.data_type = data_type;
 334         lcd_dma.xres = fb_xres;
 335         lcd_dma.yres = fb_yres;
 336 }
 337
 338 static void set_b1_regs(void)
 339 {
 340         unsigned long top, bottom;
 341         int es;
 342         u16 w, en, fn;
 343         s16 ei;
 344         s32 fi;
 345         u32 l;
 346
 347         switch (lcd_dma.data_type) {
 348         case OMAP_DMA_DATA_TYPE_S8:
 349                 es = 1;
 350                 break;
 351         case OMAP_DMA_DATA_TYPE_S16:
 352                 es = 2;
 353                 break;
 354         case OMAP_DMA_DATA_TYPE_S32:
 355                 es = 4;
 356                 break;
 357         default:
 358                 BUG();
 359                 return;
 360         }
 361
 362         if (lcd_dma.rotate == 0) {
 363                 top = lcd_dma.addr;
 364                 bottom = lcd_dma.addr + (lcd_dma.xres * lcd_dma.yres - 1) * es;
 365                 /* 1510 DMA requires the bottom address to be 2 more than the
 366                  * actual last memory access location. */
 367                 if (omap_dma_in_1510_mode() &&
 368                     lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
 369                         bottom += 2;
 370                 en = lcd_dma.xres;
 371                 fn = lcd_dma.yres;
 372                 ei = 0;
 373                 fi = 0;
 374         } else {
 375                 top = lcd_dma.addr + (lcd_dma.xres - 1) * es;
 376                 bottom = lcd_dma.addr + (lcd_dma.yres - 1) * lcd_dma.xres * es;
 377                 en = lcd_dma.yres;
 378                 fn = lcd_dma.xres;
 379                 ei = (lcd_dma.xres - 1) * es + 1;
 380                 fi = -(lcd_dma.xres * (lcd_dma.yres - 1) + 2) * 2 + 1;
 381         }
 382
 383         if (omap_dma_in_1510_mode()) {
 384                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
 385                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
 386                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
 387                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
 388
 389                 return;
 390         }
 391
 392         /* 1610 regs */
 393         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
 394         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
 395         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
 396         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
 397
 398         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
 399         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
 400
 401         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
 402         w &= ~0x03;
 403         w |= lcd_dma.data_type;
 404         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
 405
 406         if (!lcd_dma.rotate)
 407                 return;
 408
 409         /* Rotation stuff */
 410         l = omap_readw(OMAP1610_DMA_LCD_CSDP);
 411         /* Disable burst access */
 412         l &= ~(0x03 << 7);
 413         omap_writew(l, OMAP1610_DMA_LCD_CSDP);
 414
 415         l = omap_readw(OMAP1610_DMA_LCD_CCR);
 416         /* Set the double-indexed addressing mode */
 417         l |= (0x03 << 12);
 418         omap_writew(l, OMAP1610_DMA_LCD_CCR);
 419
 420         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
 421         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
 422         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
 423 }
 424
 425 void omap_set_lcd_dma_b1_rotation(int rotate)
 426 {
 427         if (omap_dma_in_1510_mode()) {
 428                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
 429                 BUG();
 430                 return;
 431         }
 432         lcd_dma.rotate = rotate;
 433 }
 434
 435 int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
 436                          void *data)
 437 {
 438         spin_lock_irq(&lcd_dma.lock);
 439         if (lcd_dma.reserved) {
 440                 spin_unlock_irq(&lcd_dma.lock);
 441                 printk(KERN_ERR "LCD DMA channel already reserved\n");
 442                 BUG();
 443                 return -EBUSY;
 444         }
 445         lcd_dma.reserved = 1;
 446         spin_unlock_irq(&lcd_dma.lock);
 447         lcd_dma.callback = callback;
 448         lcd_dma.cb_data = data;
 449
 450         return 0;
 451 }
 452
 453 void omap_free_lcd_dma(void)
 454 {
 455         spin_lock(&lcd_dma.lock);
 456         if (!lcd_dma.reserved) {
 457                 spin_unlock(&lcd_dma.lock);
 458                 printk(KERN_ERR "LCD DMA is not reserved\n");
 459                 BUG();
 460                 return;
 461         }
 462         if (!enable_1510_mode)
 463                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR);
 464         lcd_dma.reserved = 0;
 465         spin_unlock(&lcd_dma.lock);
 466 }
 467
 468 void omap_start_lcd_dma(void)
 469 {
 470         if (!enable_1510_mode) {
 471                 /* Set some reasonable defaults */
 472                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
 473                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
 474                 omap_writew(0x5740, OMAP1610_DMA_LCD_CCR);
 475         }
 476         set_b1_regs();
 477         if (!enable_1510_mode)
 478                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) | 1, OMAP1610_DMA_LCD_CCR);
 479 }
 480
 481 void omap_stop_lcd_dma(void)
 482 {
 483         if (!enable_1510_mode)
 484                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR);
 485 }
 486
 487 static int __init omap_init_dma(void)
 488 {
 489         int ch, r;
 490
 491         if (cpu_is_omap1510()) {
 492                 printk(KERN_INFO "DMA support for OMAP1510 initialized\n");
 493                 dma_chan_count = 9;
 494                 enable_1510_mode = 1;
 495         } else if (cpu_is_omap1610() || cpu_is_omap5912()) {
 496                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
 497                        omap_readw(OMAP_DMA_HW_ID_REG));
 498                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
 499                        (omap_readw(OMAP_DMA_CAPS_0_U_REG) << 16) | omap_readw(OMAP_DMA_CAPS_0_L_REG),
 500                        (omap_readw(OMAP_DMA_CAPS_1_U_REG) << 16) | omap_readw(OMAP_DMA_CAPS_1_L_REG),
 501                        omap_readw(OMAP_DMA_CAPS_2_REG), omap_readw(OMAP_DMA_CAPS_3_REG),
 502                        omap_readw(OMAP_DMA_CAPS_4_REG));
 503                 if (!enable_1510_mode) {
 504                         u16 w;
 505
 506                         /* Disable OMAP 3.0/3.1 compatibility mode. */
 507                         w = omap_readw(OMAP_DMA_GSCR_REG);
 508                         w |= 1 << 3;
 509                         omap_writew(w, OMAP_DMA_GSCR_REG);
 510                         dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
 511                 } else
 512                         dma_chan_count = 9;
 513         } else {
 514                 dma_chan_count = 0;
 515                 return 0;
 516         }
 517
 518         memset(&lcd_dma, 0, sizeof(lcd_dma));
 519         spin_lock_init(&lcd_dma.lock);
 520         spin_lock_init(&dma_chan_lock);
 521         memset(&dma_chan, 0, sizeof(dma_chan));
 522
 523         for (ch = 0; ch < dma_chan_count; ch++) {
 524                 dma_chan[ch].dev_id = -1;
 525                 if (ch >= 6 && enable_1510_mode)
 526                         continue;
 527
 528                 /* request_irq() doesn't like dev_id (ie. ch) being zero,
 529                  * so we have to kludge around this. */
 530                 r = request_irq(dma_irq[ch], dma_irq_handler, 0, "DMA",
 531                                 (void *) (ch + 1));
 532                 if (r != 0) {
 533                         int i;
 534
 535                         printk(KERN_ERR "unable to request IRQ %d for DMA (error %d)\n",
 536                                dma_irq[ch], r);
 537                         for (i = 0; i < ch; i++)
 538                                 free_irq(dma_irq[i], (void *) (i + 1));
 539                         return r;
 540                 }
 541         }
 542
 543         return 0;
 544 }
 545 arch_initcall(omap_init_dma);
 546
 547 EXPORT_SYMBOL(omap_request_dma);
 548 EXPORT_SYMBOL(omap_free_dma);
 549 EXPORT_SYMBOL(omap_start_dma);
 550 EXPORT_SYMBOL(omap_stop_dma);
 551 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 552 EXPORT_SYMBOL(omap_set_dma_src_params);
 553 EXPORT_SYMBOL(omap_set_dma_dest_params);
 554
 555 EXPORT_SYMBOL(omap_request_lcd_dma);
 556 EXPORT_SYMBOL(omap_free_lcd_dma);
 557 EXPORT_SYMBOL(omap_start_lcd_dma);
 558 EXPORT_SYMBOL(omap_stop_lcd_dma);
 559 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
 560 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);