arch/arm/mach-omap/dma.c

   1 /*
   2  * linux/arch/arm/omap/dma.c
   3  *
   4  * Copyright (C) 2003 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  *
   8  * Support functions for the OMAP internal DMA channels.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/sched.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/errno.h>
  21 #include <linux/interrupt.h>
  22
  23 #include <asm/system.h>
  24 #include <asm/irq.h>
  25 #include <asm/hardware.h>
  26 #include <asm/dma.h>
  27 #include <asm/io.h>
  28
  29 #define OMAP_DMA_ACTIVE         0x01
  30
  31 #define OMAP_DMA_CCR_EN         (1 << 7)
  32
  33 #define OMAP_FUNC_MUX_ARM_BASE  (0xfffe1000 + 0xec)
  34
  35 static int enable_1510_mode = 0;
  36
  37 struct omap_dma_lch {
  38         int next_lch;
  39         int dev_id;
  40         u16 saved_csr;
  41         u16 enabled_irqs;
  42         const char *dev_name;
  43         void (* callback)(int lch, u16 ch_status, void *data);
  44         void *data;
  45         long flags;
  46 };
  47
  48 static int dma_chan_count;
  49
  50 static spinlock_t dma_chan_lock;
  51 static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
  52
  53 const static u8 dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
  54         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
  55         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
  56         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
  57         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
  58         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
  59 };
  60
  61 static inline int get_gdma_dev(int req)
  62 {
  63         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
  64         int shift = ((req - 1) % 5) * 6;
  65
  66         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
  67 }
  68
  69 static inline void set_gdma_dev(int req, int dev)
  70 {
  71         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
  72         int shift = ((req - 1) % 5) * 6;
  73         u32 l;
  74
  75         l = omap_readl(reg);
  76         l &= ~(0x3f << shift);
  77         l |= (dev - 1) << shift;
  78         omap_writel(l, reg);
  79 }
  80
  81 static void clear_lch_regs(int lch)
  82 {
  83         int i;
  84         u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
  85
  86         for (i = 0; i < 0x2c; i += 2)
  87                 omap_writew(0, lch_base + i);
  88 }
  89
  90 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
  91                                   int frame_count, int sync_mode)
  92 {
  93         u16 w;
  94
  95         w = omap_readw(OMAP_DMA_CSDP(lch));
  96         w &= ~0x03;
  97         w |= data_type;
  98         omap_writew(w, OMAP_DMA_CSDP(lch));
  99
 100         w = omap_readw(OMAP_DMA_CCR(lch));
 101         w &= ~(1 << 5);
 102         if (sync_mode == OMAP_DMA_SYNC_FRAME)
 103                 w |= 1 << 5;
 104         omap_writew(w, OMAP_DMA_CCR(lch));
 105
 106         w = omap_readw(OMAP_DMA_CCR2(lch));
 107         w &= ~(1 << 2);
 108         if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 109                 w |= 1 << 2;
 110         omap_writew(w, OMAP_DMA_CCR2(lch));
 111
 112         omap_writew(elem_count, OMAP_DMA_CEN(lch));
 113         omap_writew(frame_count, OMAP_DMA_CFN(lch));
 114
 115 }
 116 void omap_set_dma_constant_fill(int lch, u32 color)
 117 {
 118         u16 w;
 119
 120 #ifdef CONFIG_DEBUG_KERNEL
 121         if (omap_dma_in_1510_mode) {
 122                 printk(KERN_ERR "OMAP DMA constant fill not available in 1510 mode.");
 123                 BUG();
 124                 return;
 125         }
 126 #endif
 127         w = omap_readw(OMAP_DMA_CCR2(lch)) & ~0x03;
 128         w |= 0x01;
 129         omap_writew(w, OMAP_DMA_CCR2(lch));
 130
 131         omap_writew((u16)color, OMAP_DMA_COLOR_L(lch));
 132         omap_writew((u16)(color >> 16), OMAP_DMA_COLOR_U(lch));
 133
 134         w = omap_readw(OMAP_DMA_LCH_CTRL(lch)) & ~0x0f;
 135         w |= 1;         /* Channel type G */
 136         omap_writew(w, OMAP_DMA_LCH_CTRL(lch));
 137 }
 138
 139 void omap_set_dma_transparent_copy(int lch, u32 color)
 140 {
 141         u16 w;
 142
 143 #ifdef CONFIG_DEBUG_KERNEL
 144         if (omap_dma_in_1510_mode) {
 145                 printk(KERN_ERR "OMAP DMA transparent copy not available in 1510 mode.");
 146                 BUG();
 147         }
 148 #endif
 149         w = omap_readw(OMAP_DMA_CCR2(lch)) & ~0x03;
 150         w |= 0x02;
 151         omap_writew(w, OMAP_DMA_CCR2(lch));
 152
 153         omap_writew((u16)color, OMAP_DMA_COLOR_L(lch));
 154         omap_writew((u16)(color >> 16), OMAP_DMA_COLOR_U(lch));
 155
 156         w = omap_readw(OMAP_DMA_LCH_CTRL(lch)) & ~0x0f;
 157         w |= 1;         /* Channel type G */
 158         omap_writew(w, OMAP_DMA_LCH_CTRL(lch));
 159 }
 160
 161 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 162                              unsigned long src_start)
 163 {
 164         u16 w;
 165
 166         w = omap_readw(OMAP_DMA_CSDP(lch));
 167         w &= ~(0x1f << 2);
 168         w |= src_port << 2;
 169         omap_writew(w, OMAP_DMA_CSDP(lch));
 170
 171         w = omap_readw(OMAP_DMA_CCR(lch));
 172         w &= ~(0x03 << 12);
 173         w |= src_amode << 12;
 174         omap_writew(w, OMAP_DMA_CCR(lch));
 175
 176         omap_writew(src_start >> 16, OMAP_DMA_CSSA_U(lch));
 177         omap_writew(src_start, OMAP_DMA_CSSA_L(lch));
 178 }
 179
 180 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 181 {
 182         omap_writew(eidx, OMAP_DMA_CSEI(lch));
 183         omap_writew(fidx, OMAP_DMA_CSFI(lch));
 184 }
 185
 186 void omap_set_dma_src_data_pack(int lch, int enable)
 187 {
 188         u16 w;
 189
 190         w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 6);
 191         w |= enable ? (1 << 6) : 0;
 192         omap_writew(w, OMAP_DMA_CSDP(lch));
 193 }
 194
 195 void omap_set_dma_src_burst_mode(int lch, int burst_mode)
 196 {
 197         u16 w;
 198
 199         w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 7);
 200         switch (burst_mode) {
 201         case OMAP_DMA_DATA_BURST_4:
 202                 w |= (0x01 << 7);
 203                 break;
 204         case OMAP_DMA_DATA_BURST_8:
 205                 w |= (0x03 << 7);
 206                 break;
 207         default:
 208                 printk(KERN_ERR "Invalid DMA burst mode\n");
 209                 BUG();
 210                 return;
 211         }
 212         omap_writew(w, OMAP_DMA_CSDP(lch));
 213 }
 214
 215 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 216                               unsigned long dest_start)
 217 {
 218         u16 w;
 219
 220         w = omap_readw(OMAP_DMA_CSDP(lch));
 221         w &= ~(0x1f << 9);
 222         w |= dest_port << 9;
 223         omap_writew(w, OMAP_DMA_CSDP(lch));
 224
 225         w = omap_readw(OMAP_DMA_CCR(lch));
 226         w &= ~(0x03 << 14);
 227         w |= dest_amode << 14;
 228         omap_writew(w, OMAP_DMA_CCR(lch));
 229
 230         omap_writew(dest_start >> 16, OMAP_DMA_CDSA_U(lch));
 231         omap_writew(dest_start, OMAP_DMA_CDSA_L(lch));
 232 }
 233
 234 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 235 {
 236         omap_writew(eidx, OMAP_DMA_CDEI(lch));
 237         omap_writew(fidx, OMAP_DMA_CDFI(lch));
 238 }
 239
 240 void omap_set_dma_dest_data_pack(int lch, int enable)
 241 {
 242         u16 w;
 243
 244         w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 13);
 245         w |= enable ? (1 << 13) : 0;
 246         omap_writew(w, OMAP_DMA_CSDP(lch));
 247 }
 248
 249 void omap_set_dma_dest_burst_mode(int lch, int burst_mode)
 250 {
 251         u16 w;
 252
 253         w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 14);
 254         switch (burst_mode) {
 255         case OMAP_DMA_DATA_BURST_4:
 256                 w |= (0x01 << 14);
 257                 break;
 258         case OMAP_DMA_DATA_BURST_8:
 259                 w |= (0x03 << 14);
 260                 break;
 261         default:
 262                 printk(KERN_ERR "Invalid DMA burst mode\n");
 263                 BUG();
 264                 return;
 265         }
 266         omap_writew(w, OMAP_DMA_CSDP(lch));
 267 }
 268
 269 void omap_start_dma(int lch)
 270 {
 271         u16 w;
 272
 273         if (!omap_dma_in_1510_mode()) {
 274                 int next_lch;
 275
 276                 next_lch = dma_chan[lch].next_lch;
 277
 278                 /* Enable the queue, if needed so. */
 279                 if (next_lch != -1) {
 280                         /* Clear the STOP_LNK bits */
 281                         w = omap_readw(OMAP_DMA_CLNK_CTRL(lch));
 282                         w &= ~(1 << 14);
 283                         omap_writew(w, OMAP_DMA_CLNK_CTRL(lch));
 284                         w = omap_readw(OMAP_DMA_CLNK_CTRL(next_lch));
 285                         w &= ~(1 << 14);
 286                         omap_writew(w, OMAP_DMA_CLNK_CTRL(next_lch));
 287
 288                         /* And set the ENABLE_LNK bits */
 289                         omap_writew(next_lch | (1 << 15),
 290                                     OMAP_DMA_CLNK_CTRL(lch));
 291                         /* The loop case */
 292                         if (dma_chan[next_lch].next_lch == lch)
 293                                 omap_writew(lch | (1 << 15),
 294                                             OMAP_DMA_CLNK_CTRL(next_lch));
 295
 296                         /* Read CSR to make sure it's cleared. */
 297                         w = omap_readw(OMAP_DMA_CSR(next_lch));
 298                         /* Enable some nice interrupts. */
 299                         omap_writew(dma_chan[next_lch].enabled_irqs,
 300                                     OMAP_DMA_CICR(next_lch));
 301                         dma_chan[next_lch].flags |= OMAP_DMA_ACTIVE;
 302                 }
 303         }
 304
 305         /* Read CSR to make sure it's cleared. */
 306         w = omap_readw(OMAP_DMA_CSR(lch));
 307         /* Enable some nice interrupts. */
 308         omap_writew(dma_chan[lch].enabled_irqs, OMAP_DMA_CICR(lch));
 309
 310         w = omap_readw(OMAP_DMA_CCR(lch));
 311         w |= OMAP_DMA_CCR_EN;
 312         omap_writew(w, OMAP_DMA_CCR(lch));
 313         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 314 }
 315
 316 void omap_stop_dma(int lch)
 317 {
 318         u16 w;
 319         int next_lch;
 320
 321         /* Disable all interrupts on the channel */
 322         omap_writew(0, OMAP_DMA_CICR(lch));
 323
 324         if (omap_dma_in_1510_mode()) {
 325                 w = omap_readw(OMAP_DMA_CCR(lch));
 326                 w &= ~OMAP_DMA_CCR_EN;
 327                 omap_writew(w, OMAP_DMA_CCR(lch));
 328                 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 329                 return;
 330         }
 331
 332         next_lch = dma_chan[lch].next_lch;
 333
 334         /*
 335          * According to thw HW spec, enabling the STOP_LNK bit
 336          * resets the CCR_EN bit at the same time.
 337          */
 338         w = omap_readw(OMAP_DMA_CLNK_CTRL(lch));
 339         w |= (1 << 14);
 340         w = omap_writew(w, OMAP_DMA_CLNK_CTRL(lch));
 341         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 342
 343         if (next_lch != -1) {
 344                 omap_writew(0, OMAP_DMA_CICR(next_lch));
 345                 w = omap_readw(OMAP_DMA_CLNK_CTRL(next_lch));
 346                 w |= (1 << 14);
 347                 w = omap_writew(w, OMAP_DMA_CLNK_CTRL(next_lch));
 348                 dma_chan[next_lch].flags &= ~OMAP_DMA_ACTIVE;
 349         }
 350 }
 351
 352 void omap_enable_dma_irq(int lch, u16 bits)
 353 {
 354         dma_chan[lch].enabled_irqs |= bits;
 355 }
 356
 357 void omap_disable_dma_irq(int lch, u16 bits)
 358 {
 359         dma_chan[lch].enabled_irqs &= ~bits;
 360 }
 361
 362 static int dma_handle_ch(int ch)
 363 {
 364         u16 csr;
 365
 366         if (enable_1510_mode && ch >= 6) {
 367                 csr = dma_chan[ch].saved_csr;
 368                 dma_chan[ch].saved_csr = 0;
 369         } else
 370                 csr = omap_readw(OMAP_DMA_CSR(ch));
 371         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
 372                 dma_chan[ch + 6].saved_csr = csr >> 7;
 373                 csr &= 0x7f;
 374         }
 375         if (!csr)
 376                 return 0;
 377         if (unlikely(dma_chan[ch].dev_id == -1)) {
 378                 printk(KERN_WARNING "Spurious interrupt from DMA channel %d (CSR %04x)\n",
 379                        ch, csr);
 380                 return 0;
 381         }
 382         if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
 383                 printk(KERN_WARNING "DMA timeout with device %d\n", dma_chan[ch].dev_id);
 384         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
 385                 printk(KERN_WARNING "DMA synchronization event drop occurred with device %d\n",
 386                        dma_chan[ch].dev_id);
 387         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
 388                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
 389         if (likely(dma_chan[ch].callback != NULL))
 390                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
 391         return 1;
 392 }
 393
 394 static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 395 {
 396         int ch = ((int) dev_id) - 1;
 397         int handled = 0;
 398
 399         for (;;) {
 400                 int handled_now = 0;
 401
 402                 handled_now += dma_handle_ch(ch);
 403                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
 404                         handled_now += dma_handle_ch(ch + 6);
 405                 if (!handled_now)
 406                         break;
 407                 handled += handled_now;
 408         }
 409
 410         return handled ? IRQ_HANDLED : IRQ_NONE;
 411 }
 412
 413 int omap_request_dma(int dev_id, const char *dev_name,
 414                      void (* callback)(int lch, u16 ch_status, void *data),
 415                      void *data, int *dma_ch_out)
 416 {
 417         int ch, free_ch = -1;
 418         unsigned long flags;
 419         struct omap_dma_lch *chan;
 420
 421         spin_lock_irqsave(&dma_chan_lock, flags);
 422         for (ch = 0; ch < dma_chan_count; ch++) {
 423                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 424                         free_ch = ch;
 425                         if (dev_id == 0)
 426                                 break;
 427                 }
 428                 if (dev_id != 0 && dma_chan[ch].dev_id == dev_id) {
 429                         spin_unlock_irqrestore(&dma_chan_lock, flags);
 430                         return -EAGAIN;
 431                 }
 432         }
 433         if (free_ch == -1) {
 434                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 435                 return -EBUSY;
 436         }
 437         chan = dma_chan + free_ch;
 438         chan->dev_id = dev_id;
 439         clear_lch_regs(free_ch);
 440         spin_unlock_irqrestore(&dma_chan_lock, flags);
 441
 442         chan->dev_id = dev_id;
 443         chan->dev_name = dev_name;
 444         chan->callback = callback;
 445         chan->data = data;
 446         chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 447
 448         if (cpu_is_omap1610() || cpu_is_omap5912()) {
 449                 /* If the sync device is set, configure it dynamically. */
 450                 if (dev_id != 0) {
 451                         set_gdma_dev(free_ch + 1, dev_id);
 452                         dev_id = free_ch + 1;
 453                 }
 454                 /* Disable the 1510 compatibility mode and set the sync device
 455                  * id. */
 456                 omap_writew(dev_id | (1 << 10), OMAP_DMA_CCR(free_ch));
 457         } else {
 458                 omap_writew(dev_id, OMAP_DMA_CCR(free_ch));
 459         }
 460         *dma_ch_out = free_ch;
 461
 462         return 0;
 463 }
 464
 465 void omap_free_dma(int ch)
 466 {
 467         unsigned long flags;
 468
 469         spin_lock_irqsave(&dma_chan_lock, flags);
 470         if (dma_chan[ch].dev_id == -1) {
 471                 printk("omap_dma: trying to free nonallocated DMA channel %d\n", ch);
 472                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 473                 return;
 474         }
 475         dma_chan[ch].dev_id = -1;
 476         spin_unlock_irqrestore(&dma_chan_lock, flags);
 477
 478         /* Disable all DMA interrupts for the channel. */
 479         omap_writew(0, OMAP_DMA_CICR(ch));
 480         /* Make sure the DMA transfer is stopped. */
 481         omap_writew(0, OMAP_DMA_CCR(ch));
 482 }
 483
 484 int omap_dma_in_1510_mode(void)
 485 {
 486         return enable_1510_mode;
 487 }
 488
 489 /*
 490  * lch_queue DMA will start right after lch_head one is finished.
 491  * For this DMA link to start, you still need to start (see omap_start_dma)
 492  * the first one. That will fire up the entire queue.
 493  */
 494 void omap_dma_link_lch (int lch_head, int lch_queue)
 495 {
 496         if (omap_dma_in_1510_mode()) {
 497                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
 498                 BUG();
 499                 return;
 500         }
 501
 502         if ((dma_chan[lch_head].dev_id == -1) ||
 503             (dma_chan[lch_queue].dev_id == -1)) {
 504                 printk(KERN_ERR "omap_dma: trying to link non requested channels\n");
 505                 dump_stack();
 506         }
 507
 508         dma_chan[lch_head].next_lch = lch_queue;
 509 }
 510
 511 /*
 512  * Once the DMA queue is stopped, we can destroy it.
 513  */
 514 void omap_dma_unlink_lch (int lch_head, int lch_queue)
 515 {
 516         if (omap_dma_in_1510_mode()) {
 517                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
 518                 BUG();
 519                 return;
 520         }
 521
 522         if (dma_chan[lch_head].next_lch != lch_queue ||
 523             dma_chan[lch_head].next_lch == -1) {
 524                 printk(KERN_ERR "omap_dma: trying to unlink non linked channels\n");
 525                 dump_stack();
 526         }
 527
 528
 529         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
 530             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
 531                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels before unlinking\n");
 532                 dump_stack();
 533         }
 534
 535         dma_chan[lch_head].next_lch = -1;
 536         dma_chan[lch_queue].next_lch = -1;
 537 }
 538
 539
 540 static struct lcd_dma_info {
 541         spinlock_t lock;
 542         int reserved;
 543         void (* callback)(u16 status, void *data);
 544         void *cb_data;
 545
 546         unsigned long addr, size;
 547         int rotate, data_type, xres, yres;
 548 } lcd_dma;
 549
 550 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
 551                          int data_type)
 552 {
 553         lcd_dma.addr = addr;
 554         lcd_dma.data_type = data_type;
 555         lcd_dma.xres = fb_xres;
 556         lcd_dma.yres = fb_yres;
 557 }
 558
 559 static void set_b1_regs(void)
 560 {
 561         unsigned long top, bottom;
 562         int es;
 563         u16 w, en, fn;
 564         s16 ei;
 565         s32 fi;
 566         u32 l;
 567
 568         switch (lcd_dma.data_type) {
 569         case OMAP_DMA_DATA_TYPE_S8:
 570                 es = 1;
 571                 break;
 572         case OMAP_DMA_DATA_TYPE_S16:
 573                 es = 2;
 574                 break;
 575         case OMAP_DMA_DATA_TYPE_S32:
 576                 es = 4;
 577                 break;
 578         default:
 579                 BUG();
 580                 return;
 581         }
 582
 583         if (lcd_dma.rotate == 0) {
 584                 top = lcd_dma.addr;
 585                 bottom = lcd_dma.addr + (lcd_dma.xres * lcd_dma.yres - 1) * es;
 586                 /* 1510 DMA requires the bottom address to be 2 more than the
 587                  * actual last memory access location. */
 588                 if (omap_dma_in_1510_mode() &&
 589                     lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
 590                         bottom += 2;
 591                 en = lcd_dma.xres;
 592                 fn = lcd_dma.yres;
 593                 ei = 0;
 594                 fi = 0;
 595         } else {
 596                 top = lcd_dma.addr + (lcd_dma.xres - 1) * es;
 597                 bottom = lcd_dma.addr + (lcd_dma.yres - 1) * lcd_dma.xres * es;
 598                 en = lcd_dma.yres;
 599                 fn = lcd_dma.xres;
 600                 ei = (lcd_dma.xres - 1) * es + 1;
 601                 fi = -(lcd_dma.xres * (lcd_dma.yres - 1) + 2) * 2 + 1;
 602         }
 603
 604         if (omap_dma_in_1510_mode()) {
 605                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
 606                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
 607                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
 608                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
 609
 610                 return;
 611         }
 612
 613         /* 1610 regs */
 614         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
 615         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
 616         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
 617         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
 618
 619         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
 620         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
 621
 622         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
 623         w &= ~0x03;
 624         w |= lcd_dma.data_type;
 625         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
 626
 627         if (!lcd_dma.rotate)
 628                 return;
 629
 630         /* Rotation stuff */
 631         l = omap_readw(OMAP1610_DMA_LCD_CSDP);
 632         /* Disable burst access */
 633         l &= ~(0x03 << 7);
 634         omap_writew(l, OMAP1610_DMA_LCD_CSDP);
 635
 636         l = omap_readw(OMAP1610_DMA_LCD_CCR);
 637         /* Set the double-indexed addressing mode */
 638         l |= (0x03 << 12);
 639         omap_writew(l, OMAP1610_DMA_LCD_CCR);
 640
 641         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
 642         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
 643         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
 644 }
 645
 646 void omap_set_lcd_dma_b1_rotation(int rotate)
 647 {
 648         if (omap_dma_in_1510_mode()) {
 649                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
 650                 BUG();
 651                 return;
 652         }
 653         lcd_dma.rotate = rotate;
 654 }
 655
 656 int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
 657                          void *data)
 658 {
 659         spin_lock_irq(&lcd_dma.lock);
 660         if (lcd_dma.reserved) {
 661                 spin_unlock_irq(&lcd_dma.lock);
 662                 printk(KERN_ERR "LCD DMA channel already reserved\n");
 663                 BUG();
 664                 return -EBUSY;
 665         }
 666         lcd_dma.reserved = 1;
 667         spin_unlock_irq(&lcd_dma.lock);
 668         lcd_dma.callback = callback;
 669         lcd_dma.cb_data = data;
 670
 671         return 0;
 672 }
 673
 674 void omap_free_lcd_dma(void)
 675 {
 676         spin_lock(&lcd_dma.lock);
 677         if (!lcd_dma.reserved) {
 678                 spin_unlock(&lcd_dma.lock);
 679                 printk(KERN_ERR "LCD DMA is not reserved\n");
 680                 BUG();
 681                 return;
 682         }
 683         if (!enable_1510_mode)
 684                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR);
 685         lcd_dma.reserved = 0;
 686         spin_unlock(&lcd_dma.lock);
 687 }
 688
 689 void omap_start_lcd_dma(void)
 690 {
 691         if (!enable_1510_mode) {
 692                 /* Set some reasonable defaults */
 693                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
 694                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
 695                 omap_writew(0x5740, OMAP1610_DMA_LCD_CCR);
 696         }
 697         set_b1_regs();
 698         if (!enable_1510_mode)
 699                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) | 1, OMAP1610_DMA_LCD_CCR);
 700 }
 701
 702 void omap_stop_lcd_dma(void)
 703 {
 704         if (!enable_1510_mode)
 705                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR);
 706 }
 707
 708 static int __init omap_init_dma(void)
 709 {
 710         int ch, r;
 711
 712         if (cpu_is_omap1510()) {
 713                 printk(KERN_INFO "DMA support for OMAP1510 initialized\n");
 714                 dma_chan_count = 9;
 715                 enable_1510_mode = 1;
 716         } else if (cpu_is_omap1610() || cpu_is_omap5912()) {
 717                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
 718                        omap_readw(OMAP_DMA_HW_ID));
 719                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
 720                        (omap_readw(OMAP_DMA_CAPS_0_U) << 16) | omap_readw(OMAP_DMA_CAPS_0_L),
 721                        (omap_readw(OMAP_DMA_CAPS_1_U) << 16) | omap_readw(OMAP_DMA_CAPS_1_L),
 722                        omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
 723                        omap_readw(OMAP_DMA_CAPS_4));
 724                 if (!enable_1510_mode) {
 725                         u16 w;
 726
 727                         /* Disable OMAP 3.0/3.1 compatibility mode. */
 728                         w = omap_readw(OMAP_DMA_GSCR);
 729                         w |= 1 << 3;
 730                         omap_writew(w, OMAP_DMA_GSCR);
 731                         dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
 732                 } else
 733                         dma_chan_count = 9;
 734         } else {
 735                 dma_chan_count = 0;
 736                 return 0;
 737         }
 738
 739         memset(&lcd_dma, 0, sizeof(lcd_dma));
 740         spin_lock_init(&lcd_dma.lock);
 741         spin_lock_init(&dma_chan_lock);
 742         memset(&dma_chan, 0, sizeof(dma_chan));
 743
 744         for (ch = 0; ch < dma_chan_count; ch++) {
 745                 dma_chan[ch].dev_id = -1;
 746                 dma_chan[ch].next_lch = -1;
 747
 748                 if (ch >= 6 && enable_1510_mode)
 749                         continue;
 750
 751                 /* request_irq() doesn't like dev_id (ie. ch) being zero,
 752                  * so we have to kludge around this. */
 753                 r = request_irq(dma_irq[ch], dma_irq_handler, 0, "DMA",
 754                                 (void *) (ch + 1));
 755                 if (r != 0) {
 756                         int i;
 757
 758                         printk(KERN_ERR "unable to request IRQ %d for DMA (error %d)\n",
 759                                dma_irq[ch], r);
 760                         for (i = 0; i < ch; i++)
 761                                 free_irq(dma_irq[i], (void *) (i + 1));
 762                         return r;
 763                 }
 764         }
 765
 766         return 0;
 767 }
 768 arch_initcall(omap_init_dma);
 769
 770 EXPORT_SYMBOL(omap_request_dma);
 771 EXPORT_SYMBOL(omap_free_dma);
 772 EXPORT_SYMBOL(omap_start_dma);
 773 EXPORT_SYMBOL(omap_stop_dma);
 774
 775 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 776 EXPORT_SYMBOL(omap_set_dma_constant_fill);
 777 EXPORT_SYMBOL(omap_set_dma_transparent_copy);
 778
 779 EXPORT_SYMBOL(omap_set_dma_src_params);
 780 EXPORT_SYMBOL(omap_set_dma_src_index);
 781 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 782 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 783
 784 EXPORT_SYMBOL(omap_set_dma_dest_params);
 785 EXPORT_SYMBOL(omap_set_dma_dest_index);
 786 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 787 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 788
 789 EXPORT_SYMBOL(omap_dma_link_lch);
 790 EXPORT_SYMBOL(omap_dma_unlink_lch);
 791
 792 EXPORT_SYMBOL(omap_request_lcd_dma);
 793 EXPORT_SYMBOL(omap_free_lcd_dma);
 794 EXPORT_SYMBOL(omap_start_lcd_dma);
 795 EXPORT_SYMBOL(omap_stop_lcd_dma);
 796 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
 797 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);