arch/arm/mach-omap/dma.c

   1 /*
   2  * linux/arch/arm/omap/dma.c
   3  *
   4  * Copyright (C) 2003 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  *
   8  * Support functions for the OMAP internal DMA channels.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/sched.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/errno.h>
  21 #include <linux/interrupt.h>
  22
  23 #include <asm/system.h>
  24 #include <asm/irq.h>
  25 #include <asm/hardware.h>
  26 #include <asm/dma.h>
  27 #include <asm/io.h>
  28
  29 #define OMAP_DMA_ACTIVE         0x01
  30
  31 #define OMAP_DMA_CCR_EN         (1 << 7)
  32
  33 #define OMAP_FUNC_MUX_ARM_BASE  (0xfffe1000 + 0xec)
  34
  35 static int enable_1510_mode = 0;
  36
  37 struct omap_dma_lch {
  38         int next_lch;
  39         int dev_id;
  40         u16 saved_csr;
  41         u16 enabled_irqs;
  42         const char *dev_name;
  43         void (* callback)(int lch, u16 ch_status, void *data);
  44         void *data;
  45         long flags;
  46 };
  47
  48 static int dma_chan_count;
  49
  50 static spinlock_t dma_chan_lock;
  51 static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
  52
  53 const static u8 dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
  54         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
  55         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
  56         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
  57         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
  58         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
  59 };
  60
  61 static inline int get_gdma_dev(int req)
  62 {
  63         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
  64         int shift = ((req - 1) % 5) * 6;
  65
  66         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
  67 }
  68
  69 static inline void set_gdma_dev(int req, int dev)
  70 {
  71         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
  72         int shift = ((req - 1) % 5) * 6;
  73         u32 l;
  74
  75         l = omap_readl(reg);
  76         l &= ~(0x3f << shift);
  77         l |= (dev - 1) << shift;
  78         omap_writel(l, reg);
  79 }
  80
  81 static void clear_lch_regs(int lch)
  82 {
  83         int i;
  84         u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
  85
  86         for (i = 0; i < 0x2c; i += 2)
  87                 omap_writew(0, lch_base + i);
  88 }
  89
  90 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
  91                                   int frame_count, int sync_mode)
  92 {
  93         u16 w;
  94
  95         w = omap_readw(OMAP_DMA_CSDP(lch));
  96         w &= ~0x03;
  97         w |= data_type;
  98         omap_writew(w, OMAP_DMA_CSDP(lch));
  99
 100         w = omap_readw(OMAP_DMA_CCR(lch));
 101         w &= ~(1 << 5);
 102         if (sync_mode == OMAP_DMA_SYNC_FRAME)
 103                 w |= 1 << 5;
 104         omap_writew(w, OMAP_DMA_CCR(lch));
 105
 106         w = omap_readw(OMAP_DMA_CCR2(lch));
 107         w &= ~(1 << 2);
 108         if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 109                 w |= 1 << 2;
 110         omap_writew(w, OMAP_DMA_CCR2(lch));
 111
 112         omap_writew(elem_count, OMAP_DMA_CEN(lch));
 113         omap_writew(frame_count, OMAP_DMA_CFN(lch));
 114
 115 }
 116 void omap_set_dma_constant_fill(int lch, u32 color)
 117 {
 118         u16 w;
 119
 120 #ifdef CONFIG_DEBUG_KERNEL
 121         if (omap_dma_in_1510_mode()) {
 122                 printk(KERN_ERR "OMAP DMA constant fill not available in 1510 mode.");
 123                 BUG();
 124                 return;
 125         }
 126 #endif
 127         w = omap_readw(OMAP_DMA_CCR2(lch)) & ~0x03;
 128         w |= 0x01;
 129         omap_writew(w, OMAP_DMA_CCR2(lch));
 130
 131         omap_writew((u16)color, OMAP_DMA_COLOR_L(lch));
 132         omap_writew((u16)(color >> 16), OMAP_DMA_COLOR_U(lch));
 133
 134         w = omap_readw(OMAP_DMA_LCH_CTRL(lch)) & ~0x0f;
 135         w |= 1;         /* Channel type G */
 136         omap_writew(w, OMAP_DMA_LCH_CTRL(lch));
 137 }
 138
 139 void omap_set_dma_transparent_copy(int lch, u32 color)
 140 {
 141         u16 w;
 142
 143 #ifdef CONFIG_DEBUG_KERNEL
 144         if (omap_dma_in_1510_mode()) {
 145                 printk(KERN_ERR "OMAP DMA transparent copy not available in 1510 mode.");
 146                 BUG();
 147         }
 148 #endif
 149         w = omap_readw(OMAP_DMA_CCR2(lch)) & ~0x03;
 150         w |= 0x02;
 151         omap_writew(w, OMAP_DMA_CCR2(lch));
 152
 153         omap_writew((u16)color, OMAP_DMA_COLOR_L(lch));
 154         omap_writew((u16)(color >> 16), OMAP_DMA_COLOR_U(lch));
 155
 156         w = omap_readw(OMAP_DMA_LCH_CTRL(lch)) & ~0x0f;
 157         w |= 1;         /* Channel type G */
 158         omap_writew(w, OMAP_DMA_LCH_CTRL(lch));
 159 }
 160
 161 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 162                              unsigned long src_start)
 163 {
 164         u16 w;
 165
 166         w = omap_readw(OMAP_DMA_CSDP(lch));
 167         w &= ~(0x1f << 2);
 168         w |= src_port << 2;
 169         omap_writew(w, OMAP_DMA_CSDP(lch));
 170
 171         w = omap_readw(OMAP_DMA_CCR(lch));
 172         w &= ~(0x03 << 12);
 173         w |= src_amode << 12;
 174         omap_writew(w, OMAP_DMA_CCR(lch));
 175
 176         omap_writew(src_start >> 16, OMAP_DMA_CSSA_U(lch));
 177         omap_writew(src_start, OMAP_DMA_CSSA_L(lch));
 178 }
 179
 180 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 181 {
 182         omap_writew(eidx, OMAP_DMA_CSEI(lch));
 183         omap_writew(fidx, OMAP_DMA_CSFI(lch));
 184 }
 185
 186 void omap_set_dma_src_data_pack(int lch, int enable)
 187 {
 188         u16 w;
 189
 190         w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 6);
 191         w |= enable ? (1 << 6) : 0;
 192         omap_writew(w, OMAP_DMA_CSDP(lch));
 193 }
 194
 195 void omap_set_dma_src_burst_mode(int lch, int burst_mode)
 196 {
 197         u16 w;
 198
 199         w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 7);
 200         switch (burst_mode) {
 201         case OMAP_DMA_DATA_BURST_4:
 202                 w |= (0x01 << 7);
 203                 break;
 204         case OMAP_DMA_DATA_BURST_8:
 205                 w |= (0x03 << 7);
 206                 break;
 207         default:
 208                 printk(KERN_ERR "Invalid DMA burst mode\n");
 209                 BUG();
 210                 return;
 211         }
 212         omap_writew(w, OMAP_DMA_CSDP(lch));
 213 }
 214
 215 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 216                               unsigned long dest_start)
 217 {
 218         u16 w;
 219
 220         w = omap_readw(OMAP_DMA_CSDP(lch));
 221         w &= ~(0x1f << 9);
 222         w |= dest_port << 9;
 223         omap_writew(w, OMAP_DMA_CSDP(lch));
 224
 225         w = omap_readw(OMAP_DMA_CCR(lch));
 226         w &= ~(0x03 << 14);
 227         w |= dest_amode << 14;
 228         omap_writew(w, OMAP_DMA_CCR(lch));
 229
 230         omap_writew(dest_start >> 16, OMAP_DMA_CDSA_U(lch));
 231         omap_writew(dest_start, OMAP_DMA_CDSA_L(lch));
 232 }
 233
 234 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 235 {
 236         omap_writew(eidx, OMAP_DMA_CDEI(lch));
 237         omap_writew(fidx, OMAP_DMA_CDFI(lch));
 238 }
 239
 240 void omap_set_dma_dest_data_pack(int lch, int enable)
 241 {
 242         u16 w;
 243
 244         w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 13);
 245         w |= enable ? (1 << 13) : 0;
 246         omap_writew(w, OMAP_DMA_CSDP(lch));
 247 }
 248
 249 void omap_set_dma_dest_burst_mode(int lch, int burst_mode)
 250 {
 251         u16 w;
 252
 253         w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 14);
 254         switch (burst_mode) {
 255         case OMAP_DMA_DATA_BURST_4:
 256                 w |= (0x01 << 14);
 257                 break;
 258         case OMAP_DMA_DATA_BURST_8:
 259                 w |= (0x03 << 14);
 260                 break;
 261         default:
 262                 printk(KERN_ERR "Invalid DMA burst mode\n");
 263                 BUG();
 264                 return;
 265         }
 266         omap_writew(w, OMAP_DMA_CSDP(lch));
 267 }
 268
 269 static inline void init_intr(int lch)
 270 {
 271         u16 w;
 272
 273         /* Read CSR to make sure it's cleared. */
 274         w = omap_readw(OMAP_DMA_CSR(lch));
 275         /* Enable some nice interrupts. */
 276         omap_writew(dma_chan[lch].enabled_irqs, OMAP_DMA_CICR(lch));
 277         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 278 }
 279
 280 static inline void enable_lnk(int lch)
 281 {
 282         u16 w;
 283
 284         /* Clear the STOP_LNK bits */
 285         w = omap_readw(OMAP_DMA_CLNK_CTRL(lch));
 286         w &= ~(1 << 14);
 287         omap_writew(w, OMAP_DMA_CLNK_CTRL(lch));
 288
 289         /* And set the ENABLE_LNK bits */
 290         if (dma_chan[lch].next_lch != -1)
 291                 omap_writew(dma_chan[lch].next_lch | (1 << 15),
 292                             OMAP_DMA_CLNK_CTRL(lch));
 293 }
 294
 295 static inline void disable_lnk(int lch)
 296 {
 297         u16 w;
 298
 299         /* Disable interrupts */
 300         omap_writew(0, OMAP_DMA_CICR(lch));
 301
 302         /* Set the STOP_LNK bit */
 303         w = omap_readw(OMAP_DMA_CLNK_CTRL(lch));
 304         w |= (1 << 14);
 305         w = omap_writew(w, OMAP_DMA_CLNK_CTRL(lch));
 306
 307         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 308 }
 309
 310 void omap_start_dma(int lch)
 311 {
 312         u16 w;
 313
 314         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 315                 int next_lch, cur_lch;
 316                 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
 317
 318                 dma_chan_link_map[lch] = 1;
 319                 /* Set the link register of the first channel */
 320                 enable_lnk(lch);
 321
 322                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 323                 cur_lch = dma_chan[lch].next_lch;
 324                 do {
 325                         next_lch = dma_chan[cur_lch].next_lch;
 326
 327                         /* The loop case: we've been here already */
 328                         if (dma_chan_link_map[cur_lch])
 329                                 break;
 330                         /* Mark the current channel */
 331                         dma_chan_link_map[cur_lch] = 1;
 332
 333                         enable_lnk(cur_lch);
 334                         init_intr(cur_lch);
 335
 336                         cur_lch = next_lch;
 337                 } while (next_lch != -1);
 338         }
 339
 340         init_intr(lch);
 341
 342         w = omap_readw(OMAP_DMA_CCR(lch));
 343         w |= OMAP_DMA_CCR_EN;
 344         omap_writew(w, OMAP_DMA_CCR(lch));
 345         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 346 }
 347
 348 void omap_stop_dma(int lch)
 349 {
 350         u16 w;
 351
 352         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 353                 int next_lch, cur_lch = lch;
 354                 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
 355
 356                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 357                 do {
 358                         /* The loop case: we've been here already */
 359                         if (dma_chan_link_map[cur_lch])
 360                                 break;
 361                         /* Mark the current channel */
 362                         dma_chan_link_map[cur_lch] = 1;
 363
 364                         disable_lnk(cur_lch);
 365
 366                         next_lch = dma_chan[cur_lch].next_lch;
 367                         cur_lch = next_lch;
 368                 } while (next_lch != -1);
 369
 370                 return;
 371         }
 372         /* Disable all interrupts on the channel */
 373         omap_writew(0, OMAP_DMA_CICR(lch));
 374
 375         w = omap_readw(OMAP_DMA_CCR(lch));
 376         w &= ~OMAP_DMA_CCR_EN;
 377         omap_writew(w, OMAP_DMA_CCR(lch));
 378         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 379 }
 380
 381 void omap_enable_dma_irq(int lch, u16 bits)
 382 {
 383         dma_chan[lch].enabled_irqs |= bits;
 384 }
 385
 386 void omap_disable_dma_irq(int lch, u16 bits)
 387 {
 388         dma_chan[lch].enabled_irqs &= ~bits;
 389 }
 390
 391 static int dma_handle_ch(int ch)
 392 {
 393         u16 csr;
 394
 395         if (enable_1510_mode && ch >= 6) {
 396                 csr = dma_chan[ch].saved_csr;
 397                 dma_chan[ch].saved_csr = 0;
 398         } else
 399                 csr = omap_readw(OMAP_DMA_CSR(ch));
 400         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
 401                 dma_chan[ch + 6].saved_csr = csr >> 7;
 402                 csr &= 0x7f;
 403         }
 404         if (!csr)
 405                 return 0;
 406         if (unlikely(dma_chan[ch].dev_id == -1)) {
 407                 printk(KERN_WARNING "Spurious interrupt from DMA channel %d (CSR %04x)\n",
 408                        ch, csr);
 409                 return 0;
 410         }
 411         if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
 412                 printk(KERN_WARNING "DMA timeout with device %d\n", dma_chan[ch].dev_id);
 413         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
 414                 printk(KERN_WARNING "DMA synchronization event drop occurred with device %d\n",
 415                        dma_chan[ch].dev_id);
 416         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
 417                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
 418         if (likely(dma_chan[ch].callback != NULL))
 419                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
 420         return 1;
 421 }
 422
 423 static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 424 {
 425         int ch = ((int) dev_id) - 1;
 426         int handled = 0;
 427
 428         for (;;) {
 429                 int handled_now = 0;
 430
 431                 handled_now += dma_handle_ch(ch);
 432                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
 433                         handled_now += dma_handle_ch(ch + 6);
 434                 if (!handled_now)
 435                         break;
 436                 handled += handled_now;
 437         }
 438
 439         return handled ? IRQ_HANDLED : IRQ_NONE;
 440 }
 441
 442 int omap_request_dma(int dev_id, const char *dev_name,
 443                      void (* callback)(int lch, u16 ch_status, void *data),
 444                      void *data, int *dma_ch_out)
 445 {
 446         int ch, free_ch = -1;
 447         unsigned long flags;
 448         struct omap_dma_lch *chan;
 449
 450         spin_lock_irqsave(&dma_chan_lock, flags);
 451         for (ch = 0; ch < dma_chan_count; ch++) {
 452                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 453                         free_ch = ch;
 454                         if (dev_id == 0)
 455                                 break;
 456                 }
 457                 if (dev_id != 0 && dma_chan[ch].dev_id == dev_id) {
 458                         spin_unlock_irqrestore(&dma_chan_lock, flags);
 459                         return -EAGAIN;
 460                 }
 461         }
 462         if (free_ch == -1) {
 463                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 464                 return -EBUSY;
 465         }
 466         chan = dma_chan + free_ch;
 467         chan->dev_id = dev_id;
 468         clear_lch_regs(free_ch);
 469         spin_unlock_irqrestore(&dma_chan_lock, flags);
 470
 471         chan->dev_id = dev_id;
 472         chan->dev_name = dev_name;
 473         chan->callback = callback;
 474         chan->data = data;
 475         chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 476
 477         if (cpu_is_omap1610() || cpu_is_omap5912() || cpu_is_omap730() || cpu_is_omap1710()) {
 478                 /* If the sync device is set, configure it dynamically. */
 479                 if (dev_id != 0) {
 480                         set_gdma_dev(free_ch + 1, dev_id);
 481                         dev_id = free_ch + 1;
 482                 }
 483                 /* Disable the 1510 compatibility mode and set the sync device
 484                  * id. */
 485                 omap_writew(dev_id | (1 << 10), OMAP_DMA_CCR(free_ch));
 486         } else {
 487                 omap_writew(dev_id, OMAP_DMA_CCR(free_ch));
 488         }
 489         *dma_ch_out = free_ch;
 490
 491         return 0;
 492 }
 493
 494 void omap_free_dma(int ch)
 495 {
 496         unsigned long flags;
 497
 498         spin_lock_irqsave(&dma_chan_lock, flags);
 499         if (dma_chan[ch].dev_id == -1) {
 500                 printk("omap_dma: trying to free nonallocated DMA channel %d\n", ch);
 501                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 502                 return;
 503         }
 504         dma_chan[ch].dev_id = -1;
 505         spin_unlock_irqrestore(&dma_chan_lock, flags);
 506
 507         /* Disable all DMA interrupts for the channel. */
 508         omap_writew(0, OMAP_DMA_CICR(ch));
 509         /* Make sure the DMA transfer is stopped. */
 510         omap_writew(0, OMAP_DMA_CCR(ch));
 511 }
 512
 513 int omap_dma_in_1510_mode(void)
 514 {
 515         return enable_1510_mode;
 516 }
 517
 518 /*
 519  * lch_queue DMA will start right after lch_head one is finished.
 520  * For this DMA link to start, you still need to start (see omap_start_dma)
 521  * the first one. That will fire up the entire queue.
 522  */
 523 void omap_dma_link_lch (int lch_head, int lch_queue)
 524 {
 525         if (omap_dma_in_1510_mode()) {
 526                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
 527                 BUG();
 528                 return;
 529         }
 530
 531         if ((dma_chan[lch_head].dev_id == -1) ||
 532             (dma_chan[lch_queue].dev_id == -1)) {
 533                 printk(KERN_ERR "omap_dma: trying to link non requested channels\n");
 534                 dump_stack();
 535         }
 536
 537         dma_chan[lch_head].next_lch = lch_queue;
 538 }
 539
 540 /*
 541  * Once the DMA queue is stopped, we can destroy it.
 542  */
 543 void omap_dma_unlink_lch (int lch_head, int lch_queue)
 544 {
 545         if (omap_dma_in_1510_mode()) {
 546                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
 547                 BUG();
 548                 return;
 549         }
 550
 551         if (dma_chan[lch_head].next_lch != lch_queue ||
 552             dma_chan[lch_head].next_lch == -1) {
 553                 printk(KERN_ERR "omap_dma: trying to unlink non linked channels\n");
 554                 dump_stack();
 555         }
 556
 557
 558         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
 559             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
 560                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels before unlinking\n");
 561                 dump_stack();
 562         }
 563
 564         dma_chan[lch_head].next_lch = -1;
 565 }
 566
 567
 568 static struct lcd_dma_info {
 569         spinlock_t lock;
 570         int reserved;
 571         void (* callback)(u16 status, void *data);
 572         void *cb_data;
 573
 574         unsigned long addr, size;
 575         int rotate, data_type, xres, yres;
 576 } lcd_dma;
 577
 578 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
 579                          int data_type)
 580 {
 581         lcd_dma.addr = addr;
 582         lcd_dma.data_type = data_type;
 583         lcd_dma.xres = fb_xres;
 584         lcd_dma.yres = fb_yres;
 585 }
 586
 587 static void set_b1_regs(void)
 588 {
 589         unsigned long top, bottom;
 590         int es;
 591         u16 w, en, fn;
 592         s16 ei;
 593         s32 fi;
 594         u32 l;
 595
 596         switch (lcd_dma.data_type) {
 597         case OMAP_DMA_DATA_TYPE_S8:
 598                 es = 1;
 599                 break;
 600         case OMAP_DMA_DATA_TYPE_S16:
 601                 es = 2;
 602                 break;
 603         case OMAP_DMA_DATA_TYPE_S32:
 604                 es = 4;
 605                 break;
 606         default:
 607                 BUG();
 608                 return;
 609         }
 610
 611         if (lcd_dma.rotate == 0) {
 612                 top = lcd_dma.addr;
 613                 bottom = lcd_dma.addr + (lcd_dma.xres * lcd_dma.yres - 1) * es;
 614                 /* 1510 DMA requires the bottom address to be 2 more than the
 615                  * actual last memory access location. */
 616                 if (omap_dma_in_1510_mode() &&
 617                     lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
 618                         bottom += 2;
 619                 en = lcd_dma.xres;
 620                 fn = lcd_dma.yres;
 621                 ei = 0;
 622                 fi = 0;
 623         } else {
 624                 top = lcd_dma.addr + (lcd_dma.xres - 1) * es;
 625                 bottom = lcd_dma.addr + (lcd_dma.yres - 1) * lcd_dma.xres * es;
 626                 en = lcd_dma.yres;
 627                 fn = lcd_dma.xres;
 628                 ei = (lcd_dma.xres - 1) * es + 1;
 629                 fi = -(lcd_dma.xres * (lcd_dma.yres - 1) + 2) * 2 + 1;
 630         }
 631
 632         if (omap_dma_in_1510_mode()) {
 633                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
 634                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
 635                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
 636                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
 637
 638                 return;
 639         }
 640
 641         /* 1610 regs */
 642         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
 643         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
 644         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
 645         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
 646
 647         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
 648         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
 649
 650         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
 651         w &= ~0x03;
 652         w |= lcd_dma.data_type;
 653         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
 654
 655         if (!lcd_dma.rotate)
 656                 return;
 657
 658         /* Rotation stuff */
 659         l = omap_readw(OMAP1610_DMA_LCD_CSDP);
 660         /* Disable burst access */
 661         l &= ~(0x03 << 7);
 662         omap_writew(l, OMAP1610_DMA_LCD_CSDP);
 663
 664         l = omap_readw(OMAP1610_DMA_LCD_CCR);
 665         /* Set the double-indexed addressing mode */
 666         l |= (0x03 << 12);
 667         omap_writew(l, OMAP1610_DMA_LCD_CCR);
 668
 669         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
 670         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
 671         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
 672 }
 673
 674 void omap_set_lcd_dma_b1_rotation(int rotate)
 675 {
 676         if (omap_dma_in_1510_mode()) {
 677                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
 678                 BUG();
 679                 return;
 680         }
 681         lcd_dma.rotate = rotate;
 682 }
 683
 684 int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
 685                          void *data)
 686 {
 687         spin_lock_irq(&lcd_dma.lock);
 688         if (lcd_dma.reserved) {
 689                 spin_unlock_irq(&lcd_dma.lock);
 690                 printk(KERN_ERR "LCD DMA channel already reserved\n");
 691                 BUG();
 692                 return -EBUSY;
 693         }
 694         lcd_dma.reserved = 1;
 695         spin_unlock_irq(&lcd_dma.lock);
 696         lcd_dma.callback = callback;
 697         lcd_dma.cb_data = data;
 698
 699         return 0;
 700 }
 701
 702 void omap_free_lcd_dma(void)
 703 {
 704         spin_lock(&lcd_dma.lock);
 705         if (!lcd_dma.reserved) {
 706                 spin_unlock(&lcd_dma.lock);
 707                 printk(KERN_ERR "LCD DMA is not reserved\n");
 708                 BUG();
 709                 return;
 710         }
 711         if (!enable_1510_mode)
 712                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR);
 713         lcd_dma.reserved = 0;
 714         spin_unlock(&lcd_dma.lock);
 715 }
 716
 717 void omap_start_lcd_dma(void)
 718 {
 719         if (!enable_1510_mode) {
 720                 /* Set some reasonable defaults */
 721                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
 722                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
 723                 omap_writew(0x5740, OMAP1610_DMA_LCD_CCR);
 724         }
 725         set_b1_regs();
 726         if (!enable_1510_mode)
 727                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) | 1, OMAP1610_DMA_LCD_CCR);
 728 }
 729
 730 void omap_stop_lcd_dma(void)
 731 {
 732         if (!enable_1510_mode)
 733                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR);
 734 }
 735
 736 static int __init omap_init_dma(void)
 737 {
 738         int ch, r;
 739
 740         if (cpu_is_omap1510()) {
 741                 printk(KERN_INFO "DMA support for OMAP1510 initialized\n");
 742                 dma_chan_count = 9;
 743                 enable_1510_mode = 1;
 744         } else if (cpu_is_omap1610() || cpu_is_omap5912() || cpu_is_omap730() || cpu_is_omap1710()) {
 745                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
 746                        omap_readw(OMAP_DMA_HW_ID));
 747                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
 748                        (omap_readw(OMAP_DMA_CAPS_0_U) << 16) | omap_readw(OMAP_DMA_CAPS_0_L),
 749                        (omap_readw(OMAP_DMA_CAPS_1_U) << 16) | omap_readw(OMAP_DMA_CAPS_1_L),
 750                        omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
 751                        omap_readw(OMAP_DMA_CAPS_4));
 752                 if (!enable_1510_mode) {
 753                         u16 w;
 754
 755                         /* Disable OMAP 3.0/3.1 compatibility mode. */
 756                         w = omap_readw(OMAP_DMA_GSCR);
 757                         w |= 1 << 3;
 758                         omap_writew(w, OMAP_DMA_GSCR);
 759                         dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
 760                 } else
 761                         dma_chan_count = 9;
 762         } else {
 763                 dma_chan_count = 0;
 764                 return 0;
 765         }
 766
 767         memset(&lcd_dma, 0, sizeof(lcd_dma));
 768         spin_lock_init(&lcd_dma.lock);
 769         spin_lock_init(&dma_chan_lock);
 770         memset(&dma_chan, 0, sizeof(dma_chan));
 771
 772         for (ch = 0; ch < dma_chan_count; ch++) {
 773                 dma_chan[ch].dev_id = -1;
 774                 dma_chan[ch].next_lch = -1;
 775
 776                 if (ch >= 6 && enable_1510_mode)
 777                         continue;
 778
 779                 /* request_irq() doesn't like dev_id (ie. ch) being zero,
 780                  * so we have to kludge around this. */
 781                 r = request_irq(dma_irq[ch], dma_irq_handler, 0, "DMA",
 782                                 (void *) (ch + 1));
 783                 if (r != 0) {
 784                         int i;
 785
 786                         printk(KERN_ERR "unable to request IRQ %d for DMA (error %d)\n",
 787                                dma_irq[ch], r);
 788                         for (i = 0; i < ch; i++)
 789                                 free_irq(dma_irq[i], (void *) (i + 1));
 790                         return r;
 791                 }
 792         }
 793
 794         return 0;
 795 }
 796 arch_initcall(omap_init_dma);
 797
 798 EXPORT_SYMBOL(omap_request_dma);
 799 EXPORT_SYMBOL(omap_free_dma);
 800 EXPORT_SYMBOL(omap_start_dma);
 801 EXPORT_SYMBOL(omap_stop_dma);
 802 EXPORT_SYMBOL(omap_enable_dma_irq);
 803 EXPORT_SYMBOL(omap_disable_dma_irq);
 804
 805 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 806 EXPORT_SYMBOL(omap_set_dma_constant_fill);
 807 EXPORT_SYMBOL(omap_set_dma_transparent_copy);
 808
 809 EXPORT_SYMBOL(omap_set_dma_src_params);
 810 EXPORT_SYMBOL(omap_set_dma_src_index);
 811 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 812 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 813
 814 EXPORT_SYMBOL(omap_set_dma_dest_params);
 815 EXPORT_SYMBOL(omap_set_dma_dest_index);
 816 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 817 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 818
 819 EXPORT_SYMBOL(omap_dma_link_lch);
 820 EXPORT_SYMBOL(omap_dma_unlink_lch);
 821
 822 EXPORT_SYMBOL(omap_request_lcd_dma);
 823 EXPORT_SYMBOL(omap_free_lcd_dma);
 824 EXPORT_SYMBOL(omap_start_lcd_dma);
 825 EXPORT_SYMBOL(omap_stop_lcd_dma);
 826 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
 827 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);