2 * linux/arch/arm/mach-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/interrupt.h>
19 #include <linux/ptrace.h>
21 #include <asm/hardware.h>
23 #include <asm/arch/irqs.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/pm.h>
26 #include <asm/mach/irq.h>
31 * OMAP1510 GPIO registers
33 #define OMAP1510_GPIO_BASE 0xfffce000
34 #define OMAP1510_GPIO_DATA_INPUT 0x00
35 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
36 #define OMAP1510_GPIO_DIR_CONTROL 0x08
37 #define OMAP1510_GPIO_INT_CONTROL 0x0c
38 #define OMAP1510_GPIO_INT_MASK 0x10
39 #define OMAP1510_GPIO_INT_STATUS 0x14
40 #define OMAP1510_GPIO_PIN_CONTROL 0x18
42 #define OMAP1510_IH_GPIO_BASE 64
45 * OMAP1610 specific GPIO registers
47 #define OMAP1610_GPIO1_BASE 0xfffbe400
48 #define OMAP1610_GPIO2_BASE 0xfffbec00
49 #define OMAP1610_GPIO3_BASE 0xfffbb400
50 #define OMAP1610_GPIO4_BASE 0xfffbbc00
51 #define OMAP1610_GPIO_REVISION 0x0000
52 #define OMAP1610_GPIO_SYSCONFIG 0x0010
53 #define OMAP1610_GPIO_SYSSTATUS 0x0014
54 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
55 #define OMAP1610_GPIO_IRQENABLE1 0x001c
56 #define OMAP1610_GPIO_DATAIN 0x002c
57 #define OMAP1610_GPIO_DATAOUT 0x0030
58 #define OMAP1610_GPIO_DIRECTION 0x0034
59 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
67 * OMAP730 specific GPIO registers
69 #define OMAP730_GPIO1_BASE 0xfffbc000
70 #define OMAP730_GPIO2_BASE 0xfffbc800
71 #define OMAP730_GPIO3_BASE 0xfffbd000
72 #define OMAP730_GPIO4_BASE 0xfffbd800
73 #define OMAP730_GPIO5_BASE 0xfffbe000
74 #define OMAP730_GPIO6_BASE 0xfffbe800
75 #define OMAP730_GPIO_DATA_INPUT 0x00
76 #define OMAP730_GPIO_DATA_OUTPUT 0x04
77 #define OMAP730_GPIO_DIR_CONTROL 0x08
78 #define OMAP730_GPIO_INT_CONTROL 0x0c
79 #define OMAP730_GPIO_INT_MASK 0x10
80 #define OMAP730_GPIO_INT_STATUS 0x14
82 #define OMAP_MPUIO_MASK (~OMAP_MAX_GPIO_LINES & 0xff)
87 u16 virtual_irq_start;
93 #define METHOD_MPUIO 0
94 #define METHOD_GPIO_1510 1
95 #define METHOD_GPIO_1610 2
96 #define METHOD_GPIO_730 3
98 #if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
99 static struct gpio_bank gpio_bank_1610[5] = {
100 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
101 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
102 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
103 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
104 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
108 #ifdef CONFIG_ARCH_OMAP1510
109 static struct gpio_bank gpio_bank_1510[2] = {
110 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
111 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
115 #ifdef CONFIG_ARCH_OMAP730
116 static struct gpio_bank gpio_bank_730[7] = {
117 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
118 { OMAP730_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
119 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
120 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
121 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
122 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
123 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
127 static struct gpio_bank *gpio_bank;
128 static int gpio_bank_count;
130 static inline struct gpio_bank *get_gpio_bank(int gpio)
132 #ifdef CONFIG_ARCH_OMAP1510
133 if (cpu_is_omap1510()) {
134 if (OMAP_GPIO_IS_MPUIO(gpio))
135 return &gpio_bank[0];
136 return &gpio_bank[1];
139 #if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
140 if (cpu_is_omap1610() || cpu_is_omap5912()) {
141 if (OMAP_GPIO_IS_MPUIO(gpio))
142 return &gpio_bank[0];
143 return &gpio_bank[1 + (gpio >> 4)];
146 #ifdef CONFIG_ARCH_OMAP730
147 if (cpu_is_omap730()) {
148 if (OMAP_GPIO_IS_MPUIO(gpio))
149 return &gpio_bank[0];
150 return &gpio_bank[1 + (gpio >> 5)];
155 static inline int get_gpio_index(int gpio)
157 if (cpu_is_omap730())
163 static inline int gpio_valid(int gpio)
167 if (OMAP_GPIO_IS_MPUIO(gpio)) {
168 if ((gpio & OMAP_MPUIO_MASK) > 16)
172 #ifdef CONFIG_ARCH_OMAP1510
173 if (cpu_is_omap1510() && gpio < 16)
176 #if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
177 if ((cpu_is_omap1610() || cpu_is_omap5912()) && gpio < 64)
180 #ifdef CONFIG_ARCH_OMAP730
181 if (cpu_is_omap730() && gpio < 192)
187 static int check_gpio(int gpio)
189 if (unlikely(gpio_valid(gpio)) < 0) {
190 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
197 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
199 u32 reg = bank->base;
202 switch (bank->method) {
204 reg += OMAP_MPUIO_IO_CNTL;
206 case METHOD_GPIO_1510:
207 reg += OMAP1510_GPIO_DIR_CONTROL;
209 case METHOD_GPIO_1610:
210 reg += OMAP1610_GPIO_DIRECTION;
212 case METHOD_GPIO_730:
213 reg += OMAP730_GPIO_DIR_CONTROL;
224 void omap_set_gpio_direction(int gpio, int is_input)
226 struct gpio_bank *bank;
228 if (check_gpio(gpio) < 0)
230 bank = get_gpio_bank(gpio);
231 spin_lock(&bank->lock);
232 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
233 spin_unlock(&bank->lock);
236 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
238 u32 reg = bank->base;
241 switch (bank->method) {
243 reg += OMAP_MPUIO_OUTPUT_REG;
250 case METHOD_GPIO_1510:
251 reg += OMAP1510_GPIO_DATA_OUTPUT;
258 case METHOD_GPIO_1610:
260 reg += OMAP1610_GPIO_SET_DATAOUT;
262 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
265 case METHOD_GPIO_730:
266 reg += OMAP730_GPIO_DATA_OUTPUT;
280 void omap_set_gpio_dataout(int gpio, int enable)
282 struct gpio_bank *bank;
284 if (check_gpio(gpio) < 0)
286 bank = get_gpio_bank(gpio);
287 spin_lock(&bank->lock);
288 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
289 spin_unlock(&bank->lock);
292 int omap_get_gpio_datain(int gpio)
294 struct gpio_bank *bank;
297 if (check_gpio(gpio) < 0)
299 bank = get_gpio_bank(gpio);
301 switch (bank->method) {
303 reg += OMAP_MPUIO_INPUT_LATCH;
305 case METHOD_GPIO_1510:
306 reg += OMAP1510_GPIO_DATA_INPUT;
308 case METHOD_GPIO_1610:
309 reg += OMAP1610_GPIO_DATAIN;
315 return (omap_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
318 static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge)
320 u32 reg = bank->base;
323 switch (bank->method) {
325 reg += OMAP_MPUIO_GPIO_INT_EDGE_REG;
327 if (edge == OMAP_GPIO_RISING_EDGE)
333 case METHOD_GPIO_1510:
334 reg += OMAP1510_GPIO_INT_CONTROL;
336 if (edge == OMAP_GPIO_RISING_EDGE)
342 case METHOD_GPIO_1610:
345 reg += OMAP1610_GPIO_EDGE_CTRL2;
347 reg += OMAP1610_GPIO_EDGE_CTRL1;
350 l &= ~(3 << (gpio << 1));
351 l |= edge << (gpio << 1);
354 case METHOD_GPIO_730:
355 reg += OMAP730_GPIO_INT_CONTROL;
357 if (edge == OMAP_GPIO_RISING_EDGE)
369 void omap_set_gpio_edge_ctrl(int gpio, int edge)
371 struct gpio_bank *bank;
373 if (check_gpio(gpio) < 0)
375 bank = get_gpio_bank(gpio);
376 spin_lock(&bank->lock);
377 _set_gpio_edge_ctrl(bank, get_gpio_index(gpio), edge);
378 spin_unlock(&bank->lock);
382 static int _get_gpio_edge_ctrl(struct gpio_bank *bank, int gpio)
384 u32 reg = bank->base, l;
386 switch (bank->method) {
388 l = omap_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE_REG);
389 return (l & (1 << gpio)) ?
390 OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
391 case METHOD_GPIO_1510:
392 l = omap_readl(reg + OMAP1510_GPIO_INT_CONTROL);
393 return (l & (1 << gpio)) ?
394 OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
395 case METHOD_GPIO_1610:
397 reg += OMAP1610_GPIO_EDGE_CTRL2;
399 reg += OMAP1610_GPIO_EDGE_CTRL1;
400 return (omap_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03;
401 case METHOD_GPIO_730:
402 l = omap_readl(reg + OMAP730_GPIO_INT_CONTROL);
403 return (l & (1 << gpio)) ?
404 OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
411 static void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
413 u32 reg = bank->base;
415 switch (bank->method) {
417 /* MPUIO irqstatus cannot be cleared one bit at a time,
418 * so do nothing here */
420 case METHOD_GPIO_1510:
421 reg += OMAP1510_GPIO_INT_STATUS;
423 case METHOD_GPIO_1610:
424 reg += OMAP1610_GPIO_IRQSTATUS1;
426 case METHOD_GPIO_730:
427 reg += OMAP730_GPIO_INT_STATUS;
433 omap_writel(1 << get_gpio_index(gpio), reg);
436 static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
438 u32 reg = bank->base;
441 switch (bank->method) {
443 reg += OMAP_MPUIO_GPIO_MASKIT;
450 case METHOD_GPIO_1510:
451 reg += OMAP1510_GPIO_INT_MASK;
458 case METHOD_GPIO_1610:
460 reg += OMAP1610_GPIO_SET_IRQENABLE1;
461 _clear_gpio_irqstatus(bank, gpio);
463 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
466 case METHOD_GPIO_730:
467 reg += OMAP730_GPIO_INT_MASK;
481 int omap_request_gpio(int gpio)
483 struct gpio_bank *bank;
485 if (check_gpio(gpio) < 0)
488 bank = get_gpio_bank(gpio);
489 spin_lock(&bank->lock);
490 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
491 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
493 spin_unlock(&bank->lock);
496 bank->reserved_map |= (1 << get_gpio_index(gpio));
497 #ifdef CONFIG_ARCH_OMAP1510
498 if (bank->method == METHOD_GPIO_1510) {
501 /* Claim the pin for the ARM */
502 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
503 omap_writel(omap_readl(reg) | (1 << get_gpio_index(gpio)), reg);
506 spin_unlock(&bank->lock);
511 void omap_free_gpio(int gpio)
513 struct gpio_bank *bank;
515 if (check_gpio(gpio) < 0)
517 bank = get_gpio_bank(gpio);
518 spin_lock(&bank->lock);
519 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
520 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
522 spin_unlock(&bank->lock);
525 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
526 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
527 _set_gpio_irqenable(bank, get_gpio_index(gpio), 0);
528 spin_unlock(&bank->lock);
531 static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
532 struct pt_regs *regs)
535 struct gpio_bank *bank = (struct gpio_bank *) desc->data;
538 * Acknowledge the parent IRQ.
540 desc->chip->ack(irq);
542 /* Since the level 1 GPIO interrupt cascade (IRQ14) is configured as
543 * edge-sensitive, we need to unmask it here in order to avoid missing
544 * any additional GPIO interrupts that might occur after the last time
545 * we check for pending GPIO interrupts here.
546 * We are relying on the fact that this interrupt handler was installed
547 * with the SA_INTERRUPT flag so that interrupts are disabled at the
548 * CPU while it is executing.
550 desc->chip->unmask(irq);
552 if (bank->method == METHOD_MPUIO)
553 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
554 #ifdef CONFIG_ARCH_OMAP1510
555 if (bank->method == METHOD_GPIO_1510)
556 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
558 #if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
559 if (bank->method == METHOD_GPIO_1610)
560 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
562 #ifdef CONFIG_ARCH_OMAP730
563 if (bank->method == METHOD_GPIO_730)
564 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
567 u32 isr = omap_readl(isr_reg);
568 unsigned int gpio_irq;
572 gpio_irq = bank->virtual_irq_start;
574 for (; isr != 0; isr >>= 1, gpio_irq++) {
576 struct irqdesc *d = irq_desc + gpio_irq;
577 d->handle(gpio_irq, d, regs);
583 static void gpio_ack_irq(unsigned int irq)
585 unsigned int gpio = irq - IH_GPIO_BASE;
586 struct gpio_bank *bank = get_gpio_bank(gpio);
588 #ifdef CONFIG_ARCH_OMAP1510
589 if (bank->method == METHOD_GPIO_1510)
590 omap_writew(1 << gpio, bank->base + OMAP1510_GPIO_INT_STATUS);
592 #if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
593 if (bank->method == METHOD_GPIO_1610)
594 omap_writew(1 << gpio, bank->base + OMAP1610_GPIO_IRQSTATUS1);
596 #ifdef CONFIG_ARCH_OMAP730
597 if (bank->method == METHOD_GPIO_730)
598 omap_writel(1 << gpio, bank->base + OMAP730_GPIO_INT_STATUS);
602 static void gpio_mask_irq(unsigned int irq)
604 unsigned int gpio = irq - IH_GPIO_BASE;
605 struct gpio_bank *bank = get_gpio_bank(gpio);
607 _set_gpio_irqenable(bank, get_gpio_index(gpio), 0);
610 static void gpio_unmask_irq(unsigned int irq)
612 unsigned int gpio = irq - IH_GPIO_BASE;
613 struct gpio_bank *bank = get_gpio_bank(gpio);
615 if (_get_gpio_edge_ctrl(bank, get_gpio_index(gpio)) == OMAP_GPIO_NO_EDGE) {
616 printk(KERN_ERR "OMAP GPIO %d: trying to enable GPIO IRQ while no edge is set\n",
618 _set_gpio_edge_ctrl(bank, get_gpio_index(gpio), OMAP_GPIO_RISING_EDGE);
620 _set_gpio_irqenable(bank, get_gpio_index(gpio), 1);
623 static void mpuio_ack_irq(unsigned int irq)
625 /* The ISR is reset automatically, so do nothing here. */
628 static void mpuio_mask_irq(unsigned int irq)
630 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
631 struct gpio_bank *bank = get_gpio_bank(gpio);
633 _set_gpio_irqenable(bank, gpio, 0);
636 static void mpuio_unmask_irq(unsigned int irq)
638 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
639 struct gpio_bank *bank = get_gpio_bank(gpio);
641 _set_gpio_irqenable(bank, gpio, 1);
644 static struct irqchip gpio_irq_chip = {
646 .mask = gpio_mask_irq,
647 .unmask = gpio_unmask_irq,
650 static struct irqchip mpuio_irq_chip = {
651 .ack = mpuio_ack_irq,
652 .mask = mpuio_mask_irq,
653 .unmask = mpuio_unmask_irq
656 static int initialized = 0;
658 static int __init _omap_gpio_init(void)
661 struct gpio_bank *bank;
665 #ifdef CONFIG_ARCH_OMAP1510
666 if (cpu_is_omap1510()) {
667 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
669 gpio_bank = gpio_bank_1510;
672 #if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
673 if (cpu_is_omap1610() || cpu_is_omap5912()) {
677 gpio_bank = gpio_bank_1610;
678 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
679 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
680 (rev >> 4) & 0x0f, rev & 0x0f);
683 #ifdef CONFIG_ARCH_OMAP730
684 if (cpu_is_omap730()) {
685 printk(KERN_INFO "OMAP730 GPIO hardware\n");
687 gpio_bank = gpio_bank_730;
690 for (i = 0; i < gpio_bank_count; i++) {
691 int j, gpio_count = 16;
693 bank = &gpio_bank[i];
694 bank->reserved_map = 0;
695 spin_lock_init(&bank->lock);
696 if (bank->method == METHOD_MPUIO) {
697 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
699 #ifdef CONFIG_ARCH_OMAP1510
700 if (bank->method == METHOD_GPIO_1510) {
701 omap_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
702 omap_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
705 #if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
706 if (bank->method == METHOD_GPIO_1610) {
707 omap_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
708 omap_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
711 #ifdef CONFIG_ARCH_OMAP730
712 if (bank->method == METHOD_GPIO_730) {
713 omap_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
714 omap_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
716 gpio_count = 32; /* 730 has 32-bit GPIOs */
719 for (j = bank->virtual_irq_start;
720 j < bank->virtual_irq_start + gpio_count; j++) {
721 if (bank->method == METHOD_MPUIO)
722 set_irq_chip(j, &mpuio_irq_chip);
724 set_irq_chip(j, &gpio_irq_chip);
725 set_irq_handler(j, do_level_IRQ);
726 set_irq_flags(j, IRQF_VALID);
728 set_irq_chained_handler(bank->irq, gpio_irq_handler);
729 set_irq_data(bank->irq, bank);
732 /* Enable system clock for GPIO module.
733 * The CAM_CLK_CTRL_REG *is* really the right place. */
734 if (cpu_is_omap1610())
735 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL_REG) | 0x04, ULPD_CAM_CLK_CTRL_REG);
741 * This may get called early from board specific init
743 int omap_gpio_init(void)
746 return _omap_gpio_init();
751 EXPORT_SYMBOL(omap_gpio_init);
752 EXPORT_SYMBOL(omap_request_gpio);
753 EXPORT_SYMBOL(omap_free_gpio);
755 arch_initcall(omap_gpio_init);