arch/arm/mach-omap/irq.c

   1 /*
   2  * linux/arch/arm/mach-omap/irq.c
   3  *
   4  * Interrupt handler for all OMAP boards
   5  *
   6  * Copyright (C) 2004 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Completely re-written to support various OMAP chips with bank specific
  10  * interrupt handlers.
  11  *
  12  * Some snippets of the code taken from the older OMAP interrupt handler
  13  * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
  14  *
  15  * GPIO interrupt handler moved to gpio.c by Juha Yrjola
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2 of the License, or (at your
  20  * option) any later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the  GNU General Public License along
  34  * with this program; if not, write  to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/config.h>
  39 #include <linux/init.h>
  40 #include <linux/module.h>
  41 #include <linux/sched.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/ptrace.h>
  44
  45 #include <asm/hardware.h>
  46 #include <asm/irq.h>
  47 #include <asm/mach/irq.h>
  48 #include <asm/arch/gpio.h>
  49
  50 #include <asm/io.h>
  51
  52 #include "irq.h"
  53
  54 static unsigned int banks = 0;
  55 static struct omap_irq_bank irq_banks[MAX_NR_IRQ_BANKS];
  56
  57 static inline unsigned int irq_bank_readl(int bank, int offset)
  58 {
  59         return omap_readl(irq_banks[bank].base_reg + offset);
  60 }
  61
  62 static inline void irq_bank_writel(unsigned long value, int bank, int offset)
  63 {
  64         omap_writel(value, irq_banks[bank].base_reg + offset);
  65 }
  66
  67 /*
  68  * Ack routine for chips with register offsets of 0x100
  69  */
  70 static void omap_offset_ack_irq(unsigned int irq)
  71 {
  72         if (irq > 31)
  73                 omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG);
  74
  75         omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG);
  76 }
  77
  78 /*
  79  * Mask routine for chips with register offsets of 0x100
  80  */
  81 static void omap_offset_mask_irq(unsigned int irq)
  82 {
  83         int bank = IRQ_TO_BANK(irq);
  84
  85         if (bank) {
  86                 omap_writel(
  87                         omap_readl(OMAP_IH2_BASE + BANK_OFFSET(bank) + IRQ_MIR)
  88                         | (1 << IRQ_BIT(irq)),
  89                         OMAP_IH2_BASE + BANK_OFFSET(bank) + IRQ_MIR);
  90         } else {
  91                 omap_writel(
  92                         omap_readl(OMAP_IH1_BASE + IRQ_MIR)
  93                         | (1 << IRQ_BIT(irq)),
  94                         OMAP_IH1_BASE  + IRQ_MIR);
  95         }
  96 }
  97
  98 /*
  99  * Unmask routine for chips with register offsets of 0x100
 100  */
 101 static void omap_offset_unmask_irq(unsigned int irq)
 102 {
 103         int bank = IRQ_TO_BANK(irq);
 104
 105         if (bank) {
 106                 omap_writel(
 107                         omap_readl(OMAP_IH2_BASE + BANK_OFFSET(bank) + IRQ_MIR)
 108                         & ~(1 << IRQ_BIT(irq)),
 109                         OMAP_IH2_BASE + BANK_OFFSET(bank) + IRQ_MIR);
 110         } else {
 111                 omap_writel(
 112                         omap_readl(OMAP_IH1_BASE + IRQ_MIR)
 113                         & ~(1 << IRQ_BIT(irq)),
 114                         OMAP_IH1_BASE  + IRQ_MIR);
 115         }
 116 }
 117
 118 static void omap_offset_mask_ack_irq(unsigned int irq)
 119 {
 120         omap_offset_mask_irq(irq);
 121         omap_offset_ack_irq(irq);
 122 }
 123
 124 /*
 125  * Given the irq number returns the bank number
 126  */
 127 signed int irq_get_bank(unsigned int irq)
 128 {
 129         int i;
 130
 131         for (i = 0; i < banks; i++) {
 132                 if (irq >= irq_banks[i].start_irq
 133                     && irq <= irq_banks[i].start_irq + BANK_NR_IRQS) {
 134                         return i;
 135                 }
 136         }
 137
 138         printk(KERN_ERR "No irq handler found for irq %i\n", irq);
 139
 140         return -ENODEV;
 141 }
 142
 143 /*
 144  * Given the bank and irq number returns the irq bit at the bank register
 145  */
 146 signed int irq_bank_get_bit(int bank, unsigned int irq)
 147 {
 148         if (irq_banks[bank].start_irq > irq) {
 149                 printk(KERN_ERR "Incorrect irq %i: bank %i offset %i\n",
 150                        irq, bank, irq_banks[bank].start_irq);
 151                 return -ENODEV;
 152         }
 153
 154         return irq - irq_banks[bank].start_irq;
 155 }
 156
 157 /*
 158  * Allows tuning the IRQ type and priority
 159  *
 160  * NOTE: There is currently no OMAP fiq handler for Linux. Read the
 161  *       mailing list threads on FIQ handlers if you are planning to
 162  *       add a FIQ handler for OMAP.
 163  */
 164 void omap_irq_set_cfg(int irq, int fiq, int priority, int irq_level)
 165 {
 166         signed int bank;
 167         unsigned int irq_bit;
 168         unsigned long val, offset;
 169
 170
 171         bank = irq_get_bank(irq);
 172
 173         if (bank < 0)
 174                 return;
 175
 176         irq_bit = irq_bank_get_bit(bank, irq);
 177
 178         if (irq_bit < 0)
 179                 return;
 180
 181         /* FIQ is only availabe on bank 0 interrupts */
 182         fiq = bank ? 0 : (fiq & 0x1);
 183
 184         val = fiq | ((priority & 0x1f) << 2) | ((irq_level & 0x1) << 1);
 185
 186         offset = IRQ_ILR0 + irq_bit * 0x4;
 187
 188         irq_bank_writel(val, bank, offset);
 189 }
 190
 191 static struct omap_irq_desc *irq_bank_desc[] __initdata = {
 192         &omap730_bank0_irqs,
 193         &omap730_bank1_irqs,
 194         &omap730_bank2_irqs,
 195         &omap1510_bank0_irqs,
 196         &omap1510_bank1_irqs,
 197         &omap1610_bank0_irqs,
 198         &omap1610_bank1_irqs,
 199         &omap1610_bank2_irqs,
 200         &omap1610_bank3_irqs,
 201         NULL,
 202 };
 203
 204 void __init omap_init_irq(void)
 205 {
 206         int i,j, board_irq_type = 0, interrupts = 0;
 207         struct omap_irq_desc *entry;
 208
 209         if (cpu_is_omap730()) {
 210                 board_irq_type = OMAP_IRQ_TYPE730;
 211         } else if (cpu_is_omap1510()) {
 212                 board_irq_type = OMAP_IRQ_TYPE1510;
 213         } else if (cpu_is_omap1610() || cpu_is_omap5912()) {
 214                 board_irq_type = OMAP_IRQ_TYPE1610;
 215         }
 216
 217         if (board_irq_type == 0) {
 218                 printk("Could not detect OMAP type\n");
 219                 return;
 220         }
 221
 222         /* Scan through the interrupt bank maps and copy the right data */
 223         for (i = 0; (entry = irq_bank_desc[i]) != NULL; i++) {
 224                 if (entry->cpu_type == board_irq_type) {
 225                         printk("Type %i IRQs from %3i to %3i base at 0x%lx\n",
 226                                board_irq_type, entry->start_irq,
 227                                entry->start_irq + BANK_NR_IRQS, entry->base_reg);
 228
 229                         irq_banks[banks].start_irq = entry->start_irq;
 230                         irq_banks[banks].level_map = entry->level_map;
 231                         irq_banks[banks].base_reg = entry->base_reg;
 232                         irq_banks[banks].mask_reg = entry->mask_reg;
 233                         irq_banks[banks].ack_reg = entry->ack_reg;
 234                         irq_banks[banks].handler = entry->handler;
 235
 236                         interrupts += BANK_NR_IRQS;
 237                         banks++;
 238                 }
 239         }
 240
 241         printk("Found total of %i interrupts in %i interrupt banks\n",
 242                interrupts, banks);
 243
 244         /* Mask and clear all interrupts */
 245         for (i = 0; i < banks; i++) {
 246                 irq_bank_writel(~0x0, i, IRQ_MIR);
 247                 irq_bank_writel(0x0, i, IRQ_ITR);
 248         }
 249
 250         /*
 251          * Clear any pending interrupts
 252          */
 253         irq_bank_writel(3, 0, IRQ_CONTROL_REG);
 254         irq_bank_writel(3, 1, IRQ_CONTROL_REG);
 255
 256         /* Install the interrupt handlers for each bank */
 257         for (i = 0; i < banks; i++) {
 258                 for (j = irq_banks[i].start_irq;
 259                      j <= irq_banks[i].start_irq + BANK_NR_IRQS; j++) {
 260                         int irq_level;
 261                         set_irq_chip(j, irq_banks[i].handler);
 262                         set_irq_handler(j, do_level_IRQ);
 263                         set_irq_flags(j, IRQF_VALID);
 264                         irq_level = irq_banks[i].level_map
 265                                 >> (j - irq_banks[i].start_irq) & 1;
 266                         omap_irq_set_cfg(j, 0, 0, irq_level);
 267                 }
 268         }
 269
 270         /* Unmask level 2 handler */
 271         omap_writel(0, irq_banks[0].mask_reg);
 272 }
 273
 274 EXPORT_SYMBOL(omap_irq_set_cfg);