arch/arm/mach-omap/irq.h

   1 /*
   2  * linux/arch/arm/mach-omap/irq.h
   3  *
   4  * OMAP specific interrupt bank definitions
   5  *
   6  * Copyright (C) 2004 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License as published by the
  11  * Free Software Foundation; either version 2 of the License, or (at your
  12  * option) any later version.
  13  *
  14  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  15  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  16  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  17  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  20  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  * You should have received a copy of the  GNU General Public License along
  26  * with this program; if not, write  to the Free Software Foundation, Inc.,
  27  * 675 Mass Ave, Cambridge, MA 02139, USA.
  28  */
  29
  30 #define OMAP_IRQ_TYPE710        1
  31 #define OMAP_IRQ_TYPE730        2
  32 #define OMAP_IRQ_TYPE1510       3
  33 #define OMAP_IRQ_TYPE1610       4
  34 #define OMAP_IRQ_TYPE1710       5
  35
  36 #define MAX_NR_IRQ_BANKS        4
  37
  38 #define BANK_NR_IRQS            32
  39
  40 struct omap_irq_desc {
  41         unsigned int    cpu_type;
  42         unsigned int    start_irq;
  43         unsigned long   level_map;
  44         unsigned long   base_reg;
  45         unsigned long   mask_reg;
  46         unsigned long   ack_reg;
  47         struct irqchip  *handler;
  48 };
  49
  50 struct omap_irq_bank {
  51         unsigned int    start_irq;
  52         unsigned long   level_map;
  53         unsigned long   base_reg;
  54         unsigned long   mask_reg;
  55         unsigned long   ack_reg;
  56         struct irqchip  *handler;
  57 };
  58
  59 static void omap_offset_ack_irq(unsigned int irq);
  60 static void omap_offset_mask_irq(unsigned int irq);
  61 static void omap_offset_unmask_irq(unsigned int irq);
  62 static void omap_offset_mask_ack_irq(unsigned int irq);
  63
  64 /* NOTE: These will not work if irq bank offset != 0x100 */
  65 #define IRQ_TO_BANK(irq)        (irq >> 5)
  66 #define IRQ_BIT(irq)            (irq & 0x1f)
  67 #define BANK_OFFSET(bank)       ((bank - 1) * 0x100)
  68
  69 static struct irqchip omap_offset_irq = {
  70         .ack    =  omap_offset_mask_ack_irq,
  71         .mask   =  omap_offset_mask_irq,
  72         .unmask =  omap_offset_unmask_irq,
  73 };
  74
  75 /*
  76  * OMAP-730 interrupt banks
  77  */
  78 static struct omap_irq_desc omap730_bank0_irqs __initdata = {
  79         .cpu_type       = OMAP_IRQ_TYPE730,
  80         .start_irq      = 0,
  81         .level_map      = 0xb3f8e22f,
  82         .base_reg       = OMAP_IH1_BASE,
  83         .mask_reg       = OMAP_IH1_BASE + IRQ_MIR,
  84         .ack_reg        = OMAP_IH1_BASE + IRQ_CONTROL_REG,
  85         .handler        = &omap_offset_irq,     /* IH2 regs at 0x100 offsets */
  86 };
  87
  88 static struct omap_irq_desc omap730_bank1_irqs __initdata = {
  89         .cpu_type       = OMAP_IRQ_TYPE730,
  90         .start_irq      = 32,
  91         .level_map      = 0xfdb9c1f2,
  92         .base_reg       = OMAP_IH2_BASE,
  93         .mask_reg       = OMAP_IH2_BASE + IRQ_MIR,
  94         .ack_reg        = OMAP_IH2_BASE + IRQ_CONTROL_REG,
  95         .handler        = &omap_offset_irq,     /* IH2 regs at 0x100 offsets */
  96 };
  97
  98 static struct omap_irq_desc omap730_bank2_irqs __initdata = {
  99         .cpu_type       = OMAP_IRQ_TYPE730,
 100         .start_irq      = 64,
 101         .level_map      = 0x800040f3,
 102         .base_reg       = OMAP_IH2_BASE + 0x100,
 103         .mask_reg       = OMAP_IH2_BASE + 0x100 + IRQ_MIR,
 104         .ack_reg        = OMAP_IH2_BASE + IRQ_CONTROL_REG, /* Not replicated */
 105         .handler        = &omap_offset_irq,     /* IH2 regs at 0x100 offsets */
 106 };
 107
 108 /*
 109  * OMAP-1510 interrupt banks
 110  */
 111 static struct omap_irq_desc omap1510_bank0_irqs __initdata = {
 112         .cpu_type       = OMAP_IRQ_TYPE1510,
 113         .start_irq      = 0,
 114         .level_map      = 0xb3febfff,
 115         .base_reg       = OMAP_IH1_BASE,
 116         .mask_reg       = OMAP_IH1_BASE + IRQ_MIR,
 117         .ack_reg        = OMAP_IH1_BASE + IRQ_CONTROL_REG,
 118         .handler        = &omap_offset_irq,     /* IH2 regs at 0x100 offsets */
 119 };
 120
 121 static struct omap_irq_desc omap1510_bank1_irqs __initdata = {
 122         .cpu_type       = OMAP_IRQ_TYPE1510,
 123         .start_irq      = 32,
 124         .level_map      = 0xffbfffed,
 125         .base_reg       = OMAP_IH2_BASE,
 126         .mask_reg       = OMAP_IH2_BASE + IRQ_MIR,
 127         .ack_reg        = OMAP_IH2_BASE + IRQ_CONTROL_REG,
 128         .handler        = &omap_offset_irq,     /* IH2 regs at 0x100 offsets */
 129 };
 130
 131 /*
 132  * OMAP-1610 interrupt banks
 133  */
 134 static struct omap_irq_desc omap1610_bank0_irqs __initdata = {
 135         .cpu_type       = OMAP_IRQ_TYPE1610,
 136         .start_irq      = 0,
 137         .level_map      = 0xb3fefe8f,
 138         .base_reg       = OMAP_IH1_BASE,
 139         .mask_reg       = OMAP_IH1_BASE + IRQ_MIR,
 140         .ack_reg        = OMAP_IH1_BASE + IRQ_CONTROL_REG,
 141         .handler        = &omap_offset_irq,     /* IH2 regs at 0x100 offsets */
 142 };
 143
 144 static struct omap_irq_desc omap1610_bank1_irqs __initdata = {
 145         .cpu_type       = OMAP_IRQ_TYPE1610,
 146         .start_irq      = 32,
 147         .level_map      = 0xfffff7ff,
 148         .base_reg       = OMAP_IH2_BASE,
 149         .mask_reg       = OMAP_IH2_BASE + IRQ_MIR,
 150         .ack_reg        = OMAP_IH2_BASE + IRQ_CONTROL_REG,
 151         .handler        = &omap_offset_irq,     /* IH2 regs at 0x100 offsets */
 152 };
 153
 154 static struct omap_irq_desc omap1610_bank2_irqs __initdata = {
 155         .cpu_type       = OMAP_IRQ_TYPE1610,
 156         .start_irq      = 64,
 157         .level_map      = 0xffffffff,
 158         .base_reg       = OMAP_IH2_BASE + 0x100,
 159         .mask_reg       = OMAP_IH2_BASE + 0x100 + IRQ_MIR,
 160         .ack_reg        = OMAP_IH2_BASE + IRQ_CONTROL_REG, /* Not replicated */
 161         .handler        = &omap_offset_irq,     /* IH2 regs at 0x100 offsets */
 162 };
 163
 164 static struct omap_irq_desc omap1610_bank3_irqs __initdata = {
 165         .cpu_type       = OMAP_IRQ_TYPE1610,
 166         .start_irq      = 96,
 167         .level_map      = 0xffffffff,
 168         .base_reg       = OMAP_IH2_BASE + 0x200,
 169         .mask_reg       = OMAP_IH2_BASE + 0x200 + IRQ_MIR,
 170         .ack_reg        = OMAP_IH2_BASE + IRQ_CONTROL_REG, /* Not replicated */
 171         .handler        = &omap_offset_irq,     /* IH2 regs at 0x100 offsets */
 172 };