arch/arm/mach-versatile/core.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/config.h>
  22 #include <linux/init.h>
  23 #include <linux/device.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/interrupt.h>
  27
  28 #include <asm/system.h>
  29 #include <asm/hardware.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/leds.h>
  33 #include <asm/mach-types.h>
  34 #include <asm/hardware/amba.h>
  35 #include <asm/hardware/amba_clcd.h>
  36
  37 #include <asm/mach/arch.h>
  38 #include <asm/mach/flash.h>
  39 #include <asm/mach/irq.h>
  40 #include <asm/mach/time.h>
  41 #include <asm/mach/map.h>
  42 #ifdef CONFIG_MMC
  43 #include <asm/mach/mmc.h>
  44 #endif
  45
  46 /*
  47  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  48  * is the (PA >> 12).
  49  *
  50  * Setup a VA for the Versatile Vectored Interrupt Controller.
  51  */
  52 #define VA_VIC_BASE              IO_ADDRESS(VERSATILE_VIC_BASE)
  53 #define VA_SIC_BASE              IO_ADDRESS(VERSATILE_SIC_BASE)
  54
  55 static void vic_mask_irq(unsigned int irq)
  56 {
  57         irq -= IRQ_VIC_START;
  58         writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
  59 }
  60
  61 static void vic_unmask_irq(unsigned int irq)
  62 {
  63         irq -= IRQ_VIC_START;
  64         writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE);
  65 }
  66
  67 static struct irqchip vic_chip = {
  68         .ack    = vic_mask_irq,
  69         .mask   = vic_mask_irq,
  70         .unmask = vic_unmask_irq,
  71 };
  72
  73 static void sic_mask_irq(unsigned int irq)
  74 {
  75         irq -= IRQ_SIC_START;
  76         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  77 }
  78
  79 static void sic_unmask_irq(unsigned int irq)
  80 {
  81         irq -= IRQ_SIC_START;
  82         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
  83 }
  84
  85 static struct irqchip sic_chip = {
  86         .ack    = sic_mask_irq,
  87         .mask   = sic_mask_irq,
  88         .unmask = sic_unmask_irq,
  89 };
  90
  91 static void
  92 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
  93 {
  94         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
  95
  96         if (status == 0) {
  97                 do_bad_IRQ(irq, desc, regs);
  98                 return;
  99         }
 100
 101         do {
 102                 irq = ffs(status) - 1;
 103                 status &= ~(1 << irq);
 104
 105                 irq += IRQ_SIC_START;
 106
 107                 desc = irq_desc + irq;
 108                 desc->handle(irq, desc, regs);
 109         } while (status);
 110 }
 111
 112 #if 1
 113 #define IRQ_MMCI0A      IRQ_VICSOURCE22
 114 #define IRQ_MMCI1A      IRQ_VICSOURCE23
 115 #define IRQ_AACI        IRQ_VICSOURCE24
 116 #define IRQ_ETH         IRQ_VICSOURCE25
 117 #define PIC_MASK        0xFFD00000
 118 #else
 119 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
 120 #define IRQ_MMCI1A      IRQ_SIC_MMCI1A
 121 #define IRQ_AACI        IRQ_SIC_AACI
 122 #define IRQ_ETH         IRQ_SIC_ETH
 123 #define PIC_MASK        0
 124 #endif
 125
 126 static void __init versatile_init_irq(void)
 127 {
 128         unsigned int i, value;
 129
 130         /* Disable all interrupts initially. */
 131
 132         writel(0, VA_VIC_BASE + VIC_INT_SELECT);
 133         writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE);
 134         writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
 135         writel(0, VA_VIC_BASE + VIC_IRQ_STATUS);
 136         writel(0, VA_VIC_BASE + VIC_ITCR);
 137         writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR);
 138
 139         /*
 140          * Make sure we clear all existing interrupts
 141          */
 142         writel(0, VA_VIC_BASE + VIC_VECT_ADDR);
 143         for (i = 0; i < 19; i++) {
 144                 value = readl(VA_VIC_BASE + VIC_VECT_ADDR);
 145                 writel(value, VA_VIC_BASE + VIC_VECT_ADDR);
 146         }
 147
 148         for (i = 0; i < 16; i++) {
 149                 value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
 150                 writel(value | VICVectCntl_Enable | i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
 151         }
 152
 153         writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR);
 154
 155         for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) {
 156                 if (i != IRQ_VICSOURCE31) {
 157                         set_irq_chip(i, &vic_chip);
 158                         set_irq_handler(i, do_level_IRQ);
 159                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 160                 }
 161         }
 162
 163         set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
 164         vic_unmask_irq(IRQ_VICSOURCE31);
 165
 166         /* Do second interrupt controller */
 167         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 168
 169         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 170                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
 171                         set_irq_chip(i, &sic_chip);
 172                         set_irq_handler(i, do_level_IRQ);
 173                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 174                 }
 175         }
 176
 177         /*
 178          * Interrupts on secondary controller from 0 to 8 are routed to
 179          * source 31 on PIC.
 180          * Interrupts from 21 to 31 are routed directly to the VIC on
 181          * the corresponding number on primary controller. This is controlled
 182          * by setting PIC_ENABLEx.
 183          */
 184         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 185 }
 186
 187 static struct map_desc versatile_io_desc[] __initdata = {
 188  { IO_ADDRESS(VERSATILE_SYS_BASE),   VERSATILE_SYS_BASE,   SZ_4K,      MT_DEVICE },
 189  { IO_ADDRESS(VERSATILE_SIC_BASE),   VERSATILE_SIC_BASE,   SZ_4K,      MT_DEVICE },
 190  { IO_ADDRESS(VERSATILE_VIC_BASE),   VERSATILE_VIC_BASE,   SZ_4K,      MT_DEVICE },
 191  { IO_ADDRESS(VERSATILE_SCTL_BASE),  VERSATILE_SCTL_BASE,  SZ_4K * 9,  MT_DEVICE },
 192 #ifdef CONFIG_DEBUG_LL
 193  { IO_ADDRESS(VERSATILE_UART0_BASE), VERSATILE_UART0_BASE, SZ_4K,      MT_DEVICE },
 194 #endif
 195 #ifdef FIXME
 196  { PCI_MEMORY_VADDR,                 PHYS_PCI_MEM_BASE,    SZ_16M,     MT_DEVICE },
 197  { PCI_CONFIG_VADDR,                 PHYS_PCI_CONFIG_BASE, SZ_16M,     MT_DEVICE },
 198  { PCI_V3_VADDR,                     PHYS_PCI_V3_BASE,     SZ_512K,    MT_DEVICE },
 199  { PCI_IO_VADDR,                     PHYS_PCI_IO_BASE,     SZ_64K,     MT_DEVICE },
 200 #endif
 201 };
 202
 203 static void __init versatile_map_io(void)
 204 {
 205         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 206 }
 207
 208 #define VERSATILE_REFCOUNTER    (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
 209
 210 /*
 211  * This is the VersatilePB sched_clock implementation.  This has
 212  * a resolution of 41.7ns, and a maximum value of about 179s.
 213  */
 214 unsigned long long sched_clock(void)
 215 {
 216         unsigned long long v;
 217
 218         v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125;
 219         do_div(v, 3);
 220
 221         return v;
 222 }
 223
 224
 225 #define VERSATILE_FLASHCTRL    (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 226
 227 static int versatile_flash_init(void)
 228 {
 229         u32 val;
 230
 231         val = __raw_readl(VERSATILE_FLASHCTRL);
 232         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 233         __raw_writel(val, VERSATILE_FLASHCTRL);
 234
 235         return 0;
 236 }
 237
 238 static void versatile_flash_exit(void)
 239 {
 240         u32 val;
 241
 242         val = __raw_readl(VERSATILE_FLASHCTRL);
 243         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 244         __raw_writel(val, VERSATILE_FLASHCTRL);
 245 }
 246
 247 static void versatile_flash_set_vpp(int on)
 248 {
 249         u32 val;
 250
 251         val = __raw_readl(VERSATILE_FLASHCTRL);
 252         if (on)
 253                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 254         else
 255                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 256         __raw_writel(val, VERSATILE_FLASHCTRL);
 257 }
 258
 259 static struct flash_platform_data versatile_flash_data = {
 260         .map_name               = "cfi_probe",
 261         .width                  = 4,
 262         .init                   = versatile_flash_init,
 263         .exit                   = versatile_flash_exit,
 264         .set_vpp                = versatile_flash_set_vpp,
 265 };
 266
 267 static struct resource versatile_flash_resource = {
 268         .start                  = VERSATILE_FLASH_BASE,
 269         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE,
 270         .flags                  = IORESOURCE_MEM,
 271 };
 272
 273 static struct platform_device versatile_flash_device = {
 274         .name                   = "armflash",
 275         .id                     = 0,
 276         .dev                    = {
 277                 .platform_data  = &versatile_flash_data,
 278         },
 279         .num_resources          = 1,
 280         .resource               = &versatile_flash_resource,
 281 };
 282
 283 static struct resource smc91x_resources[] = {
 284         [0] = {
 285                 .start          = VERSATILE_ETH_BASE,
 286                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 287                 .flags          = IORESOURCE_MEM,
 288         },
 289         [1] = {
 290                 .start          = IRQ_ETH,
 291                 .end            = IRQ_ETH,
 292                 .flags          = IORESOURCE_IRQ,
 293         },
 294 };
 295
 296 static struct platform_device smc91x_device = {
 297         .name           = "smc91x",
 298         .id             = 0,
 299         .num_resources  = ARRAY_SIZE(smc91x_resources),
 300         .resource       = smc91x_resources,
 301 };
 302
 303 #define VERSATILE_SYSMCI        (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 304
 305 #ifdef CONFIG_MMC
 306 static unsigned int mmc_status(struct device *dev)
 307 {
 308         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 309         u32 mask;
 310
 311         if (adev->res.start == VERSATILE_MMCI0_BASE)
 312                 mask = 1;
 313         else
 314                 mask = 2;
 315
 316         return readl(VERSATILE_SYSMCI) & mask;
 317 }
 318
 319 static struct mmc_platform_data mmc0_plat_data = {
 320         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 321         .status         = mmc_status,
 322 };
 323
 324 static struct mmc_platform_data mmc1_plat_data = {
 325         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 326         .status         = mmc_status,
 327 };
 328 #endif
 329
 330 /*
 331  * CLCD support.
 332  */
 333 #define SYS_CLCD_MODE_MASK      (3 << 0)
 334 #define SYS_CLCD_MODE_5551      (0 << 0)
 335 #define SYS_CLCD_MODE_565       (1 << 0)
 336 #define SYS_CLCD_MODE_888       (2 << 0)
 337 #define SYS_CLCD_MODE_LT        (3 << 0)
 338 #define SYS_CLCD_NLCDIOON       (1 << 2)
 339 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 340 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 341 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 342 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 343 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 344 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 345 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 346
 347 static struct clcd_panel vga = {
 348         .mode           = {
 349                 .name           = "VGA",
 350                 .refresh        = 60,
 351                 .xres           = 640,
 352                 .yres           = 480,
 353                 .pixclock       = 39721,
 354                 .left_margin    = 40,
 355                 .right_margin   = 24,
 356                 .upper_margin   = 32,
 357                 .lower_margin   = 11,
 358                 .hsync_len      = 96,
 359                 .vsync_len      = 2,
 360                 .sync           = 0,
 361                 .vmode          = FB_VMODE_NONINTERLACED,
 362         },
 363         .width          = -1,
 364         .height         = -1,
 365         .tim2           = TIM2_BCD | TIM2_IPC,
 366         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 367         .bpp            = 16,
 368 };
 369
 370 static struct clcd_panel sanyo_3_8_in = {
 371         .mode           = {
 372                 .name           = "Sanyo QVGA",
 373                 .refresh        = 116,
 374                 .xres           = 320,
 375                 .yres           = 240,
 376                 .pixclock       = 100000,
 377                 .left_margin    = 6,
 378                 .right_margin   = 6,
 379                 .upper_margin   = 5,
 380                 .lower_margin   = 5,
 381                 .hsync_len      = 6,
 382                 .vsync_len      = 6,
 383                 .sync           = 0,
 384                 .vmode          = FB_VMODE_NONINTERLACED,
 385         },
 386         .width          = -1,
 387         .height         = -1,
 388         .tim2           = TIM2_BCD,
 389         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 390         .bpp            = 16,
 391 };
 392
 393 static struct clcd_panel epson_2_2_in = {
 394         .mode           = {
 395                 .name           = "Epson QCIF",
 396                 .refresh        = 390,
 397                 .xres           = 176,
 398                 .yres           = 220,
 399                 .pixclock       = 62500,
 400                 .left_margin    = 3,
 401                 .right_margin   = 2,
 402                 .upper_margin   = 1,
 403                 .lower_margin   = 0,
 404                 .hsync_len      = 3,
 405                 .vsync_len      = 2,
 406                 .sync           = 0,
 407                 .vmode          = FB_VMODE_NONINTERLACED,
 408         },
 409         .width          = -1,
 410         .height         = -1,
 411         .tim2           = TIM2_BCD | TIM2_IPC,
 412         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 413         .bpp            = 16,
 414 };
 415
 416 /*
 417  * Detect which LCD panel is connected, and return the appropriate
 418  * clcd_panel structure.  Note: we do not have any information on
 419  * the required timings for the 8.4in panel, so we presently assume
 420  * VGA timings.
 421  */
 422 static struct clcd_panel *versatile_clcd_panel(void)
 423 {
 424         unsigned long sys_clcd = IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 425         struct clcd_panel *panel = &vga;
 426         u32 val;
 427
 428         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 429         if (val == SYS_CLCD_ID_SANYO_3_8)
 430                 panel = &sanyo_3_8_in;
 431         else if (val == SYS_CLCD_ID_EPSON_2_2)
 432                 panel = &epson_2_2_in;
 433         else if (val == SYS_CLCD_ID_VGA)
 434                 panel = &vga;
 435         else {
 436                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 437                         val);
 438         }
 439
 440         return &vga;
 441 }
 442
 443 /*
 444  * Disable all display connectors on the interface module.
 445  */
 446 static void versatile_clcd_disable(struct clcd_fb *fb)
 447 {
 448         unsigned long sys_clcd = IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 449         u32 val;
 450
 451         val = readl(sys_clcd);
 452         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 453         writel(val, sys_clcd);
 454 }
 455
 456 /*
 457  * Enable the relevant connector on the interface module.
 458  */
 459 static void versatile_clcd_enable(struct clcd_fb *fb)
 460 {
 461         unsigned long sys_clcd = IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 462         u32 val;
 463
 464         val = readl(sys_clcd);
 465         val &= ~SYS_CLCD_MODE_MASK;
 466
 467         switch (fb->fb.var.green.length) {
 468         case 5:
 469 #if 0
 470                 /*
 471                  * For some undocumented reason, we need to select 565 mode
 472                  * even when using 555 with VGA.  Maybe this is only true
 473                  * for the VGA output and needs to be done for LCD panels?
 474                  * I can't get an explaination from the people who should
 475                  * know.
 476                  */
 477                 val |= SYS_CLCD_MODE_5551;
 478                 break;
 479 #endif
 480         case 6:
 481                 val |= SYS_CLCD_MODE_565;
 482                 break;
 483         case 8:
 484                 val |= SYS_CLCD_MODE_888;
 485                 break;
 486         }
 487
 488         /*
 489          * Set the MUX
 490          */
 491         writel(val, sys_clcd);
 492
 493         /*
 494          * And now enable the PSUs
 495          */
 496         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 497         writel(val, sys_clcd);
 498 }
 499
 500 static unsigned long framesize = SZ_1M;
 501
 502 static int versatile_clcd_setup(struct clcd_fb *fb)
 503 {
 504         dma_addr_t dma;
 505
 506         fb->panel               = versatile_clcd_panel();
 507
 508         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 509                                                     &dma, GFP_KERNEL);
 510         if (!fb->fb.screen_base) {
 511                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 512                 return -ENOMEM;
 513         }
 514
 515         fb->fb.fix.smem_start   = dma;
 516         fb->fb.fix.smem_len     = framesize;
 517
 518         return 0;
 519 }
 520
 521 static void versatile_clcd_remove(struct clcd_fb *fb)
 522 {
 523         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 524                               fb->fb.screen_base, fb->fb.fix.smem_start);
 525 }
 526
 527 static struct clcd_board clcd_plat_data = {
 528         .name           = "Versatile PB",
 529         .check          = clcdfb_check,
 530         .decode         = clcdfb_decode,
 531         .disable        = versatile_clcd_disable,
 532         .enable         = versatile_clcd_enable,
 533         .setup          = versatile_clcd_setup,
 534         .remove         = versatile_clcd_remove,
 535 };
 536
 537 #define AMBA_DEVICE(name,busid,base,plat)                       \
 538 static struct amba_device name##_device = {                     \
 539         .dev            = {                                     \
 540                 .coherent_dma_mask = ~0,                        \
 541                 .bus_id = busid,                                \
 542                 .platform_data = plat,                          \
 543         },                                                      \
 544         .res            = {                                     \
 545                 .start  = VERSATILE_##base##_BASE,              \
 546                 .end    = (VERSATILE_##base##_BASE) + SZ_4K - 1,\
 547                 .flags  = IORESOURCE_MEM,                       \
 548         },                                                      \
 549         .dma_mask       = ~0,                                   \
 550         .irq            = base##_IRQ,                           \
 551         /* .dma         = base##_DMA,*/                         \
 552 }
 553
 554 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 555 #define AACI_DMA        { 0x80, 0x81 }
 556 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 557 #define MMCI0_DMA       { 0x84, 0 }
 558 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
 559 #define KMI0_DMA        { 0, 0 }
 560 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
 561 #define KMI1_DMA        { 0, 0 }
 562 #define UART3_IRQ       { IRQ_SIC_UART3, NO_IRQ }
 563 #define UART3_DMA       { 0x86, 0x87 }
 564 #define SCI1_IRQ        { IRQ_SIC_SCI3, NO_IRQ }
 565 #define SCI1_DMA        { 0x88, 0x89 }
 566 #define MMCI1_IRQ       { IRQ_MMCI1A, IRQ_SIC_MMCI1B }
 567 #define MMCI1_DMA       { 0x85, 0 }
 568
 569 /*
 570  * These devices are connected directly to the multi-layer AHB switch
 571  */
 572 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
 573 #define SMC_DMA         { 0, 0 }
 574 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
 575 #define MPMC_DMA        { 0, 0 }
 576 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
 577 #define CLCD_DMA        { 0, 0 }
 578 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
 579 #define DMAC_DMA        { 0, 0 }
 580
 581 /*
 582  * These devices are connected via the core APB bridge
 583  */
 584 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 585 #define SCTL_DMA        { 0, 0 }
 586 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
 587 #define WATCHDOG_DMA    { 0, 0 }
 588 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
 589 #define GPIO0_DMA       { 0, 0 }
 590 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
 591 #define GPIO1_DMA       { 0, 0 }
 592 #define GPIO2_IRQ       { IRQ_GPIOINT2, NO_IRQ }
 593 #define GPIO2_DMA       { 0, 0 }
 594 #define GPIO3_IRQ       { IRQ_GPIOINT3, NO_IRQ }
 595 #define GPIO3_DMA       { 0, 0 }
 596 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
 597 #define RTC_DMA         { 0, 0 }
 598
 599 /*
 600  * These devices are connected via the DMA APB bridge
 601  */
 602 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
 603 #define SCI_DMA         { 7, 6 }
 604 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
 605 #define UART0_DMA       { 15, 14 }
 606 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
 607 #define UART1_DMA       { 13, 12 }
 608 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
 609 #define UART2_DMA       { 11, 10 }
 610 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
 611 #define SSP_DMA         { 9, 8 }
 612
 613 /* FPGA Primecells */
 614 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 615 #ifdef CONFIG_MMC
 616 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 617 #endif
 618 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 619 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 620 AMBA_DEVICE(uart3, "fpga:09", UART3,    NULL);
 621 AMBA_DEVICE(sci1,  "fpga:0a", SCI1,     NULL);
 622 #ifdef CONFIG_MMC
 623 AMBA_DEVICE(mmc1,  "fpga:0b", MMCI1,    &mmc1_plat_data);
 624 #endif
 625
 626 /* DevChip Primecells */
 627 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
 628 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 629 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 630 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 631 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 632 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 633 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
 634 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
 635 AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    NULL);
 636 AMBA_DEVICE(gpio3, "dev:e7",  GPIO3,    NULL);
 637 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 638 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 639 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 640 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 641 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 642 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
 643
 644 static struct amba_device *amba_devs[] __initdata = {
 645         &dmac_device,
 646         &uart0_device,
 647         &uart1_device,
 648         &uart2_device,
 649         &uart3_device,
 650         &smc_device,
 651         &mpmc_device,
 652         &clcd_device,
 653         &sctl_device,
 654         &wdog_device,
 655         &gpio0_device,
 656         &gpio1_device,
 657         &gpio2_device,
 658         &gpio3_device,
 659         &rtc_device,
 660         &sci0_device,
 661         &ssp0_device,
 662         &aaci_device,
 663 #ifdef CONFIG_MMC
 664         &mmc0_device,
 665 #endif
 666         &kmi0_device,
 667         &kmi1_device,
 668         &sci1_device,
 669 #ifdef CONFIG_MMC
 670         &mmc1_device,
 671 #endif
 672 };
 673
 674 #define VA_LEDS_BASE (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 675
 676 static void versatile_leds_event(led_event_t ledevt)
 677 {
 678         unsigned long flags;
 679         u32 val;
 680
 681         local_irq_save(flags);
 682         val = readl(VA_LEDS_BASE);
 683
 684         switch (ledevt) {
 685         case led_idle_start:
 686                 val = val & ~VERSATILE_SYS_LED0;
 687                 break;
 688
 689         case led_idle_end:
 690                 val = val | VERSATILE_SYS_LED0;
 691                 break;
 692
 693         case led_timer:
 694                 val = val ^ VERSATILE_SYS_LED1;
 695                 break;
 696
 697         case led_halted:
 698                 val = 0;
 699                 break;
 700
 701         default:
 702                 break;
 703         }
 704
 705         writel(val, VA_LEDS_BASE);
 706         local_irq_restore(flags);
 707 }
 708
 709 static void __init versatile_init(void)
 710 {
 711         int i;
 712
 713         platform_device_register(&versatile_flash_device);
 714         platform_device_register(&smc91x_device);
 715
 716         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 717                 struct amba_device *d = amba_devs[i];
 718                 amba_device_register(d, &iomem_resource);
 719         }
 720
 721         leds_event = versatile_leds_event;
 722 }
 723
 724 /*
 725  * Where is the timer (VA)?
 726  */
 727 #define TIMER0_VA_BASE           IO_ADDRESS(VERSATILE_TIMER0_1_BASE)
 728 #define TIMER1_VA_BASE          (IO_ADDRESS(VERSATILE_TIMER0_1_BASE) + 0x20)
 729 #define TIMER2_VA_BASE           IO_ADDRESS(VERSATILE_TIMER2_3_BASE)
 730 #define TIMER3_VA_BASE          (IO_ADDRESS(VERSATILE_TIMER2_3_BASE) + 0x20)
 731 #define VA_IC_BASE               IO_ADDRESS(VERSATILE_VIC_BASE)
 732
 733 /*
 734  * How long is the timer interval?
 735  */
 736 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 737 #if TIMER_INTERVAL >= 0x100000
 738 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)           /* Divide by 256 */
 739 #define TIMER_CTRL      0x88                            /* Enable, Clock / 256 */
 740 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 741 #elif TIMER_INTERVAL >= 0x10000
 742 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 743 #define TIMER_CTRL      0x84                            /* Enable, Clock / 16 */
 744 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 745 #else
 746 #define TIMER_RELOAD    (TIMER_INTERVAL)
 747 #define TIMER_CTRL      0x80                            /* Enable */
 748 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 749 #endif
 750
 751 #define TIMER_CTRL_IE   (1 << 5)        /* Interrupt Enable */
 752
 753 /*
 754  * What does it look like?
 755  */
 756 typedef struct TimerStruct {
 757         unsigned long TimerLoad;
 758         unsigned long TimerValue;
 759         unsigned long TimerControl;
 760         unsigned long TimerClear;
 761 } TimerStruct_t;
 762
 763 extern unsigned long (*gettimeoffset)(void);
 764
 765 /*
 766  * Returns number of ms since last clock interrupt.  Note that interrupts
 767  * will have been disabled by do_gettimeoffset()
 768  */
 769 static unsigned long versatile_gettimeoffset(void)
 770 {
 771         volatile TimerStruct_t *timer0 = (TimerStruct_t *)TIMER0_VA_BASE;
 772         unsigned long ticks1, ticks2, status;
 773
 774         /*
 775          * Get the current number of ticks.  Note that there is a race
 776          * condition between us reading the timer and checking for
 777          * an interrupt.  We get around this by ensuring that the
 778          * counter has not reloaded between our two reads.
 779          */
 780         ticks2 = timer0->TimerValue & 0xffff;
 781         do {
 782                 ticks1 = ticks2;
 783                 status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS);
 784                 ticks2 = timer0->TimerValue & 0xffff;
 785         } while (ticks2 > ticks1);
 786
 787         /*
 788          * Number of ticks since last interrupt.
 789          */
 790         ticks1 = TIMER_RELOAD - ticks2;
 791
 792         /*
 793          * Interrupt pending?  If so, we've reloaded once already.
 794          *
 795          * FIXME: Need to check this is effectively timer 0 that expires
 796          */
 797         if (status & IRQMASK_TIMERINT0_1)
 798                 ticks1 += TIMER_RELOAD;
 799
 800         /*
 801          * Convert the ticks to usecs
 802          */
 803         return TICKS2USECS(ticks1);
 804 }
 805
 806 /*
 807  * IRQ handler for the timer
 808  */
 809 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 810 {
 811         volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *)TIMER0_VA_BASE;
 812
 813         // ...clear the interrupt
 814         timer0->TimerClear = 1;
 815
 816         timer_tick(regs);
 817
 818         return IRQ_HANDLED;
 819 }
 820
 821 static struct irqaction versatile_timer_irq = {
 822         .name           = "Versatile Timer Tick",
 823         .flags          = SA_INTERRUPT,
 824         .handler        = versatile_timer_interrupt
 825 };
 826
 827 /*
 828  * Set up timer interrupt, and return the current time in seconds.
 829  */
 830 void __init versatile_init_time(void)
 831 {
 832         volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *)TIMER0_VA_BASE;
 833         volatile TimerStruct_t *timer1 = (volatile TimerStruct_t *)TIMER1_VA_BASE;
 834         volatile TimerStruct_t *timer2 = (volatile TimerStruct_t *)TIMER2_VA_BASE;
 835         volatile TimerStruct_t *timer3 = (volatile TimerStruct_t *)TIMER3_VA_BASE;
 836
 837         /*
 838          * set clock frequency:
 839          *      VERSATILE_REFCLK is 32KHz
 840          *      VERSATILE_TIMCLK is 1MHz
 841          */
 842         *(volatile unsigned int *)IO_ADDRESS(VERSATILE_SCTL_BASE) |=
 843           ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 844            (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel));
 845
 846         /*
 847          * Initialise to a known state (all timers off)
 848          */
 849         timer0->TimerControl = 0;
 850         timer1->TimerControl = 0;
 851         timer2->TimerControl = 0;
 852         timer3->TimerControl = 0;
 853
 854         timer0->TimerLoad    = TIMER_RELOAD;
 855         timer0->TimerValue   = TIMER_RELOAD;
 856         timer0->TimerControl = TIMER_CTRL | 0x40 | TIMER_CTRL_IE;  /* periodic + IE */
 857
 858         /*
 859          * Make irqs happen for the system timer
 860          */
 861         setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
 862         gettimeoffset = versatile_gettimeoffset;
 863 }
 864
 865 MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
 866         MAINTAINER("ARM Ltd/Deep Blue Solutions Ltd")
 867         BOOT_MEM(0x00000000, 0x101f1000, 0xf11f1000)
 868         BOOT_PARAMS(0x00000100)
 869         MAPIO(versatile_map_io)
 870         INITIRQ(versatile_init_irq)
 871         INITTIME(versatile_init_time)
 872         INIT_MACHINE(versatile_init)
 873 MACHINE_END