arch/arm/mach-versatile/core.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/config.h>
  22 #include <linux/init.h>
  23 #include <linux/device.h>
  24 #include <linux/sysdev.h>
  25
  26 #include <asm/hardware.h>
  27 #include <asm/io.h>
  28 #include <asm/irq.h>
  29 #include <asm/leds.h>
  30 #include <asm/mach-types.h>
  31 #include <asm/hardware/amba.h>
  32
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/flash.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach/map.h>
  37 #ifdef CONFIG_MMC
  38 #include <asm/mach/mmc.h>
  39 #endif
  40
  41 /*
  42  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  43  * is the (PA >> 12).
  44  *
  45  * Setup a VA for the Versatile Vectored Interrupt Controller.
  46  */
  47 #define VA_VIC_BASE              IO_ADDRESS(VERSATILE_VIC_BASE)
  48 #define VA_SIC_BASE              IO_ADDRESS(VERSATILE_SIC_BASE)
  49
  50 static void vic_mask_irq(unsigned int irq)
  51 {
  52         irq -= IRQ_VIC_START;
  53         writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
  54 }
  55
  56 static void vic_unmask_irq(unsigned int irq)
  57 {
  58         irq -= IRQ_VIC_START;
  59         writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE);
  60 }
  61
  62 static struct irqchip vic_chip = {
  63         .ack    = vic_mask_irq,
  64         .mask   = vic_mask_irq,
  65         .unmask = vic_unmask_irq,
  66 };
  67
  68 static void sic_mask_irq(unsigned int irq)
  69 {
  70         irq -= IRQ_SIC_START;
  71         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  72 }
  73
  74 static void sic_unmask_irq(unsigned int irq)
  75 {
  76         irq -= IRQ_SIC_START;
  77         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
  78 }
  79
  80 static struct irqchip sic_chip = {
  81         .ack    = sic_mask_irq,
  82         .mask   = sic_mask_irq,
  83         .unmask = sic_unmask_irq,
  84 };
  85
  86 static void
  87 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
  88 {
  89         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
  90
  91         if (status == 0) {
  92                 do_bad_IRQ(irq, desc, regs);
  93                 return;
  94         }
  95
  96         do {
  97                 irq = ffs(status) - 1;
  98                 status &= ~(1 << irq);
  99
 100                 irq += IRQ_SIC_START;
 101
 102                 desc = irq_desc + irq;
 103                 desc->handle(irq, desc, regs);
 104         } while (status);
 105 }
 106
 107 #if 1
 108 #define IRQ_MMCI0A      IRQ_VICSOURCE22
 109 #define IRQ_MMCI1A      IRQ_VICSOURCE23
 110 #define IRQ_AACI        IRQ_VICSOURCE24
 111 #define IRQ_ETH         IRQ_VICSOURCE25
 112 #define PIC_MASK        0xFFD00000
 113 #else
 114 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
 115 #define IRQ_MMCI1A      IRQ_SIC_MMCI1A
 116 #define IRQ_AACI        IRQ_SIC_AACI
 117 #define IRQ_ETH         IRQ_SIC_ETH
 118 #define PIC_MASK        0
 119 #endif
 120
 121 static void __init versatile_init_irq(void)
 122 {
 123         unsigned int i, value;
 124
 125         /* Disable all interrupts initially. */
 126
 127         writel(0, VA_VIC_BASE + VIC_INT_SELECT);
 128         writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE);
 129         writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
 130         writel(0, VA_VIC_BASE + VIC_IRQ_STATUS);
 131         writel(0, VA_VIC_BASE + VIC_ITCR);
 132         writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR);
 133
 134         /*
 135          * Make sure we clear all existing interrupts
 136          */
 137         writel(0, VA_VIC_BASE + VIC_VECT_ADDR);
 138         for (i = 0; i < 19; i++) {
 139                 value = readl(VA_VIC_BASE + VIC_VECT_ADDR);
 140                 writel(value, VA_VIC_BASE + VIC_VECT_ADDR);
 141         }
 142
 143         for (i = 0; i < 16; i++) {
 144                 value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
 145                 writel(value | VICVectCntl_Enable | i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
 146         }
 147
 148         writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR);
 149
 150         for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) {
 151                 if (i != IRQ_VICSOURCE31) {
 152                         set_irq_chip(i, &vic_chip);
 153                         set_irq_handler(i, do_level_IRQ);
 154                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 155                 }
 156         }
 157
 158         set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
 159         vic_unmask_irq(IRQ_VICSOURCE31);
 160
 161         /* Do second interrupt controller */
 162         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 163
 164         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 165                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
 166                         set_irq_chip(i, &sic_chip);
 167                         set_irq_handler(i, do_level_IRQ);
 168                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 169                 }
 170         }
 171
 172         /*
 173          * Interrupts on secondary controller from 0 to 8 are routed to
 174          * source 31 on PIC.
 175          * Interrupts from 21 to 31 are routed directly to the VIC on
 176          * the corresponding number on primary controller. This is controlled
 177          * by setting PIC_ENABLEx.
 178          */
 179         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 180 }
 181
 182 static struct map_desc versatile_io_desc[] __initdata = {
 183  { IO_ADDRESS(VERSATILE_SYS_BASE),   VERSATILE_SYS_BASE,   SZ_4K,      MT_DEVICE },
 184  { IO_ADDRESS(VERSATILE_SIC_BASE),   VERSATILE_SIC_BASE,   SZ_4K,      MT_DEVICE },
 185  { IO_ADDRESS(VERSATILE_VIC_BASE),   VERSATILE_VIC_BASE,   SZ_4K,      MT_DEVICE },
 186  { IO_ADDRESS(VERSATILE_SCTL_BASE),  VERSATILE_SCTL_BASE,  SZ_4K * 9,  MT_DEVICE },
 187 #ifdef CONFIG_DEBUG_LL
 188  { IO_ADDRESS(VERSATILE_UART0_BASE), VERSATILE_UART0_BASE, SZ_4K,      MT_DEVICE },
 189 #endif
 190 #ifdef FIXME
 191  { PCI_MEMORY_VADDR,                 PHYS_PCI_MEM_BASE,    SZ_16M,     MT_DEVICE },
 192  { PCI_CONFIG_VADDR,                 PHYS_PCI_CONFIG_BASE, SZ_16M,     MT_DEVICE },
 193  { PCI_V3_VADDR,                     PHYS_PCI_V3_BASE,     SZ_512K,    MT_DEVICE },
 194  { PCI_IO_VADDR,                     PHYS_PCI_IO_BASE,     SZ_64K,     MT_DEVICE },
 195 #endif
 196 };
 197
 198 static void __init versatile_map_io(void)
 199 {
 200         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 201 }
 202
 203 #define VERSATILE_REFCOUNTER    (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
 204
 205 /*
 206  * This is the VersatilePB sched_clock implementation.  This has
 207  * a resolution of 41.7ns, and a maximum value of about 179s.
 208  */
 209 unsigned long long sched_clock(void)
 210 {
 211         unsigned long long v;
 212
 213         v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125;
 214         do_div(v, 3);
 215
 216         return v;
 217 }
 218
 219
 220 #define VERSATILE_FLASHCTRL    (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 221
 222 static int versatile_flash_init(void)
 223 {
 224         u32 val;
 225
 226         val = __raw_readl(VERSATILE_FLASHCTRL);
 227         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 228         __raw_writel(val, VERSATILE_FLASHCTRL);
 229
 230         return 0;
 231 }
 232
 233 static void versatile_flash_exit(void)
 234 {
 235         u32 val;
 236
 237         val = __raw_readl(VERSATILE_FLASHCTRL);
 238         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 239         __raw_writel(val, VERSATILE_FLASHCTRL);
 240 }
 241
 242 static void versatile_flash_set_vpp(int on)
 243 {
 244         u32 val;
 245
 246         val = __raw_readl(VERSATILE_FLASHCTRL);
 247         if (on)
 248                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 249         else
 250                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 251         __raw_writel(val, VERSATILE_FLASHCTRL);
 252 }
 253
 254 static struct flash_platform_data versatile_flash_data = {
 255         .map_name               = "cfi_probe",
 256         .width                  = 4,
 257         .init                   = versatile_flash_init,
 258         .exit                   = versatile_flash_exit,
 259         .set_vpp                = versatile_flash_set_vpp,
 260 };
 261
 262 static struct resource versatile_flash_resource = {
 263         .start                  = VERSATILE_FLASH_BASE,
 264         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE,
 265         .flags                  = IORESOURCE_MEM,
 266 };
 267
 268 static struct platform_device versatile_flash_device = {
 269         .name                   = "armflash",
 270         .id                     = 0,
 271         .dev                    = {
 272                 .platform_data  = &versatile_flash_data,
 273         },
 274         .num_resources          = 1,
 275         .resource               = &versatile_flash_resource,
 276 };
 277
 278 static struct resource smc91x_resources[] = {
 279         [0] = {
 280                 .start          = VERSATILE_ETH_BASE,
 281                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 282                 .flags          = IORESOURCE_MEM,
 283         },
 284         [1] = {
 285                 .start          = IRQ_ETH,
 286                 .end            = IRQ_ETH,
 287                 .flags          = IORESOURCE_IRQ,
 288         },
 289 };
 290
 291 static struct platform_device smc91x_device = {
 292         .name           = "smc91x",
 293         .id             = 0,
 294         .num_resources  = ARRAY_SIZE(smc91x_resources),
 295         .resource       = smc91x_resources,
 296 };
 297
 298 #define VERSATILE_SYSMCI        (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 299
 300 #ifdef CONFIG_MMC
 301 static unsigned int mmc_status(struct device *dev)
 302 {
 303         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 304         u32 mask;
 305
 306         if (adev->res.start == VERSATILE_MMCI0_BASE)
 307                 mask = 1;
 308         else
 309                 mask = 2;
 310
 311         return readl(VERSATILE_SYSMCI) & mask;
 312 }
 313
 314 static struct mmc_platform_data mmc0_plat_data = {
 315         .mclk           = 33000000,
 316         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 317         .status         = mmc_status,
 318 };
 319
 320 static struct mmc_platform_data mmc1_plat_data = {
 321         .mclk           = 33000000,
 322         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 323         .status         = mmc_status,
 324 };
 325 #endif
 326
 327 #define AMBA_DEVICE(name,busid,base,plat)                       \
 328 static struct amba_device name##_device = {                     \
 329         .dev            = {                                     \
 330                 .coherent_dma_mask = ~0,                        \
 331                 .bus_id = busid,                                \
 332                 .platform_data = plat,                          \
 333         },                                                      \
 334         .res            = {                                     \
 335                 .start  = VERSATILE_##base##_BASE,              \
 336                 .end    = (VERSATILE_##base##_BASE) + SZ_4K - 1,\
 337                 .flags  = IORESOURCE_MEM,                       \
 338         },                                                      \
 339         .dma_mask       = ~0,                                   \
 340         .irq            = base##_IRQ,                           \
 341         /* .dma         = base##_DMA,*/                         \
 342 }
 343
 344 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 345 #define AACI_DMA        { 0x80, 0x81 }
 346 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 347 #define MMCI0_DMA       { 0x84, 0 }
 348 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
 349 #define KMI0_DMA        { 0, 0 }
 350 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
 351 #define KMI1_DMA        { 0, 0 }
 352 #define UART3_IRQ       { IRQ_SIC_UART3, NO_IRQ }
 353 #define UART3_DMA       { 0x86, 0x87 }
 354 #define SCI1_IRQ        { IRQ_SIC_SCI3, NO_IRQ }
 355 #define SCI1_DMA        { 0x88, 0x89 }
 356 #define MMCI1_IRQ       { IRQ_MMCI1A, IRQ_SIC_MMCI1B }
 357 #define MMCI1_DMA       { 0x85, 0 }
 358
 359 /*
 360  * These devices are connected directly to the multi-layer AHB switch
 361  */
 362 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
 363 #define SMC_DMA         { 0, 0 }
 364 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
 365 #define MPMC_DMA        { 0, 0 }
 366 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
 367 #define CLCD_DMA        { 0, 0 }
 368 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
 369 #define DMAC_DMA        { 0, 0 }
 370
 371 /*
 372  * These devices are connected via the core APB bridge
 373  */
 374 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 375 #define SCTL_DMA        { 0, 0 }
 376 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
 377 #define WATCHDOG_DMA    { 0, 0 }
 378 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
 379 #define GPIO0_DMA       { 0, 0 }
 380 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
 381 #define GPIO1_DMA       { 0, 0 }
 382 #define GPIO2_IRQ       { IRQ_GPIOINT2, NO_IRQ }
 383 #define GPIO2_DMA       { 0, 0 }
 384 #define GPIO3_IRQ       { IRQ_GPIOINT3, NO_IRQ }
 385 #define GPIO3_DMA       { 0, 0 }
 386 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
 387 #define RTC_DMA         { 0, 0 }
 388
 389 /*
 390  * These devices are connected via the DMA APB bridge
 391  */
 392 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
 393 #define SCI_DMA         { 7, 6 }
 394 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
 395 #define UART0_DMA       { 15, 14 }
 396 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
 397 #define UART1_DMA       { 13, 12 }
 398 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
 399 #define UART2_DMA       { 11, 10 }
 400 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
 401 #define SSP_DMA         { 9, 8 }
 402
 403 /* FPGA Primecells */
 404 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 405 #ifdef CONFIG_MMC
 406 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 407 #endif
 408 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 409 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 410 AMBA_DEVICE(uart3, "fpga:09", UART3,    NULL);
 411 AMBA_DEVICE(sci1,  "fpga:0a", SCI1,     NULL);
 412 #ifdef CONFIG_MMC
 413 AMBA_DEVICE(mmc1,  "fpga:0b", MMCI1,    &mmc1_plat_data);
 414 #endif
 415
 416 /* DevChip Primecells */
 417 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
 418 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 419 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     NULL);
 420 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 421 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 422 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 423 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
 424 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
 425 AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    NULL);
 426 AMBA_DEVICE(gpio3, "dev:e7",  GPIO3,    NULL);
 427 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 428 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 429 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 430 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 431 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 432 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
 433
 434 static struct amba_device *amba_devs[] __initdata = {
 435         &dmac_device,
 436         &uart0_device,
 437         &uart1_device,
 438         &uart2_device,
 439         &uart3_device,
 440         &smc_device,
 441         &mpmc_device,
 442         &clcd_device,
 443         &sctl_device,
 444         &wdog_device,
 445         &gpio0_device,
 446         &gpio1_device,
 447         &gpio2_device,
 448         &gpio3_device,
 449         &rtc_device,
 450         &sci0_device,
 451         &ssp0_device,
 452         &aaci_device,
 453 #ifdef CONFIG_MMC
 454         &mmc0_device,
 455 #endif
 456         &kmi0_device,
 457         &kmi1_device,
 458         &sci1_device,
 459 #ifdef CONFIG_MMC
 460         &mmc1_device,
 461 #endif
 462 };
 463
 464 #define VA_LEDS_BASE (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 465
 466 static void versatile_leds_event(led_event_t ledevt)
 467 {
 468         unsigned long flags;
 469         u32 val;
 470
 471         local_irq_save(flags);
 472         val = readl(VA_LEDS_BASE);
 473
 474         switch (ledevt) {
 475         case led_idle_start:
 476                 val = val & ~VERSATILE_SYS_LED0;
 477                 break;
 478
 479         case led_idle_end:
 480                 val = val | VERSATILE_SYS_LED0;
 481                 break;
 482
 483         case led_timer:
 484                 val = val ^ VERSATILE_SYS_LED1;
 485                 break;
 486
 487         case led_halted:
 488                 val = 0;
 489                 break;
 490
 491         default:
 492                 break;
 493         }
 494
 495         writel(val, VA_LEDS_BASE);
 496         local_irq_restore(flags);
 497 }
 498
 499 static void __init versatile_init(void)
 500 {
 501         int i;
 502
 503         platform_add_device(&versatile_flash_device);
 504         platform_add_device(&smc91x_device);
 505
 506         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 507                 struct amba_device *d = amba_devs[i];
 508                 amba_device_register(d, &iomem_resource);
 509         }
 510
 511         leds_event = versatile_leds_event;
 512 }
 513
 514 MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
 515         MAINTAINER("ARM Ltd/Deep Blue Solutions Ltd")
 516         BOOT_MEM(0x00000000, 0x101f1000, 0xf11f1000)
 517         BOOT_PARAMS(0x00000100)
 518         MAPIO(versatile_map_io)
 519         INITIRQ(versatile_init_irq)
 520         INIT_MACHINE(versatile_init)
 521 MACHINE_END