2 * linux/arch/arm/mm/copypage-v6.c
4 * Copyright (C) 2002 Deep Blue Solutions Ltd, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/init.h>
11 #include <linux/spinlock.h>
15 #include <asm/pgtable.h>
16 #include <asm/shmparam.h>
17 #include <asm/tlbflush.h>
23 #define from_address (0xffff8000)
24 #define from_pgprot PAGE_KERNEL
25 #define to_address (0xffffc000)
26 #define to_pgprot PAGE_KERNEL
28 static pte_t *from_pte;
30 static spinlock_t v6_lock = SPIN_LOCK_UNLOCKED;
32 #define DCACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
35 * Copy the user page. No aliasing to deal with so we can just
36 * attack the kernel's existing mapping of these pages.
38 void v6_copy_user_page_nonaliasing(void *kto, const void *kfrom, unsigned long vaddr)
40 copy_page(kto, kfrom);
44 * Clear the user page. No aliasing to deal with so we can just
45 * attack the kernel's existing mapping of this page.
47 void v6_clear_user_page_nonaliasing(void *kaddr, unsigned long vaddr)
53 * Copy the page, taking account of the cache colour.
55 void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned long vaddr)
57 unsigned int offset = DCACHE_COLOUR(vaddr);
58 unsigned long from, to;
61 * Discard data in the kernel mapping for the new page.
62 * FIXME: needs this MCRR to be supported.
64 __asm__("mcrr p15, 0, %1, %0, c6 @ 0xec401f06"
67 "r" ((unsigned long)kto + PAGE_SIZE - L1_CACHE_BYTES)
71 * Now copy the page using the same cache colour as the
72 * pages ultimate destination.
76 set_pte(from_pte + offset, pfn_pte(__pa(kfrom) >> PAGE_SHIFT, from_pgprot));
77 set_pte(to_pte + offset, pfn_pte(__pa(kto) >> PAGE_SHIFT, to_pgprot));
79 from = from_address + (offset << PAGE_SHIFT);
80 to = to_address + (offset << PAGE_SHIFT);
82 flush_tlb_kernel_page(from);
83 flush_tlb_kernel_page(to);
85 copy_page((void *)to, (void *)from);
87 spin_unlock(&v6_lock);
91 * Clear the user page. We need to deal with the aliasing issues,
92 * so remap the kernel page into the same cache colour as the user
95 void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr)
97 unsigned int offset = DCACHE_COLOUR(vaddr);
98 unsigned long to = to_address + (offset << PAGE_SHIFT);
101 * Discard data in the kernel mapping for the new page
102 * FIXME: needs this MCRR to be supported.
104 __asm__("mcrr p15, 0, %1, %0, c6 @ 0xec401f06"
107 "r" ((unsigned long)kaddr + PAGE_SIZE - L1_CACHE_BYTES)
111 * Now clear the page using the same cache colour as
112 * the pages ultimate destination.
116 set_pte(to_pte + offset, pfn_pte(__pa(kaddr) >> PAGE_SHIFT, to_pgprot));
117 flush_tlb_kernel_page(to);
118 clear_page((void *)to);
120 spin_unlock(&v6_lock);
123 struct cpu_user_fns v6_user_fns __initdata = {
124 .cpu_clear_user_page = v6_clear_user_page_nonaliasing,
125 .cpu_copy_user_page = v6_copy_user_page_nonaliasing,
128 static int __init v6_userpage_init(void)
130 if (cache_is_vipt_aliasing()) {
134 pgd = pgd_offset_k(from_address);
135 pmd = pmd_alloc(&init_mm, pgd, from_address);
138 from_pte = pte_alloc_kernel(&init_mm, pmd, from_address);
142 to_pte = pte_alloc_kernel(&init_mm, pmd, to_address);
146 cpu_user.cpu_clear_user_page = v6_clear_user_page_aliasing;
147 cpu_user.cpu_copy_user_page = v6_copy_user_page_aliasing;
153 __initcall(v6_userpage_init);