arch/arm/mm/proc-arm6_7.S

   1 /*
   2  *  linux/arch/arm/mm/proc-arm6,7.S
   3  *
   4  *  Copyright (C) 1997-2000 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  These are the low level assembler for performing cache and TLB
  11  *  functions on the ARM610 & ARM710.
  12  */
  13 #include <linux/linkage.h>
  14 #include <linux/init.h>
  15 #include <asm/assembler.h>
  16 #include <asm/asm-offsets.h>
  17 #include <asm/pgtable-hwdef.h>
  18 #include <asm/pgtable.h>
  19 #include <asm/procinfo.h>
  20 #include <asm/ptrace.h>
  21
  22 ENTRY(cpu_arm6_dcache_clean_area)
  23 ENTRY(cpu_arm7_dcache_clean_area)
  24                 mov     pc, lr
  25
  26 /*
  27  * Function: arm6_7_data_abort ()
  28  *
  29  * Params  : r2 = address of aborted instruction
  30  *         : sp = pointer to registers
  31  *
  32  * Purpose : obtain information about current aborted instruction
  33  *
  34  * Returns : r0 = address of abort
  35  *         : r1 = FSR
  36  */
  37
  38 ENTRY(cpu_arm7_data_abort)
  39         mrc     p15, 0, r1, c5, c0, 0           @ get FSR
  40         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
  41         ldr     r8, [r0]                        @ read arm instruction
  42         tst     r8, #1 << 20                    @ L = 0 -> write?
  43         orreq   r1, r1, #1 << 11                @ yes.
  44         and     r7, r8, #15 << 24
  45         add     pc, pc, r7, lsr #22             @ Now branch to the relevant processing routine
  46         nop
  47
  48 /* 0 */ b       .data_unknown
  49 /* 1 */ mov     pc, lr                          @ swp
  50 /* 2 */ b       .data_unknown
  51 /* 3 */ b       .data_unknown
  52 /* 4 */ b       .data_arm_lateldrpostconst      @ ldr   rd, [rn], #m
  53 /* 5 */ b       .data_arm_lateldrpreconst       @ ldr   rd, [rn, #m]
  54 /* 6 */ b       .data_arm_lateldrpostreg        @ ldr   rd, [rn], rm
  55 /* 7 */ b       .data_arm_lateldrprereg         @ ldr   rd, [rn, rm]
  56 /* 8 */ b       .data_arm_ldmstm                @ ldm*a rn, <rlist>
  57 /* 9 */ b       .data_arm_ldmstm                @ ldm*b rn, <rlist>
  58 /* a */ b       .data_unknown
  59 /* b */ b       .data_unknown
  60 /* c */ mov     pc, lr                          @ ldc   rd, [rn], #m    @ Same as ldr   rd, [rn], #m
  61 /* d */ mov     pc, lr                          @ ldc   rd, [rn, #m]
  62 /* e */ b       .data_unknown
  63 /* f */
  64 .data_unknown:  @ Part of jumptable
  65         mov     r0, r2
  66         mov     r1, r8
  67         mov     r2, sp
  68         bl      baddataabort
  69         b       ret_from_exception
  70
  71 ENTRY(cpu_arm6_data_abort)
  72         mrc     p15, 0, r1, c5, c0, 0           @ get FSR
  73         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
  74         ldr     r8, [r2]                        @ read arm instruction
  75         tst     r8, #1 << 20                    @ L = 0 -> write?
  76         orreq   r1, r1, #1 << 11                @ yes.
  77         and     r7, r8, #14 << 24
  78         teq     r7, #8 << 24                    @ was it ldm/stm
  79         movne   pc, lr
  80
  81 .data_arm_ldmstm:
  82         tst     r8, #1 << 21                    @ check writeback bit
  83         moveq   pc, lr                          @ no writeback -> no fixup
  84         mov     r7, #0x11
  85         orr     r7, r7, #0x1100
  86         and     r6, r8, r7
  87         and     r2, r8, r7, lsl #1
  88         add     r6, r6, r2, lsr #1
  89         and     r2, r8, r7, lsl #2
  90         add     r6, r6, r2, lsr #2
  91         and     r2, r8, r7, lsl #3
  92         add     r6, r6, r2, lsr #3
  93         add     r6, r6, r6, lsr #8
  94         add     r6, r6, r6, lsr #4
  95         and     r6, r6, #15                     @ r6 = no. of registers to transfer.
  96         and     r5, r8, #15 << 16               @ Extract 'n' from instruction
  97         ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
  98         tst     r8, #1 << 23                    @ Check U bit
  99         subne   r7, r7, r6, lsl #2              @ Undo increment
 100         addeq   r7, r7, r6, lsl #2              @ Undo decrement
 101         str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
 102         mov     pc, lr
 103
 104 .data_arm_apply_r6_and_rn:
 105         and     r5, r8, #15 << 16               @ Extract 'n' from instruction
 106         ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
 107         tst     r8, #1 << 23                    @ Check U bit
 108         subne   r7, r7, r6                      @ Undo incrmenet
 109         addeq   r7, r7, r6                      @ Undo decrement
 110         str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
 111         mov     pc, lr
 112
 113 .data_arm_lateldrpreconst:
 114         tst     r8, #1 << 21                    @ check writeback bit
 115         moveq   pc, lr                          @ no writeback -> no fixup
 116 .data_arm_lateldrpostconst:
 117         movs    r2, r8, lsl #20                 @ Get offset
 118         moveq   pc, lr                          @ zero -> no fixup
 119         and     r5, r8, #15 << 16               @ Extract 'n' from instruction
 120         ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
 121         tst     r8, #1 << 23                    @ Check U bit
 122         subne   r7, r7, r2, lsr #20             @ Undo increment
 123         addeq   r7, r7, r2, lsr #20             @ Undo decrement
 124         str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
 125         mov     pc, lr
 126
 127 .data_arm_lateldrprereg:
 128         tst     r8, #1 << 21                    @ check writeback bit
 129         moveq   pc, lr                          @ no writeback -> no fixup
 130 .data_arm_lateldrpostreg:
 131         and     r7, r8, #15                     @ Extract 'm' from instruction
 132         ldr     r6, [sp, r7, lsl #2]            @ Get register 'Rm'
 133         mov     r5, r8, lsr #7                  @ get shift count
 134         ands    r5, r5, #31
 135         and     r7, r8, #0x70                   @ get shift type
 136         orreq   r7, r7, #8                      @ shift count = 0
 137         add     pc, pc, r7
 138         nop
 139
 140         mov     r6, r6, lsl r5                  @ 0: LSL #!0
 141         b       .data_arm_apply_r6_and_rn
 142         b       .data_arm_apply_r6_and_rn       @ 1: LSL #0
 143         nop
 144         b       .data_unknown                   @ 2: MUL?
 145         nop
 146         b       .data_unknown                   @ 3: MUL?
 147         nop
 148         mov     r6, r6, lsr r5                  @ 4: LSR #!0
 149         b       .data_arm_apply_r6_and_rn
 150         mov     r6, r6, lsr #32                 @ 5: LSR #32
 151         b       .data_arm_apply_r6_and_rn
 152         b       .data_unknown                   @ 6: MUL?
 153         nop
 154         b       .data_unknown                   @ 7: MUL?
 155         nop
 156         mov     r6, r6, asr r5                  @ 8: ASR #!0
 157         b       .data_arm_apply_r6_and_rn
 158         mov     r6, r6, asr #32                 @ 9: ASR #32
 159         b       .data_arm_apply_r6_and_rn
 160         b       .data_unknown                   @ A: MUL?
 161         nop
 162         b       .data_unknown                   @ B: MUL?
 163         nop
 164         mov     r6, r6, ror r5                  @ C: ROR #!0
 165         b       .data_arm_apply_r6_and_rn
 166         mov     r6, r6, rrx                     @ D: RRX
 167         b       .data_arm_apply_r6_and_rn
 168         b       .data_unknown                   @ E: MUL?
 169         nop
 170         b       .data_unknown                   @ F: MUL?
 171
 172 /*
 173  * Function: arm6_7_proc_init (void)
 174  *         : arm6_7_proc_fin (void)
 175  *
 176  * Notes   : This processor does not require these
 177  */
 178 ENTRY(cpu_arm6_proc_init)
 179 ENTRY(cpu_arm7_proc_init)
 180                 mov     pc, lr
 181
 182 ENTRY(cpu_arm6_proc_fin)
 183 ENTRY(cpu_arm7_proc_fin)
 184                 mov     r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
 185                 msr     cpsr_c, r0
 186                 mov     r0, #0x31                       @ ....S..DP...M
 187                 mcr     p15, 0, r0, c1, c0, 0           @ disable caches
 188                 mov     pc, lr
 189
 190 ENTRY(cpu_arm6_do_idle)
 191 ENTRY(cpu_arm7_do_idle)
 192                 mov     pc, lr
 193
 194 /*
 195  * Function: arm6_7_switch_mm(unsigned long pgd_phys)
 196  * Params  : pgd_phys   Physical address of page table
 197  * Purpose : Perform a task switch, saving the old processes state, and restoring
 198  *           the new.
 199  */
 200 ENTRY(cpu_arm6_switch_mm)
 201 ENTRY(cpu_arm7_switch_mm)
 202                 mov     r1, #0
 203                 mcr     p15, 0, r1, c7, c0, 0           @ flush cache
 204                 mcr     p15, 0, r0, c2, c0, 0           @ update page table ptr
 205                 mcr     p15, 0, r1, c5, c0, 0           @ flush TLBs
 206                 mov     pc, lr
 207
 208 /*
 209  * Function: arm6_7_set_pte(pte_t *ptep, pte_t pte)
 210  * Params  : r0 = Address to set
 211  *         : r1 = value to set
 212  * Purpose : Set a PTE and flush it out of any WB cache
 213  */
 214                 .align  5
 215 ENTRY(cpu_arm6_set_pte)
 216 ENTRY(cpu_arm7_set_pte)
 217                 str     r1, [r0], #-2048                @ linux version
 218
 219                 eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 220
 221                 bic     r2, r1, #PTE_SMALL_AP_MASK
 222                 bic     r2, r2, #PTE_TYPE_MASK
 223                 orr     r2, r2, #PTE_TYPE_SMALL
 224
 225                 tst     r1, #L_PTE_USER                 @ User?
 226                 orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
 227
 228                 tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
 229                 orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
 230
 231                 tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young
 232                 movne   r2, #0
 233
 234                 str     r2, [r0]                        @ hardware version
 235                 mov     pc, lr
 236
 237 /*
 238  * Function: _arm6_7_reset
 239  * Params  : r0 = address to jump to
 240  * Notes   : This sets up everything for a reset
 241  */
 242 ENTRY(cpu_arm6_reset)
 243 ENTRY(cpu_arm7_reset)
 244                 mov     r1, #0
 245                 mcr     p15, 0, r1, c7, c0, 0           @ flush cache
 246                 mcr     p15, 0, r1, c5, c0, 0           @ flush TLB
 247                 mov     r1, #0x30
 248                 mcr     p15, 0, r1, c1, c0, 0           @ turn off MMU etc
 249                 mov     pc, r0
 250
 251                 __INIT
 252
 253                 .type   __arm6_setup, #function
 254 __arm6_setup:   mov     r0, #0
 255                 mcr     p15, 0, r0, c7, c0              @ flush caches on v3
 256                 mcr     p15, 0, r0, c5, c0              @ flush TLBs on v3
 257                 mov     r0, #0x3d                       @ . ..RS BLDP WCAM
 258                 orr     r0, r0, #0x100                  @ . ..01 0011 1101
 259                 mov     pc, lr
 260                 .size   __arm6_setup, . - __arm6_setup
 261
 262                 .type   __arm7_setup, #function
 263 __arm7_setup:   mov     r0, #0
 264                 mcr     p15, 0, r0, c7, c0              @ flush caches on v3
 265                 mcr     p15, 0, r0, c5, c0              @ flush TLBs on v3
 266                 mcr     p15, 0, r0, c3, c0              @ load domain access register
 267                 mov     r0, #0x7d                       @ . ..RS BLDP WCAM
 268                 orr     r0, r0, #0x100                  @ . ..01 0111 1101
 269                 mov     pc, lr
 270                 .size   __arm7_setup, . - __arm7_setup
 271
 272                 __INITDATA
 273
 274 /*
 275  * Purpose : Function pointers used to access above functions - all calls
 276  *           come through these
 277  */
 278                 .type   arm6_processor_functions, #object
 279 ENTRY(arm6_processor_functions)
 280                 .word   cpu_arm6_data_abort
 281                 .word   cpu_arm6_proc_init
 282                 .word   cpu_arm6_proc_fin
 283                 .word   cpu_arm6_reset
 284                 .word   cpu_arm6_do_idle
 285                 .word   cpu_arm6_dcache_clean_area
 286                 .word   cpu_arm6_switch_mm
 287                 .word   cpu_arm6_set_pte
 288                 .size   arm6_processor_functions, . - arm6_processor_functions
 289
 290 /*
 291  * Purpose : Function pointers used to access above functions - all calls
 292  *           come through these
 293  */
 294                 .type   arm7_processor_functions, #object
 295 ENTRY(arm7_processor_functions)
 296                 .word   cpu_arm7_data_abort
 297                 .word   cpu_arm7_proc_init
 298                 .word   cpu_arm7_proc_fin
 299                 .word   cpu_arm7_reset
 300                 .word   cpu_arm7_do_idle
 301                 .word   cpu_arm7_dcache_clean_area
 302                 .word   cpu_arm7_switch_mm
 303                 .word   cpu_arm7_set_pte
 304                 .size   arm7_processor_functions, . - arm7_processor_functions
 305
 306                 .section ".rodata"
 307
 308                 .type   cpu_arch_name, #object
 309 cpu_arch_name:  .asciz  "armv3"
 310                 .size   cpu_arch_name, . - cpu_arch_name
 311
 312                 .type   cpu_elf_name, #object
 313 cpu_elf_name:   .asciz  "v3"
 314                 .size   cpu_elf_name, . - cpu_elf_name
 315
 316                 .type   cpu_arm6_name, #object
 317 cpu_arm6_name:  .asciz  "ARM6"
 318                 .size   cpu_arm6_name, . - cpu_arm6_name
 319
 320                 .type   cpu_arm610_name, #object
 321 cpu_arm610_name:
 322                 .asciz  "ARM610"
 323                 .size   cpu_arm610_name, . - cpu_arm610_name
 324
 325                 .type   cpu_arm7_name, #object
 326 cpu_arm7_name:  .asciz  "ARM7"
 327                 .size   cpu_arm7_name, . - cpu_arm7_name
 328
 329                 .type   cpu_arm710_name, #object
 330 cpu_arm710_name:
 331                 .asciz  "ARM710"
 332                 .size   cpu_arm710_name, . - cpu_arm710_name
 333
 334                 .align
 335
 336                 .section ".proc.info.init", #alloc, #execinstr
 337
 338                 .type   __arm6_proc_info, #object
 339 __arm6_proc_info:
 340                 .long   0x41560600
 341                 .long   0xfffffff0
 342                 .long   0x00000c1e
 343                 b       __arm6_setup
 344                 .long   cpu_arch_name
 345                 .long   cpu_elf_name
 346                 .long   HWCAP_SWP | HWCAP_26BIT
 347                 .long   cpu_arm6_name
 348                 .long   arm6_processor_functions
 349                 .long   v3_tlb_fns
 350                 .long   v3_user_fns
 351                 .long   v3_cache_fns
 352                 .size   __arm6_proc_info, . - __arm6_proc_info
 353
 354                 .type   __arm610_proc_info, #object
 355 __arm610_proc_info:
 356                 .long   0x41560610
 357                 .long   0xfffffff0
 358                 .long   0x00000c1e
 359                 b       __arm6_setup
 360                 .long   cpu_arch_name
 361                 .long   cpu_elf_name
 362                 .long   HWCAP_SWP | HWCAP_26BIT
 363                 .long   cpu_arm610_name
 364                 .long   arm6_processor_functions
 365                 .long   v3_tlb_fns
 366                 .long   v3_user_fns
 367                 .long   v3_cache_fns
 368                 .size   __arm610_proc_info, . - __arm610_proc_info
 369
 370                 .type   __arm7_proc_info, #object
 371 __arm7_proc_info:
 372                 .long   0x41007000
 373                 .long   0xffffff00
 374                 .long   0x00000c1e
 375                 b       __arm7_setup
 376                 .long   cpu_arch_name
 377                 .long   cpu_elf_name
 378                 .long   HWCAP_SWP | HWCAP_26BIT
 379                 .long   cpu_arm7_name
 380                 .long   arm7_processor_functions
 381                 .long   v3_tlb_fns
 382                 .long   v3_user_fns
 383                 .long   v3_cache_fns
 384                 .size   __arm7_proc_info, . - __arm7_proc_info
 385
 386                 .type   __arm710_proc_info, #object
 387 __arm710_proc_info:
 388                 .long   0x41007100
 389                 .long   0xfff8ff00
 390                 .long   PMD_TYPE_SECT | \
 391                         PMD_SECT_BUFFERABLE | \
 392                         PMD_SECT_CACHEABLE | \
 393                         PMD_BIT4 | \
 394                         PMD_SECT_AP_WRITE | \
 395                         PMD_SECT_AP_READ
 396                 b       __arm7_setup
 397                 .long   cpu_arch_name
 398                 .long   cpu_elf_name
 399                 .long   HWCAP_SWP | HWCAP_26BIT
 400                 .long   cpu_arm710_name
 401                 .long   arm7_processor_functions
 402                 .long   v3_tlb_fns
 403                 .long   v3_user_fns
 404                 .long   v3_cache_fns
 405                 .size   __arm710_proc_info, . - __arm710_proc_info