2 * linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * Copyright (C) 2001 Altera Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm922.
26 * CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
28 #include <linux/linkage.h>
29 #include <linux/config.h>
30 #include <linux/init.h>
31 #include <asm/assembler.h>
32 #include <asm/pgtable.h>
33 #include <asm/procinfo.h>
34 #include <asm/hardware.h>
36 #include <asm/ptrace.h>
37 #include "proc-macros.S"
40 * The size of one data cache line.
42 #define CACHE_DLINESIZE 32
45 * The number of data cache segments.
47 #define CACHE_DSEGMENTS 4
50 * The number of lines in a cache segment.
52 #define CACHE_DENTRIES 64
55 * This is the size at which it becomes more efficient to
56 * clean the whole cache, rather than using the individual
57 * cache line maintainence instructions. (I think this should
60 #define CACHE_DLIMIT 8192
65 * cpu_arm922_proc_init()
67 ENTRY(cpu_arm922_proc_init)
71 * cpu_arm922_proc_fin()
73 ENTRY(cpu_arm922_proc_fin)
75 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
77 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
78 bl arm922_flush_kern_cache_all
80 bl v4wt_flush_kern_cache_all
82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
83 bic r0, r0, #0x1000 @ ...i............
84 bic r0, r0, #0x000e @ ............wca.
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
89 * cpu_arm922_reset(loc)
91 * Perform a soft reset of the system. Put the CPU into the
92 * same state as it would be if it had been reset, and branch
93 * to what would be the reset vector.
95 * loc: location to jump to for soft reset
98 ENTRY(cpu_arm922_reset)
100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c7, c10, 4 @ drain WB
102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
103 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
104 bic ip, ip, #0x000f @ ............wcam
105 bic ip, ip, #0x1100 @ ...i...s........
106 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
110 * cpu_arm922_do_idle()
113 ENTRY(cpu_arm922_do_idle)
114 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
121 * flush_user_cache_all()
123 * Clean and invalidate all cache entries in a particular
126 ENTRY(arm922_flush_user_cache_all)
130 * flush_kern_cache_all()
132 * Clean and invalidate the entire cache.
134 ENTRY(arm922_flush_kern_cache_all)
138 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
139 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
140 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
141 subs r3, r3, #1 << 26
142 bcs 2b @ entries 63 to 0
144 bcs 1b @ segments 7 to 0
146 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
147 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
151 * flush_user_cache_range(start, end, flags)
153 * Clean and invalidate a range of cache entries in the
154 * specified address range.
156 * - start - start address (inclusive)
157 * - end - end address (exclusive)
158 * - flags - vm_flags describing address space
160 ENTRY(arm922_flush_user_cache_range)
162 sub r3, r1, r0 @ calculate total size
163 cmp r3, #CACHE_DLIMIT
164 bhs __flush_whole_cache
166 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
168 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
169 add r0, r0, #CACHE_DLINESIZE
173 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
177 * coherent_kern_range(start, end)
179 * Ensure coherency between the Icache and the Dcache in the
180 * region described by start, end. If you have non-snooping
181 * Harvard caches, you need to implement this function.
183 * - start - virtual start address
184 * - end - virtual end address
186 ENTRY(arm922_coherent_kern_range)
187 bic r0, r0, #CACHE_DLINESIZE - 1
188 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
189 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
190 add r0, r0, #CACHE_DLINESIZE
193 mcr p15, 0, r0, c7, c10, 4 @ drain WB
197 * flush_kern_dcache_page(void *page)
199 * Ensure no D cache aliasing occurs, either with itself or
202 * - addr - page aligned address
204 ENTRY(arm922_flush_kern_dcache_page)
206 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
207 add r0, r0, #CACHE_DLINESIZE
211 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
212 mcr p15, 0, r0, c7, c10, 4 @ drain WB
216 * dma_inv_range(start, end)
218 * Invalidate (discard) the specified virtual address range.
219 * May not write back any entries. If 'start' or 'end'
220 * are not cache line aligned, those lines must be written
223 * - start - virtual start address
224 * - end - virtual end address
228 ENTRY(arm922_dma_inv_range)
229 tst r0, #CACHE_DLINESIZE - 1
230 bic r0, r0, #CACHE_DLINESIZE - 1
231 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
232 tst r1, #CACHE_DLINESIZE - 1
233 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
234 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
235 add r0, r0, #CACHE_DLINESIZE
238 mcr p15, 0, r0, c7, c10, 4 @ drain WB
242 * dma_clean_range(start, end)
244 * Clean the specified virtual address range.
246 * - start - virtual start address
247 * - end - virtual end address
251 ENTRY(arm922_dma_clean_range)
252 bic r0, r0, #CACHE_DLINESIZE - 1
253 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
254 add r0, r0, #CACHE_DLINESIZE
257 mcr p15, 0, r0, c7, c10, 4 @ drain WB
261 * dma_flush_range(start, end)
263 * Clean and invalidate the specified virtual address range.
265 * - start - virtual start address
266 * - end - virtual end address
268 ENTRY(arm922_dma_flush_range)
269 bic r0, r0, #CACHE_DLINESIZE - 1
270 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
271 add r0, r0, #CACHE_DLINESIZE
274 mcr p15, 0, r0, c7, c10, 4 @ drain WB
277 ENTRY(arm922_cache_fns)
278 .long arm922_flush_kern_cache_all
279 .long arm922_flush_user_cache_all
280 .long arm922_flush_user_cache_range
281 .long arm922_coherent_kern_range
282 .long arm922_flush_kern_dcache_page
283 .long arm922_dma_inv_range
284 .long arm922_dma_clean_range
285 .long arm922_dma_flush_range
290 ENTRY(cpu_arm922_dcache_clean_area)
291 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
292 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
293 add r0, r0, #CACHE_DLINESIZE
294 subs r1, r1, #CACHE_DLINESIZE
299 /* =============================== PageTable ============================== */
302 * cpu_arm922_switch_mm(pgd)
304 * Set the translation base pointer to be as described by pgd.
306 * pgd: new page tables
309 ENTRY(cpu_arm922_switch_mm)
311 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
312 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
314 @ && 'Clean & Invalidate whole DCache'
315 @ && Re-written to use Index Ops.
316 @ && Uses registers r1, r3 and ip
318 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 4 segments
319 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
320 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
321 subs r3, r3, #1 << 26
322 bcs 2b @ entries 63 to 0
324 bcs 1b @ segments 7 to 0
326 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
327 mcr p15, 0, ip, c7, c10, 4 @ drain WB
328 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
329 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
333 * cpu_arm922_set_pte(ptep, pte)
335 * Set a PTE and flush it out
338 ENTRY(cpu_arm922_set_pte)
339 str r1, [r0], #-2048 @ linux version
341 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
343 bic r2, r1, #PTE_SMALL_AP_MASK
344 bic r2, r2, #PTE_TYPE_MASK
345 orr r2, r2, #PTE_TYPE_SMALL
347 tst r1, #L_PTE_USER @ User?
348 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
350 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
351 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
353 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
356 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
357 eor r3, r2, #0x0a @ C & small page?
361 str r2, [r0] @ hardware version
363 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
364 mcr p15, 0, r0, c7, c10, 4 @ drain WB
369 .type __arm922_setup, #function
372 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
373 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
374 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
375 mcr p15, 0, r4, c2, c0 @ load page table pointer
376 mov r0, #0x1f @ Domains 0, 1 = client
377 mcr p15, 0, r0, c3, c0 @ load domain access register
378 mrc p15, 0, r0, c1, c0 @ get control register v4
380 * Clear out 'unwanted' bits (then put them in if we need them)
386 bic r0, r0, #0x1000 @ ...0 000. .... 000.
388 * Turn on what we want
391 orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1
393 #ifndef CONFIG_CPU_DCACHE_DISABLE
394 orr r0, r0, #0x0004 @ .... .... .... .1..
396 #ifndef CONFIG_CPU_ICACHE_DISABLE
397 orr r0, r0, #0x1000 @ ...1 .... .... ....
400 .size __arm922_setup, . - __arm922_setup
405 * Purpose : Function pointers used to access above functions - all calls
408 .type arm922_processor_functions, #object
409 arm922_processor_functions:
410 .word v4t_early_abort
411 .word cpu_arm922_proc_init
412 .word cpu_arm922_proc_fin
413 .word cpu_arm922_reset
414 .word cpu_arm922_do_idle
415 .word cpu_arm922_dcache_clean_area
416 .word cpu_arm922_switch_mm
417 .word cpu_arm922_set_pte
418 .size arm922_processor_functions, . - arm922_processor_functions
422 .type cpu_arch_name, #object
425 .size cpu_arch_name, . - cpu_arch_name
427 .type cpu_elf_name, #object
430 .size cpu_elf_name, . - cpu_elf_name
432 .type cpu_arm922_name, #object
435 #ifndef CONFIG_CPU_ICACHE_DISABLE
438 #ifndef CONFIG_CPU_DCACHE_DISABLE
440 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
447 .size cpu_arm922_name, . - cpu_arm922_name
451 .section ".proc.info", #alloc, #execinstr
453 .type __arm922_proc_info,#object
457 .long 0x00000c1e @ mmuflags
461 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
462 .long cpu_arm922_name
463 .long arm922_processor_functions
466 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
467 .long arm922_cache_fns
471 .size __arm922_proc_info, . - __arm922_proc_info