1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/semaphore.h>
9 #include <asm/processor.h>
13 #include <asm/mmu_context.h>
16 #ifdef CONFIG_X86_LOCAL_APIC
17 #include <asm/mpspec.h>
19 #include <mach_apic.h>
22 #include <asm/hypervisor.h>
26 DEFINE_PER_CPU(struct Xgt_desc_struct, cpu_gdt_descr);
27 EXPORT_PER_CPU_SYMBOL(cpu_gdt_descr);
29 struct i386_pda *_cpu_pda[NR_CPUS] __read_mostly;
30 EXPORT_SYMBOL(_cpu_pda);
32 static int cachesize_override __cpuinitdata = -1;
33 static int disable_x86_fxsr __cpuinitdata;
34 static int disable_x86_serial_nr __cpuinitdata = 1;
35 static int disable_x86_sep __cpuinitdata;
37 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
39 extern int disable_pse;
41 static void __cpuinit default_init(struct cpuinfo_x86 * c)
43 /* Not much we can do here... */
44 /* Check if at least it has cpuid */
45 if (c->cpuid_level == -1) {
46 /* No cpuid. It must be an ancient CPU */
48 strcpy(c->x86_model_id, "486");
50 strcpy(c->x86_model_id, "386");
54 static struct cpu_dev __cpuinitdata default_cpu = {
55 .c_init = default_init,
56 .c_vendor = "Unknown",
58 static struct cpu_dev * this_cpu __cpuinitdata = &default_cpu;
60 static int __init cachesize_setup(char *str)
62 get_option (&str, &cachesize_override);
65 __setup("cachesize=", cachesize_setup);
67 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
72 if (cpuid_eax(0x80000000) < 0x80000004)
75 v = (unsigned int *) c->x86_model_id;
76 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
77 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
78 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
79 c->x86_model_id[48] = 0;
81 /* Intel chips right-justify this string for some dumb reason;
82 undo that brain damage */
83 p = q = &c->x86_model_id[0];
89 while ( q <= &c->x86_model_id[48] )
90 *q++ = '\0'; /* Zero-pad the rest */
97 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
99 unsigned int n, dummy, ecx, edx, l2size;
101 n = cpuid_eax(0x80000000);
103 if (n >= 0x80000005) {
104 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
105 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
106 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
107 c->x86_cache_size=(ecx>>24)+(edx>>24);
110 if (n < 0x80000006) /* Some chips just has a large L1. */
113 ecx = cpuid_ecx(0x80000006);
116 /* do processor-specific cache resizing */
117 if (this_cpu->c_size_cache)
118 l2size = this_cpu->c_size_cache(c,l2size);
120 /* Allow user to override all this if necessary. */
121 if (cachesize_override != -1)
122 l2size = cachesize_override;
125 return; /* Again, no L2 cache is possible */
127 c->x86_cache_size = l2size;
129 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
133 /* Naming convention should be: <Name> [(<Codename>)] */
134 /* This table only is used unless init_<vendor>() below doesn't set it; */
135 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
137 /* Look up CPU names by table lookup. */
138 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
140 struct cpu_model_info *info;
142 if ( c->x86_model >= 16 )
143 return NULL; /* Range check */
148 info = this_cpu->c_models;
150 while (info && info->family) {
151 if (info->family == c->x86)
152 return info->model_names[c->x86_model];
155 return NULL; /* Not found */
159 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
161 char *v = c->x86_vendor_id;
165 for (i = 0; i < X86_VENDOR_NUM; i++) {
167 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
168 (cpu_devs[i]->c_ident[1] &&
169 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
172 this_cpu = cpu_devs[i];
179 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
180 printk(KERN_ERR "CPU: Your system may be unstable.\n");
182 c->x86_vendor = X86_VENDOR_UNKNOWN;
183 this_cpu = &default_cpu;
187 static int __init x86_fxsr_setup(char * s)
189 /* Tell all the other CPU's to not use it... */
190 disable_x86_fxsr = 1;
193 * ... and clear the bits early in the boot_cpu_data
194 * so that the bootup process doesn't try to do this
197 clear_bit(X86_FEATURE_FXSR, boot_cpu_data.x86_capability);
198 clear_bit(X86_FEATURE_XMM, boot_cpu_data.x86_capability);
201 __setup("nofxsr", x86_fxsr_setup);
204 static int __init x86_sep_setup(char * s)
209 __setup("nosep", x86_sep_setup);
212 /* Standard macro to see if a specific flag is changeable */
213 static inline int flag_is_changeable_p(u32 flag)
227 : "=&r" (f1), "=&r" (f2)
230 return ((f1^f2) & flag) != 0;
234 /* Probe for the CPUID instruction */
235 static int __cpuinit have_cpuid_p(void)
237 return flag_is_changeable_p(X86_EFLAGS_ID);
240 void __init cpu_detect(struct cpuinfo_x86 *c)
242 /* Get vendor name */
243 cpuid(0x00000000, &c->cpuid_level,
244 (int *)&c->x86_vendor_id[0],
245 (int *)&c->x86_vendor_id[8],
246 (int *)&c->x86_vendor_id[4]);
249 if (c->cpuid_level >= 0x00000001) {
250 u32 junk, tfms, cap0, misc;
251 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
252 c->x86 = (tfms >> 8) & 15;
253 c->x86_model = (tfms >> 4) & 15;
255 c->x86 += (tfms >> 20) & 0xff;
257 c->x86_model += ((tfms >> 16) & 0xF) << 4;
258 c->x86_mask = tfms & 15;
260 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
264 /* Do minimum CPU detection early.
265 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
266 The others are not touched to avoid unwanted side effects.
268 WARNING: this function is only called on the BP. Don't add code here
269 that is supposed to run on all CPUs. */
270 static void __init early_cpu_detect(void)
272 struct cpuinfo_x86 *c = &boot_cpu_data;
274 c->x86_cache_alignment = 32;
281 get_cpu_vendor(c, 1);
284 static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
289 if (have_cpuid_p()) {
290 /* Get vendor name */
291 cpuid(0x00000000, &c->cpuid_level,
292 (int *)&c->x86_vendor_id[0],
293 (int *)&c->x86_vendor_id[8],
294 (int *)&c->x86_vendor_id[4]);
296 get_cpu_vendor(c, 0);
297 /* Initialize the standard set of capabilities */
298 /* Note that the vendor-specific code below might override */
300 /* Intel-defined flags: level 0x00000001 */
301 if ( c->cpuid_level >= 0x00000001 ) {
302 u32 capability, excap;
303 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
304 c->x86_capability[0] = capability;
305 c->x86_capability[4] = excap;
306 c->x86 = (tfms >> 8) & 15;
307 c->x86_model = (tfms >> 4) & 15;
309 c->x86 += (tfms >> 20) & 0xff;
311 c->x86_model += ((tfms >> 16) & 0xF) << 4;
312 c->x86_mask = tfms & 15;
314 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
316 c->apicid = (ebx >> 24) & 0xFF;
318 if (c->x86_capability[0] & (1<<19))
319 c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;
321 /* Have CPUID level 0 only - unheard of */
325 /* AMD-defined flags: level 0x80000001 */
326 xlvl = cpuid_eax(0x80000000);
327 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
328 if ( xlvl >= 0x80000001 ) {
329 c->x86_capability[1] = cpuid_edx(0x80000001);
330 c->x86_capability[6] = cpuid_ecx(0x80000001);
332 if ( xlvl >= 0x80000004 )
333 get_model_name(c); /* Default name */
337 early_intel_workaround(c);
340 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
344 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
346 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
347 /* Disable processor serial number */
349 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
351 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
352 printk(KERN_NOTICE "CPU serial number disabled.\n");
353 clear_bit(X86_FEATURE_PN, c->x86_capability);
355 /* Disabling the serial number may affect the cpuid level */
356 c->cpuid_level = cpuid_eax(0);
360 static int __init x86_serial_nr_setup(char *s)
362 disable_x86_serial_nr = 0;
365 __setup("serialnumber", x86_serial_nr_setup);
370 * This does the hard work of actually picking apart the CPU stuff...
372 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
376 c->loops_per_jiffy = loops_per_jiffy;
377 c->x86_cache_size = -1;
378 c->x86_vendor = X86_VENDOR_UNKNOWN;
379 c->cpuid_level = -1; /* CPUID not detected */
380 c->x86_model = c->x86_mask = 0; /* So far unknown... */
381 c->x86_vendor_id[0] = '\0'; /* Unset */
382 c->x86_model_id[0] = '\0'; /* Unset */
383 c->x86_max_cores = 1;
384 c->x86_clflush_size = 32;
385 memset(&c->x86_capability, 0, sizeof c->x86_capability);
387 if (!have_cpuid_p()) {
388 /* First of all, decide if this is a 486 or higher */
389 /* It's a 486 if we can modify the AC flag */
390 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
398 printk(KERN_DEBUG "CPU: After generic identify, caps:");
399 for (i = 0; i < NCAPINTS; i++)
400 printk(" %08lx", c->x86_capability[i]);
403 if (this_cpu->c_identify) {
404 this_cpu->c_identify(c);
406 printk(KERN_DEBUG "CPU: After vendor identify, caps:");
407 for (i = 0; i < NCAPINTS; i++)
408 printk(" %08lx", c->x86_capability[i]);
413 * Vendor-specific initialization. In this section we
414 * canonicalize the feature flags, meaning if there are
415 * features a certain CPU supports which CPUID doesn't
416 * tell us, CPUID claiming incorrect flags, or other bugs,
417 * we handle them here.
419 * At the end of this section, c->x86_capability better
420 * indicate the features this CPU genuinely supports!
422 if (this_cpu->c_init)
425 /* Disable the PN if appropriate */
426 squash_the_stupid_serial_number(c);
429 * The vendor-specific functions might have changed features. Now
430 * we do "generic changes."
435 clear_bit(X86_FEATURE_TSC, c->x86_capability);
438 if (disable_x86_fxsr) {
439 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
440 clear_bit(X86_FEATURE_XMM, c->x86_capability);
445 clear_bit(X86_FEATURE_SEP, c->x86_capability);
448 clear_bit(X86_FEATURE_PSE, c->x86_capability);
450 if (exec_shield != 0) {
451 #ifdef CONFIG_HIGHMEM64G /* NX implies PAE */
452 if (!test_bit(X86_FEATURE_NX, c->x86_capability))
454 clear_bit(X86_FEATURE_SEP, c->x86_capability);
457 /* If the model name is still unset, do table lookup. */
458 if ( !c->x86_model_id[0] ) {
460 p = table_lookup_model(c);
462 strcpy(c->x86_model_id, p);
465 sprintf(c->x86_model_id, "%02x/%02x",
466 c->x86, c->x86_model);
469 /* Now the feature flags better reflect actual CPU features! */
471 printk(KERN_DEBUG "CPU: After all inits, caps:");
472 for (i = 0; i < NCAPINTS; i++)
473 printk(" %08lx", c->x86_capability[i]);
477 * On SMP, boot_cpu_data holds the common feature set between
478 * all CPUs; so make sure that we indicate which features are
479 * common between the CPUs. The first time this routine gets
480 * executed, c == &boot_cpu_data.
482 if ( c != &boot_cpu_data ) {
483 /* AND the already accumulated flags with these */
484 for ( i = 0 ; i < NCAPINTS ; i++ )
485 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
488 /* Init Machine Check Exception if available. */
491 if (c == &boot_cpu_data)
495 if (c == &boot_cpu_data)
502 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
504 u32 eax, ebx, ecx, edx;
505 int index_msb, core_bits;
507 cpuid(1, &eax, &ebx, &ecx, &edx);
509 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
512 smp_num_siblings = (ebx & 0xff0000) >> 16;
514 if (smp_num_siblings == 1) {
515 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
516 } else if (smp_num_siblings > 1 ) {
518 if (smp_num_siblings > NR_CPUS) {
519 printk(KERN_WARNING "CPU: Unsupported number of the "
520 "siblings %d", smp_num_siblings);
521 smp_num_siblings = 1;
525 index_msb = get_count_order(smp_num_siblings);
526 c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
528 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
531 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
533 index_msb = get_count_order(smp_num_siblings) ;
535 core_bits = get_count_order(c->x86_max_cores);
537 c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
538 ((1 << core_bits) - 1);
540 if (c->x86_max_cores > 1)
541 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
547 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
551 if (c->x86_vendor < X86_VENDOR_NUM)
552 vendor = this_cpu->c_vendor;
553 else if (c->cpuid_level >= 0)
554 vendor = c->x86_vendor_id;
556 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
557 printk("%s ", vendor);
559 if (!c->x86_model_id[0])
560 printk("%d86", c->x86);
562 printk("%s", c->x86_model_id);
564 if (c->x86_mask || c->cpuid_level >= 0)
565 printk(" stepping %02x\n", c->x86_mask);
570 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
573 * We're emulating future behavior.
574 * In the future, the cpu-specific init functions will be called implicitly
575 * via the magic of initcalls.
576 * They will insert themselves into the cpu_devs structure.
577 * Then, when cpu_init() is called, we can just iterate over that array.
580 extern int intel_cpu_init(void);
581 extern int cyrix_init_cpu(void);
582 extern int nsc_init_cpu(void);
583 extern int amd_init_cpu(void);
584 extern int centaur_init_cpu(void);
585 extern int transmeta_init_cpu(void);
586 extern int rise_init_cpu(void);
587 extern int nexgen_init_cpu(void);
588 extern int umc_init_cpu(void);
590 void __init early_cpu_init(void)
597 transmeta_init_cpu();
603 #ifdef CONFIG_DEBUG_PAGEALLOC
604 /* pse is not compatible with on-the-fly unmapping,
605 * disable it even if the cpus claim to support it.
607 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
612 /* We can't move load_gdt to asm/desc.h because it lacks make_lowmen_page_readonly()
613 definition, and as this is still the only user of load_gdt in xen.
619 static void __cpuinit load_gdt(struct Xgt_desc_struct *gdt_descr)
621 unsigned long frames[16];
625 for (va = gdt_descr->address, f = 0;
626 va < gdt_descr->address + gdt_descr->size;
627 va += PAGE_SIZE, f++) {
628 frames[f] = virt_to_mfn(va);
629 make_lowmem_page_readonly(
630 (void *)va, XENFEAT_writable_descriptor_tables);
632 if (HYPERVISOR_set_gdt(frames, gdt_descr->size / 8))
635 #endif /* CONFIG_XEN */
637 /* Make sure %gs is initialized properly in idle threads */
638 struct pt_regs * __devinit idle_regs(struct pt_regs *regs)
640 memset(regs, 0, sizeof(struct pt_regs));
641 regs->xgs = __KERNEL_PDA;
645 static __cpuinit int alloc_gdt(int cpu)
647 struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu);
648 struct desc_struct *gdt;
649 struct i386_pda *pda;
651 gdt = (struct desc_struct *)cpu_gdt_descr->address;
655 * This is a horrible hack to allocate the GDT. The problem
656 * is that cpu_init() is called really early for the boot CPU
657 * (and hence needs bootmem) but much later for the secondary
658 * CPUs, when bootmem will have gone away
660 if (NODE_DATA(0)->bdata->node_bootmem_map) {
661 BUG_ON(gdt != NULL || pda != NULL);
663 gdt = alloc_bootmem_pages(PAGE_SIZE);
664 pda = alloc_bootmem(sizeof(*pda));
665 /* alloc_bootmem(_pages) panics on failure, so no check */
667 memset(gdt, 0, PAGE_SIZE);
668 memset(pda, 0, sizeof(*pda));
670 memcpy(gdt, cpu_gdt_table, GDT_SIZE);
671 cpu_gdt_descr->size = GDT_SIZE;
674 /* GDT and PDA might already have been allocated if
675 this is a CPU hotplug re-insertion. */
677 gdt = (struct desc_struct *)get_zeroed_page(GFP_KERNEL);
680 pda = kmalloc_node(sizeof(*pda), GFP_KERNEL, cpu_to_node(cpu));
682 if (unlikely(!gdt || !pda)) {
683 free_pages((unsigned long)gdt, 0);
689 cpu_gdt_descr->address = (unsigned long)gdt;
695 /* Initial PDA used by boot CPU */
696 struct i386_pda boot_pda = {
699 .pcurrent = &init_task,
702 static inline void set_kernel_gs(void)
704 /* Set %gs for this CPU's PDA. Memory clobber is to create a
705 barrier with respect to any PDA operations, so the compiler
706 doesn't move any before here. */
707 asm volatile ("mov %0, %%gs" : : "r" (__KERNEL_PDA) : "memory");
710 /* Initialize the CPU's GDT and PDA. The boot CPU does this for
711 itself, but secondaries find this done for them. */
712 __cpuinit int init_gdt(int cpu, struct task_struct *idle)
714 struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu);
715 struct desc_struct *gdt;
716 struct i386_pda *pda;
718 /* For non-boot CPUs, the GDT and PDA should already have been
720 if (!alloc_gdt(cpu)) {
721 printk(KERN_CRIT "CPU%d failed to allocate GDT or PDA\n", cpu);
725 gdt = (struct desc_struct *)cpu_gdt_descr->address;
728 BUG_ON(gdt == NULL || pda == NULL);
732 * Initialize the per-CPU GDT with the boot GDT,
733 * and set up the GDT descriptor:
735 memcpy(gdt, cpu_gdt_table, GDT_SIZE);
736 cpu_gdt_descr->size = GDT_SIZE - 1;
741 pack_descriptor((u32 *)&gdt[GDT_ENTRY_PDA].a,
742 (u32 *)&gdt[GDT_ENTRY_PDA].b,
743 (unsigned long)pda, sizeof(*pda) - 1,
744 0x80 | DESCTYPE_S | 0x2, 0); /* present read-write data segment */
746 memset(pda, 0, sizeof(*pda));
748 pda->cpu_number = cpu;
749 pda->pcurrent = idle;
754 void __cpuinit cpu_set_gdt(int cpu)
756 struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu);
758 /* Reinit these anyway, even if they've already been done (on
759 the boot CPU, this will transition from the boot gdt+pda to
761 load_gdt(cpu_gdt_descr);
765 /* Common CPU init for both boot and secondary CPUs */
766 static void __cpuinit _cpu_init(int cpu, struct task_struct *curr)
768 #ifndef CONFIG_X86_NO_TSS
769 struct tss_struct * t = &per_cpu(init_tss, cpu);
771 struct thread_struct *thread = &curr->thread;
773 if (cpu_test_and_set(cpu, cpu_initialized)) {
774 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
775 for (;;) local_irq_enable();
778 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
780 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
781 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
782 if (tsc_disable && cpu_has_tsc) {
783 printk(KERN_NOTICE "Disabling TSC...\n");
784 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
785 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
786 set_in_cr4(X86_CR4_TSD);
789 #ifndef CONFIG_X86_NO_IDT
790 load_idt(&idt_descr);
794 * Set up and load the per-CPU TSS and LDT
796 atomic_inc(&init_mm.mm_count);
797 curr->active_mm = &init_mm;
800 enter_lazy_tlb(&init_mm, curr);
802 load_esp0(t, thread);
803 #ifndef CONFIG_X86_NO_TSS
807 load_LDT(&init_mm.context);
809 #ifdef CONFIG_DOUBLEFAULT
810 /* Set up doublefault TSS pointer in the GDT */
811 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
815 asm volatile ("mov %0, %%fs" : : "r" (0));
817 /* Clear all 6 debug registers: */
826 * Force FPU initialization:
828 current_thread_info()->status = 0;
830 mxcsr_feature_mask_init();
833 /* Entrypoint to initialize secondary CPU */
834 void __cpuinit secondary_cpu_init(void)
836 int cpu = smp_processor_id();
837 struct task_struct *curr = current;
839 _cpu_init(cpu, curr);
843 * cpu_init() initializes state that is per-CPU. Some data is already
844 * initialized (naturally) in the bootstrap process, such as the GDT
845 * and IDT. We reload them nevertheless, this function acts as a
846 * 'CPU state barrier', nothing should get across.
848 void __cpuinit cpu_init(void)
850 int cpu = smp_processor_id();
851 struct task_struct *curr = current;
853 /* Set up the real GDT and PDA, so we can transition from the
855 if (!init_gdt(cpu, curr)) {
856 /* failed to allocate something; not much we can do... */
862 _cpu_init(cpu, curr);
865 #ifdef CONFIG_HOTPLUG_CPU
866 void __cpuinit cpu_uninit(void)
868 int cpu = raw_smp_processor_id();
869 cpu_clear(cpu, cpu_initialized);
872 per_cpu(cpu_tlbstate, cpu).state = 0;
873 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;